Commit | Line | Data |
---|---|---|
86530b38 AT |
1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: n2_err_L2_NotData_NDSP_meu_trap.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define MAIN_PAGE_NUCLEUS_ALSO | |
39 | #define MAIN_PAGE_HV_ALSO | |
40 | ||
41 | #define L2_ERR_STAT_REG 0xAB00000000 | |
42 | #define L2_ERR_ADDR_REG 0xAC00000000 | |
43 | #define L2_NDDM_REG 0xAE00000000 | |
44 | ||
45 | #define TT_SW_Error 0x40 | |
46 | ||
47 | ||
48 | #define ERROR_ADDR 0x20200000 | |
49 | #define TEST_DATA0 0x1000100081c3e008 | |
50 | #define TEST_DATA1 0x2000200081c3e008 | |
51 | #define TEST_DATA2 0x3000300081c3e008 | |
52 | #define L2_ES_W1C_VALUE 0xc03ffff800000000 | |
53 | #define DRAM_ES_W1C_VALUE 0xfe00000000000000 | |
54 | ||
55 | #ifdef L20 | |
56 | #define L2_BANK_ADDR 0x0 | |
57 | #define DRAM_ERR_INJ_REG 0x8400000290 | |
58 | #define DRAM_ERR_STAT_REG 0x8400000280 | |
59 | #endif | |
60 | ||
61 | #ifdef L21 | |
62 | #define L2_BANK_ADDR 0x40 | |
63 | #define DRAM_ERR_INJ_REG 0x8400000290 | |
64 | #define DRAM_ERR_STAT_REG 0x8400000280 | |
65 | #endif | |
66 | ||
67 | #ifdef L22 | |
68 | #define L2_BANK_ADDR 0x80 | |
69 | #define DRAM_ERR_INJ_REG 0x8400001290 | |
70 | #define DRAM_ERR_STAT_REG 0x8400001280 | |
71 | #endif | |
72 | ||
73 | #ifdef L23 | |
74 | #define L2_BANK_ADDR 0xc0 | |
75 | #define DRAM_ERR_INJ_REG 0x8400001290 | |
76 | #define DRAM_ERR_STAT_REG 0x8400001280 | |
77 | #endif | |
78 | #ifdef L24 | |
79 | #define L2_BANK_ADDR 0x100 | |
80 | #define DRAM_ERR_INJ_REG 0x8400002290 | |
81 | #define DRAM_ERR_STAT_REG 0x8400002280 | |
82 | #endif | |
83 | #ifdef L25 | |
84 | #define L2_BANK_ADDR 0x140 | |
85 | #define DRAM_ERR_INJ_REG 0x8400002290 | |
86 | #define DRAM_ERR_STAT_REG 0x8400002280 | |
87 | ||
88 | #endif | |
89 | ||
90 | #ifdef L26 | |
91 | #define L2_BANK_ADDR 0x180 | |
92 | #define DRAM_ERR_INJ_REG 0x8400003290 | |
93 | #define DRAM_ERR_STAT_REG 0x8400003280 | |
94 | ||
95 | #endif | |
96 | ||
97 | #ifdef L27 | |
98 | #define L2_BANK_ADDR 0x1c0 | |
99 | #define DRAM_ERR_INJ_REG 0x8400003290 | |
100 | #define DRAM_ERR_STAT_REG 0x8400003280 | |
101 | ||
102 | #endif | |
103 | ||
104 | #include "hboot.s" | |
105 | #include "asi_s.h" | |
106 | #include "err_defines.h" | |
107 | ||
108 | ||
109 | .text | |
110 | .global main | |
111 | ||
112 | ||
113 | ||
114 | ||
115 | main: | |
116 | ||
117 | ta T_CHANGE_HPRIV | |
118 | ||
119 | ||
120 | disable_l1: | |
121 | ldxa [%g0] ASI_LSU_CONTROL, %l0 | |
122 | ! Remove the lower 2 bits (I-Cache and D-Cache enables) | |
123 | andn %l0, 0x3, %l0 | |
124 | stxa %l0, [%g0] ASI_LSU_CONTROL | |
125 | ||
126 | setx 0x20040000, %l0, %g6 | |
127 | ||
128 | ||
129 | clear_dram_esr_0: | |
130 | ! Clear DRAM Error status register (Bit[63:57] write-1-clear) | |
131 | setx DRAM_ES_W1C_VALUE, %l0, %g4 | |
132 | setx DRAM_ERR_STAT_REG, %l3, %g5 | |
133 | stx %g4, [%g5] | |
134 | ||
135 | set_DRAM_error_inject_ch0: | |
136 | mov 0x602, %l1 ! ECC Mask (2-bit error) | |
137 | mov 0x1, %l2 | |
138 | sllx %l2, DRAM_EI_SSHOT, %l3 | |
139 | Or %l1, %l3, %l1 ! Set single shot ; | |
140 | mov 0x1, %l2 | |
141 | sllx %l2, DRAM_EI_ENB, %l3 | |
142 | or %l1, %l3, %l1 ! Enable error injection for the next write | |
143 | setx DRAM_ERR_INJ_REG, %l3, %g5 | |
144 | stx %l1, [%g5] | |
145 | membar 0x40 | |
146 | ||
147 | !enable_err_reporting: | |
148 | ! setx L2EE_PA0, %l0, %l1 | |
149 | ! ldx [%l1], %l2 | |
150 | ! mov 0x3, %l0 | |
151 | ! or %l2, %l0, %l2 | |
152 | ! stx %l2, [%l1] | |
153 | ||
154 | ! Write 1 to clear L2 Error status registers | |
155 | clear_l2_ESR: | |
156 | setx L2ES_PA0, %l3, %l4 | |
157 | add %l4, L2_BANK_ADDR, %l4 | |
158 | stx %g4, [%l4] | |
159 | nop | |
160 | ||
161 | store_to_L2: | |
162 | setx TEST_DATA1, %l0, %g5 | |
163 | ||
164 | ||
165 | set_L2_Directly_Mapped_Mode: | |
166 | setx L2CS_PA0, %l6, %g1 | |
167 | add %g1, L2_BANK_ADDR, %g1 | |
168 | mov 0x2, %l0 | |
169 | stx %l0, [%g1] | |
170 | ||
171 | ||
172 | store_to_L2_way0: | |
173 | setx 0x2000aa00, %l0, %g2 ! bits [21:18] select way | |
174 | add %g2, L2_BANK_ADDR, %g2 | |
175 | stx %g5, [%g2] | |
176 | stx %g5, [%g2+8] | |
177 | membar #Sync | |
178 | ||
179 | ! Storing to same L2 way0 but different tag,this will write to mcu | |
180 | write_mcu_channel_0: | |
181 | setx 0x1000aa00, %l0, %g3 ! bits [21:18] select way | |
182 | add %g3, L2_BANK_ADDR, %g3 | |
183 | stx %g5, [%g3] | |
184 | stx %g5, [%g3+8] | |
185 | membar #Sync | |
186 | ||
187 | read_error_address_ch0: | |
188 | ldx [%g2], %l1 | |
189 | membar #Sync | |
190 | ||
191 | enable_err_reporting: | |
192 | setx L2EE_PA0, %l0, %l1 | |
193 | add %l1, L2_BANK_ADDR, %l1 | |
194 | ldx [%l1], %l2 | |
195 | mov 0x3, %l0 | |
196 | or %l2, %l0, %l2 | |
197 | stx %l2, [%l1] | |
198 | ||
199 | ||
200 | clr %i7 | |
201 | set 0xf,%l7 | |
202 | loop: | |
203 | inc %i7 | |
204 | cmp %i7,%l7 | |
205 | bne loop | |
206 | nop | |
207 | ||
208 | ||
209 | read_error_address_ch0_meu: | |
210 | ldx [%g2], %l1 | |
211 | membar #Sync | |
212 | ||
213 | miss_for_trap: | |
214 | setx 0x3000ca00, %l3, %g5 | |
215 | add %g5, L2_BANK_ADDR, %g5 | |
216 | ldx [%g5],%g4 ! Store miss to create fill, thus an error trap | |
217 | membar #Sync | |
218 | ||
219 | ||
220 | check_DRAM_ESR_0: | |
221 | setx DRAM_ERR_STAT_REG, %l3, %g5 | |
222 | ldx [%g5], %l6 | |
223 | ||
224 | compute_dram_ESR: | |
225 | setx 0xffffffffffff0000, %l0,%o2 | |
226 | and %l6,%o2,%l6 | |
227 | mov 0x1, %l1 | |
228 | sllx %l1, DRAM_ES_DAU, %l0 | |
229 | ||
230 | verify_dram_ESR: | |
231 | cmp %l0, %l6 | |
232 | bne %xcc, test_fail | |
233 | nop | |
234 | ||
235 | check_L2_ESR_0: | |
236 | setx L2_ERR_STAT_REG, %l3, %g5 | |
237 | add %g5, L2_BANK_ADDR, %g5 | |
238 | ldx [%g5], %l6 | |
239 | ||
240 | compute_L2_ESR: | |
241 | setx 0xfffffffff0000000, %l3, %l0 | |
242 | andcc %l0, %l6, %l5 ! Donot check L2ESR SYND bits | |
243 | mov 0x1, %l1 | |
244 | sllx %l1, L2ES_DAU, %l0 | |
245 | mov 0x1, %l1 | |
246 | sllx %l1, L2ES_VEU, %l2 | |
247 | or %l0, %l2, %l3 | |
248 | ||
249 | verify_L2_ESR: | |
250 | cmp %l6, %l3 | |
251 | bne %xcc, test_fail | |
252 | nop | |
253 | ||
254 | check_notData_reg: | |
255 | setx L2_NDDM_REG, %l3, %g5 | |
256 | add %g5, L2_BANK_ADDR, %g5 | |
257 | ldx [%g5], %l6 | |
258 | ||
259 | compute_notData_reg: | |
260 | setx 0xa00002000aa00, %l0, %l1 | |
261 | add %l1, L2_BANK_ADDR, %l1 | |
262 | setx 0xffffffffffff0, %l0,%o2 | |
263 | and %l6, %o2, %l6 | |
264 | cmp %l6, %l1 | |
265 | bne %xcc, test_fail | |
266 | nop | |
267 | ||
268 | setx L2EA_PA0, %l2, %l3 | |
269 | add %l3, L2_BANK_ADDR, %l3 | |
270 | check_l2_EAR: | |
271 | ldx [%l3], %l4 | |
272 | setx 0x2000aa00, %l0, %l1 ! bits [21:18] select way | |
273 | add %l1, L2_BANK_ADDR, %l1 | |
274 | ||
275 | setx 0xffffffffc0, %l0,%o2 ! Error address is the physical address of the cache line (PA[39:6]) | |
276 | and %l4, %o2, %l4 | |
277 | cmp %l4, %l1 | |
278 | bne %xcc, test_fail | |
279 | nop | |
280 | ||
281 | ||
282 | ba test_pass | |
283 | nop | |
284 | ||
285 | /******************************************************* | |
286 | * Exit code | |
287 | *******************************************************/ | |
288 | ||
289 | test_pass: | |
290 | ta T_GOOD_TRAP | |
291 | ||
292 | ||
293 | test_fail: | |
294 | ta T_BAD_TRAP | |
295 |