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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: n2_err_L2_trp_pndng_sec_errpkt.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap | |
39 | ||
40 | #define MAIN_PAGE_HV_ALSO | |
41 | ||
42 | #define L2_ENTRY_PA 0x517590000 | |
43 | #define TEST_DATA 0x555555555555555 | |
44 | #define L2_ES_W1C_VALUE 0xc03ffff800000000 | |
45 | #define REG_PSTATE_IE 0x2 | |
46 | ||
47 | ||
48 | #include "hboot.s" | |
49 | #include "asi_s.h" | |
50 | #include "err_defines.h" | |
51 | ||
52 | .text | |
53 | .global main | |
54 | .global My_Corrected_ECC_error_trap | |
55 | ||
56 | ||
57 | main: | |
58 | ||
59 | ||
60 | ! Boot code does not provide TLB translation for IO address space | |
61 | ta T_CHANGE_HPRIV | |
62 | ||
63 | setx L2_ES_W1C_VALUE, %l0, %g4 | |
64 | ||
65 | !PSTATE.IE is set to 0 | |
66 | keep_trap_pending: | |
67 | rdpr %pstate,%g1 | |
68 | wrpr %g1,REG_PSTATE_IE,%pstate | |
69 | rdpr %pstate,%g1 | |
70 | ||
71 | ||
72 | ! Now access L2 control and status registers | |
73 | disable_l1: | |
74 | ldxa [%g0] ASI_LSU_CONTROL, %l0 | |
75 | ! Remove the lower 2 bits (I-Cache and D-Cache enables) | |
76 | andn %l0, 0x3, %l0 | |
77 | stxa %l0, [%g0] ASI_LSU_CONTROL | |
78 | ||
79 | ||
80 | enable_err_reporting: | |
81 | setx L2EE_PA0, %l0, %l1 | |
82 | ldx [%l1], %l2 | |
83 | mov 0x1, %l0 | |
84 | or %l2, %l0, %l2 | |
85 | stx %l2, [%l1] | |
86 | ||
87 | ||
88 | ! Write 1 to clear L2 Error status registers | |
89 | ||
90 | clear_l2_ESR: | |
91 | setx L2ES_PA0, %l3, %l4 | |
92 | stx %g4, [%l4] | |
93 | nop | |
94 | ||
95 | ||
96 | set_L2_Directly_Mapped_Mode: | |
97 | setx L2CS_PA0, %l6, %g1 | |
98 | mov 0x2, %l0 | |
99 | stx %l0, [%g1] | |
100 | ||
101 | ||
102 | store_to_L2_way0: | |
103 | setx TEST_DATA, %l0, %g5 | |
104 | setx 0x202000aa00, %l0, %g1 | |
105 | stx %g5, [%g1] | |
106 | stx %g5, [%g1+8] | |
107 | membar #Sync | |
108 | ||
109 | ||
110 | way_found: | |
111 | ! Read L2 Data Diag - %g2 has the "way" | |
112 | ! Addressing: [39:32] See PRM, [22] odd/even word, [21:18] way, [17:8] set, [7:6] bank, [5:3] D-word, [2:0] = 0 | |
113 | setx 0x3fff8, %l0, %l2 ! Mask for extracting [17:3] | |
114 | and %g1, %l2, %g5 | |
115 | ||
116 | mov 0xa3, %l0 | |
117 | sllx %l0, 32, %l0 ! Bits [39:32] | |
118 | or %g5, %l0, %g5 ! %g5 has L2 Data Diag addressing | |
119 | ||
120 | ||
121 | read_l2_data_diag: | |
122 | ldx [%g5], %g6 | |
123 | ||
124 | ! Flip one bit from the data field | |
125 | xor %g6, 0x80, %g6 ! save on %g6 for future reference | |
126 | write_back_with_error: | |
127 | stx %g6, [%g5] | |
128 | ||
129 | ||
130 | ||
131 | ! Now do another store with the same index but different tag - to force a Write-Back | |
132 | error_address: | |
133 | mov 0x1, %l0 | |
134 | sllx %l0, 28, %l0 | |
135 | xor %g1, %l0, %l1 ! Flip bit 28 of previous L2 entry PA | |
136 | ||
137 | ! This should cause L2 LDWC (bit 51) | |
138 | store_to_L2_with_error: | |
139 | st %g5, [%l1] | |
140 | membar #Sync | |
141 | ||
142 | ! Compute expected value of L2 error status register | |
143 | compute_expected_L2_ESR: | |
144 | mov 0x1, %l1 | |
145 | sllx %l1, L2ES_LDWC, %l0 | |
146 | sllx %l1, L2ES_VEC, %l3 ! VEC bit | |
147 | or %l0, %l3, %l0 | |
148 | ! No RW bit or Syndrome field for LDWC - %l0 has expected value | |
149 | ||
150 | check_l2_ESR: | |
151 | setx L2ES_PA0, %l2, %l3 | |
152 | ldx [%l3], %l4 | |
153 | ||
154 | cmp %l4, %l0 | |
155 | bne test_fail | |
156 | nop | |
157 | ||
158 | Clear_l2_ESR_LTC: | |
159 | setx L2_ES_W1C_VALUE, %l0, %l1 | |
160 | setx L2ES_PA0, %l6, %g2 | |
161 | stx %l1, [%g2] | |
162 | ||
163 | ||
164 | L2_diag_load_TAg: | |
165 | setx 0x3ffff8, %l0, %l2 ! Mask for extracting [21:3] | |
166 | and %g1, %l2, %g5 !g2 has L2 PA, | |
167 | ||
168 | mov 0xa4, %l0 | |
169 | sllx %l0, 32, %l0 ! Bits [39:32] | |
170 | or %g5, %l0, %g5 ! %g5 has L2 Data Diag addressing | |
171 | ||
172 | ldx [%g5], %g6 | |
173 | membar #Sync | |
174 | ||
175 | ! Flip one bits to inject error | |
176 | xor %g6, 0x200, %g6 | |
177 | stx %g6, [%g5] | |
178 | membar #Sync | |
179 | ||
180 | !This should cause LTC | |
181 | read_back_LTC_InESR: !Load to L2 again to get the LTC logged in ESR | |
182 | setx 0x202000aa00, %l0, %g2 | |
183 | ldx [%g2], %l6 | |
184 | membar #Sync | |
185 | ||
186 | read_back_Send_Trap: !Load miss to L2 again to get the error trap | |
187 | setx 0x202000ba00, %l0, %g2 | |
188 | ldx [%g2], %l6 | |
189 | membar #Sync | |
190 | ||
191 | compute_error_LTC: | |
192 | mov 0x1, %l1 | |
193 | sllx %l1, L2ES_LTC, %l7 | |
194 | sllx %l1, L2ES_VEC, %l3 | |
195 | or %l7, %l3, %l7 | |
196 | ||
197 | ||
198 | check_l2_ESR_LTC: | |
199 | setx L2ES_PA0, %l6, %g1 | |
200 | ldx [%g1], %l4 | |
201 | membar #Sync | |
202 | ||
203 | cmp %l7, %l4 | |
204 | !bne test_fail | |
205 | nop | |
206 | !PSTATE.IE is set to 0 | |
207 | release_trap: | |
208 | rdpr %pstate,%g1 | |
209 | wrpr %g1,REG_PSTATE_IE,%pstate | |
210 | rdpr %pstate,%g1 | |
211 | ||
212 | nop | |
213 | nop | |
214 | nop | |
215 | nop | |
216 | nop | |
217 | ||
218 | ! Check if a Corrected ECC Trap happened | |
219 | check_error_trap: | |
220 | setx EXECUTED, %l1, %l0 | |
221 | cmp %o0, %l0 | |
222 | bne test_fail | |
223 | nop | |
224 | mov TT_Corrected_ECC, %l0 | |
225 | cmp %o1, %l0 | |
226 | bne test_fail | |
227 | nop | |
228 | ||
229 | ||
230 | ba test_pass | |
231 | nop | |
232 | ||
233 | My_Corrected_ECC_error_trap: | |
234 | ! Signal trap taken | |
235 | setx EXECUTED, %l0, %o0 | |
236 | ! save trap type value | |
237 | rdpr %tt, %o1 | |
238 | retry | |
239 | nop | |
240 | /******************************************************* | |
241 | * Exit code | |
242 | *******************************************************/ | |
243 | ||
244 | test_pass: | |
245 | ta T_GOOD_TRAP | |
246 | ||
247 | test_fail: | |
248 | ta T_BAD_TRAP | |
249 |