[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / l2 / n2_err_dram_DAU_ld_trap_L2_Off.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: n2_err_dram_DAU_ld_trap_L2_Off.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO

#define  L2_ERR_STAT_REG    0xAB00000000
#define  L2_ERR_ADDR_REG    0xAC00000000

#define  TEST_DATA0         0x1000100081c3e008
#define  TEST_DATA1         0x2000200081c3e008
#define  TEST_DATA2         0x3000300081c3e008
#define  L2_ES_W1C_VALUE    0xc03ffff800000000
#define  DRAM_ES_W1C_VALUE  0xfe00000000000000

#ifdef MCU0
#define L2_BANK_ADDR        0x0       
#define MCU_BANK_ADDR       0x0
#define  DRAM_ERR_INJ_REG   0x8400000290
#define  DRAM_ERR_STAT_REG  0x8400000280
#define	 ERROR_ADDR	    0x20200000
#endif

#ifdef MCU1
#define L2_BANK_ADDR        0x80
#define MCU_BANK_ADDR       0x80
#define  DRAM_ERR_INJ_REG   0x8400001290
#define  DRAM_ERR_STAT_REG  0x8400001280


#endif

#ifdef MCU2
#define L2_BANK_ADDR        0x100
#define MCU_BANK_ADDR       0x100
#define  DRAM_ERR_INJ_REG   0x8400002290
#define  DRAM_ERR_STAT_REG  0x8400002280
#define  ERROR_ADDR         0x20200100

#endif

#ifdef MCU3
#define L2_BANK_ADDR        0x180
#define MCU_BANK_ADDR       0x180
#define  DRAM_ERR_INJ_REG   0x8400003290
#define  DRAM_ERR_STAT_REG  0x8400003280


#endif


#include "hboot.s"
#include "asi_s.h"
#include "err_defines.h"


.text
.global  main
.global  My_Corrected_ECC_error_trap


main:
  ta T_CHANGE_HPRIV
disable_l1:
  ldxa  [%g0] ASI_LSU_CONTROL, %l0
  ! Remove the lower 2 bits (I-Cache and D-Cache enables)
  andn  %l0, 0x3, %l0
  stxa  %l0, [%g0] ASI_LSU_CONTROL


clear_dram_esr_0:
  ! Clear DRAM Error status register (Bit[63:57] write-1-clear)
  setx  DRAM_ES_W1C_VALUE, %l0, %l5
  setx  DRAM_ERR_STAT_REG, %l3, %g5  
!  add   %g5, MCU_BANK_ADDR, %g5
  stx   %l5, [%g5]

set_DRAM_error_inject_ch0:
  mov   0x606, %l1                ! ECC Mask (Multi-bit error)
  mov   0x1, %l2 		
  sllx  %l2, DRAM_EI_SSHOT, %l3
  Or    %l1, %l3, %l1           ! Set single shot ; 
  mov   0x1, %l2
  sllx  %l2, DRAM_EI_ENB, %l3
  or    %l1, %l3, %l1           ! Enable error injection for the next write
  setx  DRAM_ERR_INJ_REG, %l3, %g6 
!  add   %g6, MCU_BANK_ADDR, %g6
  stx   %l1, [%g6]
  membar 0x40

enable_err_reporting:
  setx L2EE_PA0, %l0, %l1
  add   %l1, L2_BANK_ADDR, %l1
  ldx  [%l1], %l2
  mov  0x3, %l0
  or   %l2, %l0, %l2
  stx  %l2, [%l1]


  ! Write 1 to clear L2 Error status registers
clear_l2_ESR:
  setx  L2ES_PA0, %l3, %l4
  add   %l4, L2_BANK_ADDR, %l4
  stx   %l5, [%l4]
  nop

set_L2_Off_Mode:
  setx  L2CS_PA0, %l6, %g1
  add   %g1, L2_BANK_ADDR, %g1
  mov   0x1, %l0
  stx   %l0, [%g1]

  
store_to_L2_way0:
  setx  0x2200aa00, %l0, %g2  ! bits [21:18] select way
  add   %g2, L2_BANK_ADDR, %g2
  stx %g5, [%g2]
  membar #Sync
read_error_address_ch0:
  ldx   [%g2], %l1
  membar #Sync


! Storing to same L2 way0 but different tag,this will write to mcu
write_mcu_channel_0:
  setx  0x2100aa00, %l0, %g3 ! bits [21:18] select way
  add   %g3, L2_BANK_ADDR, %g3
  stx %g5, [%g3]
  membar #Sync

/**
*read_error_address_ch0:
*  ldx   [%g2], %l1
*  membar #Sync
*!  ldx   [%g3], %l2
*!  membar #Sync
**/

   
check_DRAM_ESR_0:
  setx  DRAM_ERR_STAT_REG, %l3, %g5  
!  add   %g5, MCU_BANK_ADDR, %g5
  ldx   [%g5], %l6
  setx  0xffc0000000000000, %l0,%o2
  and  %l6,%o2,%l6


compute_dram_ESR:
  mov   0x1, %l1
  sllx  %l1, DRAM_ES_DAU, %l0


verify_dram_ESR:
  cmp   %l0, %l6
  bne   %xcc, test_fail
  nop

check_L2_ESR_0:
  setx  L2_ERR_STAT_REG, %l3, %g5  
  add   %g5, L2_BANK_ADDR, %g5
  ldx   [%g5], %l6

compute_L2_ESR:
  setx  0xfffffffff0000000, %l3, %l0
  andcc %l0, %l6, %l0                  ! Donot check L2ESR SYND bits
  mov   0x1, %l1
  sllx  %l1, L2ES_DAU, %l0
  mov   0x1, %l1
  sllx  %l1, L2ES_VEU, %l2
  or    %l0, %l2, %l3

verify_L2_ESR:
  cmp   %l6, %l3
  bne   %xcc, test_fail
  nop


  setx  L2EA_PA0, %l2, %l3
  add   %l3, L2_BANK_ADDR, %l3
check_l2_EAR:
  ldx   [%l3], %l4
  ! Error address is the physical address of the cache line (PA[5:0] 0)
  setx  0x2200aa00, %l0, %g2  ! bits [21:18] select way
  add   %g2, L2_BANK_ADDR, %g2

  setx  0xffffffffc0, %l0,%o2
  and  %l4, %o2, %l4
  cmp   %l4, %g2
  bne   %xcc, test_fail
  nop

check_Corr_err_trap:
  ! Check if a Corrected ECC Error Trap happened
  set   EXECUTED, %l0
  cmp   %o0, %l0
  bne   test_fail
  nop
  mov   TT_Data_Access_Error, %l0
  cmp   %o1, %l0
  bne   test_fail
  nop


  ba    test_pass
  nop

My_Corrected_ECC_error_trap:

!My_Recoverable_Sw_error_trap:
  ! Signal trap taken
  setx  EXECUTED, %l0, %o0
  ! save trap type value
  rdpr  %tt, %o1
  retry
  nop


/*******************************************************
 * Exit code
 *******************************************************/

test_pass:
ta  T_GOOD_TRAP


test_fail:
ta  T_BAD_TRAP
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: n2_err_dram_DAU_ld_trap_L2_Off.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define MAIN_PAGE_NUCLEUS_ALSO
	39	#define MAIN_PAGE_HV_ALSO
	40
	41	#define L2_ERR_STAT_REG 0xAB00000000
	42	#define L2_ERR_ADDR_REG 0xAC00000000
	43
	44	#define TEST_DATA0 0x1000100081c3e008
	45	#define TEST_DATA1 0x2000200081c3e008
	46	#define TEST_DATA2 0x3000300081c3e008
	47	#define L2_ES_W1C_VALUE 0xc03ffff800000000
	48	#define DRAM_ES_W1C_VALUE 0xfe00000000000000
	49
	50	#ifdef MCU0
	51	#define L2_BANK_ADDR 0x0
	52	#define MCU_BANK_ADDR 0x0
	53	#define DRAM_ERR_INJ_REG 0x8400000290
	54	#define DRAM_ERR_STAT_REG 0x8400000280
	55	#define ERROR_ADDR 0x20200000
	56	#endif
	57
	58	#ifdef MCU1
	59	#define L2_BANK_ADDR 0x80
	60	#define MCU_BANK_ADDR 0x80
	61	#define DRAM_ERR_INJ_REG 0x8400001290
	62	#define DRAM_ERR_STAT_REG 0x8400001280
	63
	64
65	#endif
66
67	#ifdef MCU2
68	#define L2_BANK_ADDR 0x100
69	#define MCU_BANK_ADDR 0x100
70	#define DRAM_ERR_INJ_REG 0x8400002290
71	#define DRAM_ERR_STAT_REG 0x8400002280
72	#define ERROR_ADDR 0x20200100
73
74	#endif
75
76	#ifdef MCU3
77	#define L2_BANK_ADDR 0x180
78	#define MCU_BANK_ADDR 0x180
79	#define DRAM_ERR_INJ_REG 0x8400003290
80	#define DRAM_ERR_STAT_REG 0x8400003280
81
82
83	#endif
84
85
86	#include "hboot.s"
87	#include "asi_s.h"
88	#include "err_defines.h"
89
90
91	.text
92	.global main
93	.global My_Corrected_ECC_error_trap
94
95
96
97	main:
98	ta T_CHANGE_HPRIV
99	disable_l1:
100	ldxa [%g0] ASI_LSU_CONTROL, %l0
101	! Remove the lower 2 bits (I-Cache and D-Cache enables)
102	andn %l0, 0x3, %l0
103	stxa %l0, [%g0] ASI_LSU_CONTROL
104
105
106	clear_dram_esr_0:
107	! Clear DRAM Error status register (Bit[63:57] write-1-clear)
108	setx DRAM_ES_W1C_VALUE, %l0, %l5
109	setx DRAM_ERR_STAT_REG, %l3, %g5
110	! add %g5, MCU_BANK_ADDR, %g5
111	stx %l5, [%g5]
112
113	set_DRAM_error_inject_ch0:
114	mov 0x606, %l1 ! ECC Mask (Multi-bit error)
115	mov 0x1, %l2
116	sllx %l2, DRAM_EI_SSHOT, %l3
117	Or %l1, %l3, %l1 ! Set single shot ;
118	mov 0x1, %l2
119	sllx %l2, DRAM_EI_ENB, %l3
120	or %l1, %l3, %l1 ! Enable error injection for the next write
121	setx DRAM_ERR_INJ_REG, %l3, %g6
122	! add %g6, MCU_BANK_ADDR, %g6
123	stx %l1, [%g6]
124	membar 0x40
125
126	enable_err_reporting:
127	setx L2EE_PA0, %l0, %l1
128	add %l1, L2_BANK_ADDR, %l1
129	ldx [%l1], %l2
130	mov 0x3, %l0
131	or %l2, %l0, %l2
132	stx %l2, [%l1]
133
134
135	! Write 1 to clear L2 Error status registers
136	clear_l2_ESR:
137	setx L2ES_PA0, %l3, %l4
138	add %l4, L2_BANK_ADDR, %l4
139	stx %l5, [%l4]
140	nop
141
142	set_L2_Off_Mode:
143	setx L2CS_PA0, %l6, %g1
144	add %g1, L2_BANK_ADDR, %g1
145	mov 0x1, %l0
146	stx %l0, [%g1]
147
148
149	store_to_L2_way0:
150	setx 0x2200aa00, %l0, %g2 ! bits [21:18] select way
151	add %g2, L2_BANK_ADDR, %g2
152	stx %g5, [%g2]
153	membar #Sync
154	read_error_address_ch0:
155	ldx [%g2], %l1
156	membar #Sync
157
158
159	! Storing to same L2 way0 but different tag,this will write to mcu
160	write_mcu_channel_0:
161	setx 0x2100aa00, %l0, %g3 ! bits [21:18] select way
162	add %g3, L2_BANK_ADDR, %g3
163	stx %g5, [%g3]
164	membar #Sync
165
166	/**
167	*read_error_address_ch0:
168	* ldx [%g2], %l1
169	* membar #Sync
170	*! ldx [%g3], %l2
171	*! membar #Sync
172	**/
173
174
175	check_DRAM_ESR_0:
176	setx DRAM_ERR_STAT_REG, %l3, %g5
177	! add %g5, MCU_BANK_ADDR, %g5
178	ldx [%g5], %l6
179	setx 0xffc0000000000000, %l0,%o2
180	and %l6,%o2,%l6
181
182
183	compute_dram_ESR:
184	mov 0x1, %l1
185	sllx %l1, DRAM_ES_DAU, %l0
186
187
188	verify_dram_ESR:
189	cmp %l0, %l6
190	bne %xcc, test_fail
191	nop
192
193	check_L2_ESR_0:
194	setx L2_ERR_STAT_REG, %l3, %g5
195	add %g5, L2_BANK_ADDR, %g5
196	ldx [%g5], %l6
197
198	compute_L2_ESR:
199	setx 0xfffffffff0000000, %l3, %l0
200	andcc %l0, %l6, %l0 ! Donot check L2ESR SYND bits
201	mov 0x1, %l1
202	sllx %l1, L2ES_DAU, %l0
203	mov 0x1, %l1
204	sllx %l1, L2ES_VEU, %l2
205	or %l0, %l2, %l3
206
207	verify_L2_ESR:
208	cmp %l6, %l3
209	bne %xcc, test_fail
210	nop
211
212
213	setx L2EA_PA0, %l2, %l3
214	add %l3, L2_BANK_ADDR, %l3
215	check_l2_EAR:
216	ldx [%l3], %l4
217	! Error address is the physical address of the cache line (PA[5:0] 0)
218	setx 0x2200aa00, %l0, %g2 ! bits [21:18] select way
219	add %g2, L2_BANK_ADDR, %g2
220
221	setx 0xffffffffc0, %l0,%o2
222	and %l4, %o2, %l4
223	cmp %l4, %g2
224	bne %xcc, test_fail
225	nop
226
227	check_Corr_err_trap:
228	! Check if a Corrected ECC Error Trap happened
229	set EXECUTED, %l0
230	cmp %o0, %l0
231	bne test_fail
232	nop
233	mov TT_Data_Access_Error, %l0
234	cmp %o1, %l0
235	bne test_fail
236	nop
237
238
239	ba test_pass
240	nop
241
242	My_Corrected_ECC_error_trap:
243
244	!My_Recoverable_Sw_error_trap:
245	! Signal trap taken
246	setx EXECUTED, %l0, %o0
247	! save trap type value
248	rdpr %tt, %o1
249	retry
250	nop
251
252
253	/*******************************************************
254	* Exit code
255	*******************************************************/
256
257	test_pass:
258	ta T_GOOD_TRAP
259
260
261	test_fail:
262	ta T_BAD_TRAP
263
264
265