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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: n2_err_dram_DmaWr_ce_L2_Off.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap | |
39 | #define ENABLE_PCIE_LINK_TRAINING | |
40 | ||
41 | ||
42 | #define MAIN_PAGE_NUCLEUS_ALSO | |
43 | #define MAIN_PAGE_HV_ALSO | |
44 | ||
45 | #define L2_ERR_STAT_REG 0xAB00000000 | |
46 | #define L2_ERR_ADDR_REG 0xAC00000000 | |
47 | ||
48 | #define TEST_DATA0 0x1000100081c3e008 | |
49 | #define TEST_DATA1 0x2000200081c3e008 | |
50 | #define TEST_DATA2 0x3000300081c3e008 | |
51 | #define L2_ES_W1C_VALUE 0xc03ffff800000000 | |
52 | #define DRAM_ES_W1C_VALUE 0xfe00000000000000 | |
53 | #define DMA_DATA_BYP_ADDR1 0xfffc00002200aa00 | |
54 | ||
55 | #ifdef MCU0 | |
56 | #define L2_BANK_ADDR 0x0 | |
57 | #define MCU_BANK_ADDR 0x0 | |
58 | #define DRAM_ERR_INJ_REG 0x8400000290 | |
59 | #define DRAM_ERR_STAT_REG 0x8400000280 | |
60 | #define ERROR_ADDR 0x20200000 | |
61 | #endif | |
62 | ||
63 | #ifdef MCU1 | |
64 | #define L2_BANK_ADDR 0x80 | |
65 | #define MCU_BANK_ADDR 0x80 | |
66 | #define DRAM_ERR_INJ_REG 0x8400001290 | |
67 | #define DRAM_ERR_STAT_REG 0x8400001280 | |
68 | ||
69 | ||
70 | #endif | |
71 | ||
72 | #ifdef MCU2 | |
73 | #define L2_BANK_ADDR 0x100 | |
74 | #define MCU_BANK_ADDR 0x100 | |
75 | #define DRAM_ERR_INJ_REG 0x8400002290 | |
76 | #define DRAM_ERR_STAT_REG 0x8400002280 | |
77 | #define ERROR_ADDR 0x20200100 | |
78 | ||
79 | #endif | |
80 | ||
81 | #ifdef MCU3 | |
82 | #define L2_BANK_ADDR 0x180 | |
83 | #define MCU_BANK_ADDR 0x180 | |
84 | #define DRAM_ERR_INJ_REG 0x8400003290 | |
85 | #define DRAM_ERR_STAT_REG 0x8400003280 | |
86 | ||
87 | ||
88 | #endif | |
89 | ||
90 | ||
91 | #include "hboot.s" | |
92 | #include "asi_s.h" | |
93 | #include "err_defines.h" | |
94 | #include "peu_defines.h" | |
95 | ||
96 | ||
97 | ||
98 | .text | |
99 | .global main | |
100 | .global My_Corrected_ECC_error_trap | |
101 | ||
102 | ||
103 | ||
104 | main: | |
105 | ta T_CHANGE_HPRIV | |
106 | disable_l1: | |
107 | ldxa [%g0] ASI_LSU_CONTROL, %l0 | |
108 | ! Remove the lower 2 bits (I-Cache and D-Cache enables) | |
109 | andn %l0, 0x3, %l0 | |
110 | stxa %l0, [%g0] ASI_LSU_CONTROL | |
111 | ||
112 | !Fill_MCU: | |
113 | ! setx 0x2200aa00, %l0, %g2 ! bits [21:18] select way | |
114 | ! add %g2, L2_BANK_ADDR, %g2 | |
115 | ! stx %g5, [%g2] | |
116 | ! membar #Sync | |
117 | ||
118 | ! Write 1 to clear L2 Error status registers | |
119 | clear_l2_ESR: | |
120 | setx L2ES_PA0, %l3, %l4 | |
121 | add %l4, L2_BANK_ADDR, %l4 | |
122 | stx %l5, [%l4] | |
123 | nop | |
124 | ||
125 | set_L2_Off_Mode: | |
126 | setx L2CS_PA0, %l6, %g1 | |
127 | add %g1, L2_BANK_ADDR, %g1 | |
128 | mov 0x1, %l0 | |
129 | stx %l0, [%g1] | |
130 | ||
131 | clear_dram_esr_0: | |
132 | ! Clear DRAM Error status register (Bit[63:57] write-1-clear) | |
133 | setx DRAM_ES_W1C_VALUE, %l0, %l5 | |
134 | setx DRAM_ERR_STAT_REG, %l3, %g5 | |
135 | ! add %g5, MCU_BANK_ADDR, %g5 | |
136 | stx %l5, [%g5] | |
137 | ||
138 | ||
139 | set_DRAM_error_inject_ch0: | |
140 | mov 0x2, %l1 ! ECC Mask (1-bit error) | |
141 | mov 0x1, %l2 | |
142 | sllx %l2, DRAM_EI_SSHOT, %l3 | |
143 | Or %l1, %l3, %l1 ! Set single shot ; | |
144 | mov 0x1, %l2 | |
145 | sllx %l2, DRAM_EI_ENB, %l3 | |
146 | or %l1, %l3, %l1 ! Enable error injection for the next write | |
147 | setx DRAM_ERR_INJ_REG, %l3, %g6 | |
148 | ! add %g6, MCU_BANK_ADDR, %g6 | |
149 | stx %l1, [%g6] | |
150 | membar 0x40 | |
151 | ||
152 | enable_err_reporting: | |
153 | setx L2EE_PA0, %l0, %l1 | |
154 | add %l1, L2_BANK_ADDR, %l1 | |
155 | ldx [%l1], %l2 | |
156 | mov 0x3, %l0 | |
157 | or %l2, %l0, %l2 | |
158 | ||
159 | ||
160 | store_to_L2_way0: | |
161 | setx TEST_DATA1, %l0, %g5 | |
162 | setx 0x2200aa00, %l0, %g2 ! bits [21:18] select way | |
163 | add %g2, L2_BANK_ADDR, %g2 | |
164 | stx %g5, [%g2] | |
165 | membar #Sync | |
166 | nop | |
167 | nop | |
168 | nop | |
169 | nop | |
170 | nop | |
171 | nop | |
172 | nop | |
173 | nop | |
174 | nop | |
175 | nop | |
176 | nop | |
177 | nop | |
178 | nop | |
179 | nop | |
180 | nop | |
181 | nop | |
182 | nop | |
183 | nop | |
184 | nop | |
185 | nop | |
186 | ||
187 | ! ldx [%g2], %g2 | |
188 | ! membar #Sync | |
189 | Wr_Evnt: nop; | |
190 | ! $EV trig_pc_d(1, @VA(.MAIN.Wr_Evnt) -> EnablePCIeIgCmd ("DMAWR",DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h40", 1 ) | |
191 | ||
192 | clr %i7 | |
193 | set 0x20, %l7 | |
194 | loop: | |
195 | inc %i7 | |
196 | cmp %i7,%l7 | |
197 | bne loop | |
198 | nop | |
199 | ||
200 | check_DRAM_ESR_0: | |
201 | setx DRAM_ERR_STAT_REG, %l3, %g5 | |
202 | ldx [%g5], %l6 | |
203 | ||
204 | compute_dram_ESR: | |
205 | mov 0x1, %l1 | |
206 | sllx %l1, DRAM_ES_DAC, %l0 | |
207 | set 0x0002, %l3 ! 16-bit Syndrome - for SECC, it's the mask nibble-reversed | |
208 | or %l0, %l3, %l0 ! %l0 has expected value | |
209 | ||
210 | verify_dram_ESR: | |
211 | cmp %l0, %l6 | |
212 | !bne %xcc, test_fail | |
213 | nop | |
214 | ||
215 | check_L2_ESR_0: | |
216 | setx L2_ERR_STAT_REG, %l3, %g5 | |
217 | add %g5, L2_BANK_ADDR, %g5 | |
218 | ldx [%g5], %l6 | |
219 | ||
220 | compute_L2_ESR: | |
221 | setx 0xfffffffff0000000, %l3, %l0 | |
222 | andcc %l0, %l6, %l0 ! Donot check L2ESR SYND bits | |
223 | mov 0x1, %l1 | |
224 | sllx %l1, L2ES_DAC, %l0 | |
225 | mov 0x1, %l1 | |
226 | sllx %l1, L2ES_VEC, %l2 | |
227 | or %l0, %l2, %l3 | |
228 | ||
229 | verify_L2_ESR: | |
230 | cmp %l6, %l3 | |
231 | !bne %xcc, test_fail | |
232 | ||
233 | nop | |
234 | ||
235 | ||
236 | setx L2EA_PA0, %l2, %l3 | |
237 | add %l3, L2_BANK_ADDR, %l3 | |
238 | check_l2_EAR: | |
239 | ldx [%l3], %l4 | |
240 | ! Error address is the physical address of the cache line (PA[5:0] 0) | |
241 | setx 0x2200aa00, %l0, %g2 ! bits [21:18] select way | |
242 | add %g2, L2_BANK_ADDR, %g2 | |
243 | ||
244 | setx 0xffffffffc0, %l0,%o2 | |
245 | and %l4, %o2, %l4 | |
246 | cmp %l4, %g2 | |
247 | !bne %xcc, test_fail | |
248 | nop | |
249 | ||
250 | check_Corr_err_trap: | |
251 | ! Check if a Corrected ECC Error Trap happened | |
252 | set EXECUTED, %l0 | |
253 | cmp %o0, %l0 | |
254 | !bne test_fail | |
255 | nop | |
256 | ! mov TT_Corrected_ECC, %l0 | |
257 | cmp %o1, %l0 | |
258 | !bne test_fail | |
259 | nop | |
260 | ||
261 | ||
262 | ba test_pass | |
263 | nop | |
264 | ||
265 | My_Corrected_ECC_error_trap: | |
266 | ||
267 | !My_Recoverable_Sw_error_trap: | |
268 | ! Signal trap taken | |
269 | setx EXECUTED, %l0, %o0 | |
270 | ! save trap type value | |
271 | rdpr %tt, %o1 | |
272 | retry | |
273 | nop | |
274 | ||
275 | ||
276 | /******************************************************* | |
277 | * Exit code | |
278 | *******************************************************/ | |
279 | ||
280 | test_pass: | |
281 | ta T_GOOD_TRAP | |
282 | ||
283 | ||
284 | test_fail: | |
285 | ta T_BAD_TRAP | |
286 | ||
287 | ||
288 |