[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / l2 / n2_err_l2_LDAC_LDWC_noDAC.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: n2_err_l2_LDAC_LDWC_noDAC.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define H_HT0_Sw_Recoverable_Error_0x40  My_Recoverable_Sw_error_trap
#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap


#define MAIN_PAGE_HV_ALSO


#define  L2_ENTRY_PA        0xa000000000
#define  TEST_DATA1         0x5555555555555555
#define	 L2_ENTRY_PA0       0x30000008
#define L2_ES_W1C_VALUE     0xc03ffff800000000
#define	 SPARC_ES_W1C_VALUE 0xefffffff
#define  TT_SW_Error        0x40

#include "hboot.s"
#include "asi_s.h"
#include "err_defines.h"

.text
.global	 main
.global	 My_Recoverable_Sw_error_trap
.global  My_Corrected_ECC_error_trap


main:


  ! Boot code does not provide TLB translation for IO address space
  ta    T_CHANGE_HPRIV


disable_l1_DCache:
  ldxa  [%g0] ASI_LSU_CONTROL, %l0
  ! Remove bit 2
  andn  %l0, 0x2, %l0
  stxa  %l0, [%g0] ASI_LSU_CONTROL

enable_err_reporting:
  setx L2EE_PA0, %l0, %l1
  ldx  [%l1], %l2
  mov  0x3, %l0
  or   %l2, %l0, %l2
  stx  %l2, [%l1]


clear_l2_ESR:
  setx  L2_ES_W1C_VALUE, %l0, %l1
  setx  L2ES_PA0, %l6, %g1
  stx   %l1, [%g1]


set_L2_Directly_Mapped_Mode:
  setx  L2CS_PA0, %l6, %g1      ! Bit 1 in L2 Control Status Register
  mov   0x2, %l0
  stx   %l0, [%g1]

store_to_L2:
  setx  TEST_DATA1, %l0, %g5

store_to_L2_way0:
  setx	0x3030aa00, %l0, %g2  ! bits [21:18] select way
  stx %g5, [%g2] 
  stx %g5, [%g2+8]
  membar #Sync

  set 0x8,%l1
  clr %l2
loop:
  inc %l2
  cmp %l1,%l2
  bne loop
  nop

L2_diag_load:
  setx  0x3ffff8, %l0, %l2      ! Mask for extracting [21:3]
  setx	L2_ENTRY_PA, %l0, %g4
  and   %g2, %l2, %g5           !g2 has L2 PA, 
  or	%g5, %g4, %g5           !g5 now has Diagnostic Data Array address 
  ldx	[%g5], %g6
  membar #Sync

  set 0x8,%l1
  clr %l2
loop1:
  inc %l2
  cmp %l1,%l2
  bne loop1
  nop

flip_one_bit:
! Flip one bits to inject error
  xor	 %g6, 0x200, %g6
  stx	%g6, [%g5]
  membar #Sync

  set 0x8,%l1
  clr %l2
loop3:
  inc %l2
  cmp %l1,%l2
  bne loop3
  nop

reading_back_0:                 !Load to L2 again to get the error
  setx  0x3030aa00, %l0, %g2
  ldx   [%g2], %l6
  membar #Sync  


check_sw_err_trap_ldac_0:
  ! Check if a Software Recoverable Error Trap happened
  set   EXECUTED, %l0
  cmp   %o0, %l0
  bne   test_fail
  nop
  mov   TT_SW_Error, %l0
  cmp   %o1, %l0
  bne   test_fail
  nop

compute_error_ldac:
  mov   0x1, %l1
  sllx  %l1, L2ES_LDAC, %l7
  sllx  %l1, L2ES_VEC, %l3
  or    %l7, %l3, %l7
  mov   0x46, %l1                ! 7-bit Syndrome
  sllx  %l1, 21, %l3             ! Syndrome for [127:96] at [27:21]
  or    %l7, %l3, %l7
  sllx  %g4, L2ES_TID, %l3       ! ID of thread that encountered error
  or    %l7, %l3, %l7            ! %l7 has expected value
  membar #Sync

check_l2_ESR_ldac:
  setx  L2ES_PA0, %l6, %g1
  ldx   [%g1], %l4
  membar #Sync

verify_ESR_ldac:
  cmp   %l7,  %l4                ! l7 has expected value l4 has actula value
  !bne test_fail

check_l2_EAR_ldac:
  setx  L2EA_PA0, %l6, %l3
  ldx   [%l3], %l4
  membar #Sync

clear_l2_ESR_ldac:
  setx  L2_ES_W1C_VALUE, %l0, %l1
  setx  L2ES_PA0, %l6, %g1
  stx   %l1, [%g1]

reading_back_1:                 !Load to L2 again to get the error
  setx  0x3030aa00, %l0, %g2
  ldx   [%g2], %l6
  nop
  nop

check_sw_err_trap_ldac_1:
  ! Check if a Software Recoverable Error Trap happened
  set   EXECUTED, %l0
  cmp   %o0, %l0
  bne   test_fail
  nop
  mov   TT_SW_Error, %l0
  cmp   %o1, %l0
  bne   test_fail
  nop

  ldx   [%g2], %l6
  nop
  nop

check_sw_err_trap_ldac_2:
  ! Check if a Software Recoverable Error Trap happened
  set   EXECUTED, %l0
  cmp   %o0, %l0
  bne   test_fail
  nop
  mov   TT_SW_Error, %l0
  cmp   %o1, %l0
  bne   test_fail
  nop

  ldx   [%g2], %l6
  nop
  nop

check_sw_err_trap_ldac_3:
  ! Check if a Software Recoverable Error Trap happened
  set   EXECUTED, %l0
  cmp   %o0, %l0
  bne   test_fail
  nop
  mov   TT_SW_Error, %l0
  cmp   %o1, %l0
  bne   test_fail
  nop

compute_error_mec:
  mov   0x1, %l1
  sllx  %l1, L2ES_LDAC, %l7
  sllx  %l1, L2ES_VEC, %l3
  or    %l7, %l3, %l7
  mov   0x1, %l1
  sllx  %l1, L2ES_MEC, %l3
  or    %l7, %l3, %l7
  mov   0x46, %l1                ! 7-bit Syndrome
  sllx  %l1, 21, %l3             ! Syndrome for [127:96] at [27:21]
  or    %l7, %l3, %l7
  sllx  %g4, L2ES_TID, %l3       ! ID of thread that encountered error
  or    %l7, %l3, %l7            ! %l7 has expected value
  membar #Sync

check_l2_ESR_mec:
  setx  L2ES_PA0, %l6, %g1
  ldx   [%g1], %l4
  membar #Sync

verify_ESR_mec:
  cmp   %l7,  %l4                ! l7 has expected value l4 has actula value
  bne test_fail

check_l2_EAR_mec:
  setx  L2EA_PA0, %l6, %l3
  ldx   [%l3], %l4
  membar #Sync

clear_l2_ESR_mec:
  setx  L2_ES_W1C_VALUE, %l0, %l1
  setx  L2ES_PA0, %l6, %g1
  stx   %l1, [%g1]


write_back_0:                 !Load to L2 again to evict error
  setx  0x7030aa00, %l0, %g2
  ldx   [%g2], %l6
  membar #Sync

compute_error_ldwc:
  mov   0x1, %l1
  sllx  %l1, L2ES_LDWC, %l7
  sllx  %l1, L2ES_VEC, %l3
  or    %l7, %l3, %l7
  mov   0x1, %l1
  sllx  %l1, L2ES_MEC, %l3
  or    %l7, %l3, %l7
  sllx  %g4, L2ES_TID, %l3       ! ID of thread that encountered error
  or    %l7, %l3, %l7            ! %l7 has expected value
  membar #Sync

check_l2_ESR_ldwc:
  setx  L2ES_PA0, %l6, %g1
  ldx   [%g1], %l4
  membar #Sync

verify_ESR_ldwc:
  cmp   %l7,  %l4                ! l7 has expected value l4 has actula value
  bne test_fail

check_l2_EAR_ldwc:
  setx  L2EA_PA0, %l6, %l3
  ldx   [%l3], %l4
  membar #Sync


clear_l2_ESR_ldwc:
  setx  L2_ES_W1C_VALUE, %l0, %l1
  setx  L2ES_PA0, %l6, %g1
  stx   %l1, [%g1]

check_hw_err_trap_ldwc:
  ! Check if a Software Recoverable Error Trap happened
  set   EXECUTED, %l0
  cmp   %o0, %l0
  bne   test_fail
  nop
  clr %o0
  mov   TT_Corrected_ECC, %l0
  cmp   %o1, %l0
  bne   test_fail
  nop
  clr %o1


reading_back_3:                 !Load to L2 again to get line from mcu, cache miss
  setx  0x3030aa00, %l0, %g2
  ldx   [%g2], %l6
  membar #Sync

check_err_trap_dac:
  ! Check if a Software Recoverable Error Trap happened
  cmp   %o0, %g0
  bne   test_fail
  nop
  cmp   %o1, %g0
  bne   test_fail
  nop


enable_l1_DCache:
  ldxa  [%g0] ASI_LSU_CONTROL, %l0
  or    %l0, 0x2, %l0
  stxa  %l0, [%g0] ASI_LSU_CONTROL


check_l2_ESR:
  setx  L2ES_PA0, %l6, %g1
  ldx   [%g1], %l4
  membar #Sync

Verify_ESR:
  cmp %l4,%g0
  bne test_fail
  nop

check_l2_EAR:
  setx  L2EA_PA0, %l6, %l3
  ldx   [%l3], %l4
  membar #Sync

count_traps:
setx 0x38888888,%g1,%g6
ldx [%g6], %g2
  set 0x5,%l2
  cmp %g2,%l2
  bne test_fail
  nop

  ba    test_pass
  nop


My_Recoverable_Sw_error_trap:
setx 0x38888888,%g1,%g6
read_trap_type_Sw:
        setx  EXECUTED, %l0, %o0
        ! save trap type value
        rdpr  %tt, %o1
        nop
  mov   0x40, %i7
  cmp   %o1, %i7
        bne test_fail
        nop

check_clear_desr_Sw:
        ldxa [%g0]ASI_DESR, %i5  !! Also clears desr
        setx 0x3f00000000000000, %i6, %i7
        and  %i5, %i7, %i5
        setx 0x2400000000000000, %i6, %i7
        cmp  %i5, %i7
	bne test_fail
 	nop
	inc %g7
	stx %g7, [%g6]
        retry
        nop


My_Corrected_ECC_error_trap:
setx 0x38888888,%g1,%g6
read_trap_type_Hw:
        setx  EXECUTED, %l0, %o0
        ! save trap type value
        rdpr  %tt, %o1
        nop
  mov   0x63, %i6
  cmp   %o1, %i6
        bne test_fail
        nop

check_clear_desr_Hw:
        ldxa [%g0]ASI_DESR, %i6  !! Also clears desr
        setx 0x3f00000000000000, %i7, %i5
        and  %i6, %i5, %i6
        setx 0x0900000000000000, %i7, %i4
        cmp  %i4, %i6
        bne test_fail
        nop
	inc %g7
	stx %g7, [%g6]
        retry
        nop


/*******************************************************
 * Exit code
 *******************************************************/

test_pass:
ta  T_GOOD_TRAP

test_fail:
ta  T_BAD_TRAP
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: n2_err_l2_LDAC_LDWC_noDAC.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
	39	#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
	40
	41
	42
	43	#define MAIN_PAGE_HV_ALSO
	44
	45
	46	#define L2_ENTRY_PA 0xa000000000
	47	#define TEST_DATA1 0x5555555555555555
	48	#define L2_ENTRY_PA0 0x30000008
	49	#define L2_ES_W1C_VALUE 0xc03ffff800000000
	50	#define SPARC_ES_W1C_VALUE 0xefffffff
	51	#define TT_SW_Error 0x40
	52
	53	#include "hboot.s"
	54	#include "asi_s.h"
	55	#include "err_defines.h"
	56
	57	.text
	58	.global main
	59	.global My_Recoverable_Sw_error_trap
	60	.global My_Corrected_ECC_error_trap
	61
	62
	63	main:
	64
65
66	! Boot code does not provide TLB translation for IO address space
67	ta T_CHANGE_HPRIV
68
69
70	disable_l1_DCache:
71	ldxa [%g0] ASI_LSU_CONTROL, %l0
72	! Remove bit 2
73	andn %l0, 0x2, %l0
74	stxa %l0, [%g0] ASI_LSU_CONTROL
75
76	enable_err_reporting:
77	setx L2EE_PA0, %l0, %l1
78	ldx [%l1], %l2
79	mov 0x3, %l0
80	or %l2, %l0, %l2
81	stx %l2, [%l1]
82
83
84
85	clear_l2_ESR:
86	setx L2_ES_W1C_VALUE, %l0, %l1
87	setx L2ES_PA0, %l6, %g1
88	stx %l1, [%g1]
89
90
91	set_L2_Directly_Mapped_Mode:
92	setx L2CS_PA0, %l6, %g1 ! Bit 1 in L2 Control Status Register
93	mov 0x2, %l0
94	stx %l0, [%g1]
95
96	store_to_L2:
97	setx TEST_DATA1, %l0, %g5
98
99	store_to_L2_way0:
100	setx 0x3030aa00, %l0, %g2 ! bits [21:18] select way
101	stx %g5, [%g2]
102	stx %g5, [%g2+8]
103	membar #Sync
104
105	set 0x8,%l1
106	clr %l2
107	loop:
108	inc %l2
109	cmp %l1,%l2
110	bne loop
111	nop
112
113	L2_diag_load:
114	setx 0x3ffff8, %l0, %l2 ! Mask for extracting [21:3]
115	setx L2_ENTRY_PA, %l0, %g4
116	and %g2, %l2, %g5 !g2 has L2 PA,
117	or %g5, %g4, %g5 !g5 now has Diagnostic Data Array address
118	ldx [%g5], %g6
119	membar #Sync
120
121	set 0x8,%l1
122	clr %l2
123	loop1:
124	inc %l2
125	cmp %l1,%l2
126	bne loop1
127	nop
128
129	flip_one_bit:
130	! Flip one bits to inject error
131	xor %g6, 0x200, %g6
132	stx %g6, [%g5]
133	membar #Sync
134
135	set 0x8,%l1
136	clr %l2
137	loop3:
138	inc %l2
139	cmp %l1,%l2
140	bne loop3
141	nop
142
143	reading_back_0: !Load to L2 again to get the error
144	setx 0x3030aa00, %l0, %g2
145	ldx [%g2], %l6
146	membar #Sync
147
148
149	check_sw_err_trap_ldac_0:
150	! Check if a Software Recoverable Error Trap happened
151	set EXECUTED, %l0
152	cmp %o0, %l0
153	bne test_fail
154	nop
155	mov TT_SW_Error, %l0
156	cmp %o1, %l0
157	bne test_fail
158	nop
159
160	compute_error_ldac:
161	mov 0x1, %l1
162	sllx %l1, L2ES_LDAC, %l7
163	sllx %l1, L2ES_VEC, %l3
164	or %l7, %l3, %l7
165	mov 0x46, %l1 ! 7-bit Syndrome
166	sllx %l1, 21, %l3 ! Syndrome for [127:96] at [27:21]
167	or %l7, %l3, %l7
168	sllx %g4, L2ES_TID, %l3 ! ID of thread that encountered error
169	or %l7, %l3, %l7 ! %l7 has expected value
170	membar #Sync
171
172	check_l2_ESR_ldac:
173	setx L2ES_PA0, %l6, %g1
174	ldx [%g1], %l4
175	membar #Sync
176
177	verify_ESR_ldac:
178	cmp %l7, %l4 ! l7 has expected value l4 has actula value
179	!bne test_fail
180
181	check_l2_EAR_ldac:
182	setx L2EA_PA0, %l6, %l3
183	ldx [%l3], %l4
184	membar #Sync
185
186	clear_l2_ESR_ldac:
187	setx L2_ES_W1C_VALUE, %l0, %l1
188	setx L2ES_PA0, %l6, %g1
189	stx %l1, [%g1]
190
191	reading_back_1: !Load to L2 again to get the error
192	setx 0x3030aa00, %l0, %g2
193	ldx [%g2], %l6
194	nop
195	nop
196
197	check_sw_err_trap_ldac_1:
198	! Check if a Software Recoverable Error Trap happened
199	set EXECUTED, %l0
200	cmp %o0, %l0
201	bne test_fail
202	nop
203	mov TT_SW_Error, %l0
204	cmp %o1, %l0
205	bne test_fail
206	nop
207
208	ldx [%g2], %l6
209	nop
210	nop
211
212	check_sw_err_trap_ldac_2:
213	! Check if a Software Recoverable Error Trap happened
214	set EXECUTED, %l0
215	cmp %o0, %l0
216	bne test_fail
217	nop
218	mov TT_SW_Error, %l0
219	cmp %o1, %l0
220	bne test_fail
221	nop
222
223	ldx [%g2], %l6
224	nop
225	nop
226
227	check_sw_err_trap_ldac_3:
228	! Check if a Software Recoverable Error Trap happened
229	set EXECUTED, %l0
230	cmp %o0, %l0
231	bne test_fail
232	nop
233	mov TT_SW_Error, %l0
234	cmp %o1, %l0
235	bne test_fail
236	nop
237
238	compute_error_mec:
239	mov 0x1, %l1
240	sllx %l1, L2ES_LDAC, %l7
241	sllx %l1, L2ES_VEC, %l3
242	or %l7, %l3, %l7
243	mov 0x1, %l1
244	sllx %l1, L2ES_MEC, %l3
245	or %l7, %l3, %l7
246	mov 0x46, %l1 ! 7-bit Syndrome
247	sllx %l1, 21, %l3 ! Syndrome for [127:96] at [27:21]
248	or %l7, %l3, %l7
249	sllx %g4, L2ES_TID, %l3 ! ID of thread that encountered error
250	or %l7, %l3, %l7 ! %l7 has expected value
251	membar #Sync
252
253	check_l2_ESR_mec:
254	setx L2ES_PA0, %l6, %g1
255	ldx [%g1], %l4
256	membar #Sync
257
258	verify_ESR_mec:
259	cmp %l7, %l4 ! l7 has expected value l4 has actula value
260	bne test_fail
261
262	check_l2_EAR_mec:
263	setx L2EA_PA0, %l6, %l3
264	ldx [%l3], %l4
265	membar #Sync
266
267	clear_l2_ESR_mec:
268	setx L2_ES_W1C_VALUE, %l0, %l1
269	setx L2ES_PA0, %l6, %g1
270	stx %l1, [%g1]
271
272
273	write_back_0: !Load to L2 again to evict error
274	setx 0x7030aa00, %l0, %g2
275	ldx [%g2], %l6
276	membar #Sync
277
278	compute_error_ldwc:
279	mov 0x1, %l1
280	sllx %l1, L2ES_LDWC, %l7
281	sllx %l1, L2ES_VEC, %l3
282	or %l7, %l3, %l7
283	mov 0x1, %l1
284	sllx %l1, L2ES_MEC, %l3
285	or %l7, %l3, %l7
286	sllx %g4, L2ES_TID, %l3 ! ID of thread that encountered error
287	or %l7, %l3, %l7 ! %l7 has expected value
288	membar #Sync
289
290	check_l2_ESR_ldwc:
291	setx L2ES_PA0, %l6, %g1
292	ldx [%g1], %l4
293	membar #Sync
294
295	verify_ESR_ldwc:
296	cmp %l7, %l4 ! l7 has expected value l4 has actula value
297	bne test_fail
298
299	check_l2_EAR_ldwc:
300	setx L2EA_PA0, %l6, %l3
301	ldx [%l3], %l4
302	membar #Sync
303
304
305	clear_l2_ESR_ldwc:
306	setx L2_ES_W1C_VALUE, %l0, %l1
307	setx L2ES_PA0, %l6, %g1
308	stx %l1, [%g1]
309
310	check_hw_err_trap_ldwc:
311	! Check if a Software Recoverable Error Trap happened
312	set EXECUTED, %l0
313	cmp %o0, %l0
314	bne test_fail
315	nop
316	clr %o0
317	mov TT_Corrected_ECC, %l0
318	cmp %o1, %l0
319	bne test_fail
320	nop
321	clr %o1
322
323
324
325	reading_back_3: !Load to L2 again to get line from mcu, cache miss
326	setx 0x3030aa00, %l0, %g2
327	ldx [%g2], %l6
328	membar #Sync
329
330	check_err_trap_dac:
331	! Check if a Software Recoverable Error Trap happened
332	cmp %o0, %g0
333	bne test_fail
334	nop
335	cmp %o1, %g0
336	bne test_fail
337	nop
338
339
340	enable_l1_DCache:
341	ldxa [%g0] ASI_LSU_CONTROL, %l0
342	or %l0, 0x2, %l0
343	stxa %l0, [%g0] ASI_LSU_CONTROL
344
345
346	check_l2_ESR:
347	setx L2ES_PA0, %l6, %g1
348	ldx [%g1], %l4
349	membar #Sync
350
351	Verify_ESR:
352	cmp %l4,%g0
353	bne test_fail
354	nop
355
356	check_l2_EAR:
357	setx L2EA_PA0, %l6, %l3
358	ldx [%l3], %l4
359	membar #Sync
360
361	count_traps:
362	setx 0x38888888,%g1,%g6
363	ldx [%g6], %g2
364	set 0x5,%l2
365	cmp %g2,%l2
366	bne test_fail
367	nop
368
369	ba test_pass
370	nop
371
372
373	My_Recoverable_Sw_error_trap:
374	setx 0x38888888,%g1,%g6
375	read_trap_type_Sw:
376	setx EXECUTED, %l0, %o0
377	! save trap type value
378	rdpr %tt, %o1
379	nop
380	mov 0x40, %i7
381	cmp %o1, %i7
382	bne test_fail
383	nop
384
385	check_clear_desr_Sw:
386	ldxa [%g0]ASI_DESR, %i5 !! Also clears desr
387	setx 0x3f00000000000000, %i6, %i7
388	and %i5, %i7, %i5
389	setx 0x2400000000000000, %i6, %i7
390	cmp %i5, %i7
391	bne test_fail
392	nop
393	inc %g7
394	stx %g7, [%g6]
395	retry
396	nop
397
398
399
400	My_Corrected_ECC_error_trap:
401	setx 0x38888888,%g1,%g6
402	read_trap_type_Hw:
403	setx EXECUTED, %l0, %o0
404	! save trap type value
405	rdpr %tt, %o1
406	nop
407	mov 0x63, %i6
408	cmp %o1, %i6
409	bne test_fail
410	nop
411
412	check_clear_desr_Hw:
413	ldxa [%g0]ASI_DESR, %i6 !! Also clears desr
414	setx 0x3f00000000000000, %i7, %i5
415	and %i6, %i5, %i6
416	setx 0x0900000000000000, %i7, %i4
417	cmp %i4, %i6
418	bne test_fail
419	nop
420	inc %g7
421	stx %g7, [%g6]
422	retry
423	nop
424
425
426
427
428	/*******************************************************
429	* Exit code
430	*******************************************************/
431
432	test_pass:
433	ta T_GOOD_TRAP
434
435	test_fail:
436	ta T_BAD_TRAP