[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / l2 / n2_err_l2_LDAC_all_tids.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: n2_err_l2_LDAC_all_tids.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define MAIN_PAGE_HV_ALSO


#define  L2_ENTRY_PA        0xa100000000
#define  L2_ENTRY_PA1       0xa200000040
#define  TEST_DATA1         0x5555555555555555
#define	 L2_ENTRY_PA0       0x2020000008
#define L2_ES_W1C_VALUE     0xc03ffff800000000
#define	 SPARC_ES_W1C_VALUE 0xefffffff
#define  TT_SW_Error        0x40

#include "hboot.s"
#include "asi_s.h"
#include "err_defines.h"

.text
.global	 main
.global	 My_Recoverable_Sw_error_trap

main:


  ! Boot code does not provide TLB translation for IO address space
  ta    T_CHANGE_HPRIV

get_th_id_o0:
        ta      T_RD_THID

        cmp     %o1, 0x0
        be      main_t0
        nop

        cmp     %o1, 0x1
        be      main_t1
        nop

        cmp     %o1, 0x2
        be      main_t1
        nop

        cmp     %o1, 0x3
        be      main_t1
        nop

        cmp     %o1, 0x4
        be      main_t1
        nop

        cmp     %o1, 0x5
        be      main_t1
        nop

        cmp     %o1, 0x6
        be      main_t1
        nop

        cmp     %o1, 0x7
        be      main_t1
        nop


main_t0:
disable_l1_DCache:
  ldxa  [%g0] ASI_LSU_CONTROL, %l0
  ! Remove bit 2
  andn  %l0, 0x2, %l0
  stxa  %l0, [%g0] ASI_LSU_CONTROL

enable_err_reporting:
  setx L2EE_PA0, %l0, %l1
  ldx  [%l1], %l2
  mov  0x3, %l0
  or   %l2, %l0, %l2
  stx  %l2, [%l1]


clear_l2_ESR:
  setx  L2_ES_W1C_VALUE, %l0, %l1
  setx  L2ES_PA0, %l6, %g1
  stx   %l1, [%g1]


set_L2_Directly_Mapped_Mode:
  setx  L2CS_PA0, %l6, %g1      ! Bit 1 in L2 Control Status Register
  mov   0x2, %l0
  stx   %l0, [%g1]

store_to_L2:
  setx  TEST_DATA1, %l0, %g5

store_to_L2_way0:
  setx	0x3200aa00, %l0, %g2  ! bits [21:18] select way
  stx %g5, [%g2] 
  membar #Sync
  stx %g5, [%g2+8]
  membar #Sync

L2_diag_load:
  setx  0x3ffff8, %l0, %l2      ! Mask for extracting [21:3]
  setx	L2_ENTRY_PA, %l0, %g4
  and   %g2, %l2, %g5           !g2 has L2 PA, 
  or	%g5, %g4, %g5           !g5 now has Diagnostic Data Array address 
  ldx	[%g5], %g6
  membar #Sync

! Flip one bits to inject error
  xor	 %g6, 0x200, %g6
  stx	%g6, [%g5]
  membar #Sync

reading_back_0:                 !Load to L2 again to get the error
  setx  0x3200aa00, %l0, %g2
  ldx   [%g2], %l6
  membar #Sync  

check_sw_err_trap:
  ! Check if a Software Recoverable Error Trap happened
  set   EXECUTED, %l0
  cmp   %o0, %l0
  bne   test_fail
  nop
  mov   TT_SW_Error, %l0
  cmp   %o1, %l0
  bne   test_fail
  nop


enable_l1_DCache:
  ldxa  [%g0] ASI_LSU_CONTROL, %l0
  or    %l0, 0x2, %l0
  stxa  %l0, [%g0] ASI_LSU_CONTROL


compute_error:
  mov   0x1, %l1
  sllx  %l1, L2ES_LDAC, %l7
  sllx  %l1, L2ES_VEC, %l3
  or    %l7, %l3, %l7
  mov   0x46, %l1                ! 7-bit Syndrome
  sllx  %l1, 21, %l3             ! Syndrome for [127:96] at [27:21]
  or    %l7, %l3, %l7
  sllx  %g4, L2ES_TID, %l3       ! ID of thread that encountered error
  or    %l7, %l3, %l7            ! %l7 has expected value
  membar #Sync


check_l2_ESR:
  setx  L2ES_PA0, %l6, %g1
  ldx   [%g1], %l4
  membar #Sync

verify_ESR:
  cmp   %l7,  %l4                ! l7 has expected value l4 has actula value
  bne test_fail


check_l2_EAR:
  setx  L2EA_PA0, %l6, %l3
  ldx   [%l3], %l4
  membar #Sync


To_Thread_1:
  setx  0x3800aaf0, %l0, %g2  ! bits [21_1:18] select way
  setx  0xffffffffffffffff, %l0, %l6  ! bits [21_1:18] select way
  stx %l6, [%g2]
  membar #Sync


  ba    test_pass
  nop

main_t1:

  setx  0x3800aaf0, %l0, %g2  ! bits [21_1:18] select way
  setx  0x1010101010101010, %l0, %l6  ! bits [21_1:18] select way
  setx  0xffffffffffffffff, %l0, %l5  ! bits [21_1:18] select way
  stx %l6, [%g2]
  membar #Sync

!From_Thread_1:
!  ldx   [%g2], %l4
!  membar #Sync
!  cmp %l4,%l5
!  bne From_Thread_1
!  nop


  set  0x40, %g7 ! g7 has L2 Bank 1 Addr 

nop
disable_l1_DCache_1:
  ldxa  [%g0] ASI_LSU_CONTROL, %l0
  ! Remove bit 2
  andn  %l0, 0x2, %l0
  stxa  %l0, [%g0] ASI_LSU_CONTROL

enable_err_reporting_1:
  setx L2EE_PA0, %l0, %l1
  add  %l1, %g7,%l1
  ldx  [%l1], %l2
  mov  0x3, %l0
  or   %l2, %l0, %l2
  stx  %l2, [%l1]

clear_l2_ESR_1:
  setx  L2_ES_W1C_VALUE, %l0, %l1
  setx  L2ES_PA0, %l6, %g1
  add  %g1, %g7,%g1
  stx   %l1, [%g1]


set_L2_Directly_Mapped_Mode_1:
  setx  L2CS_PA0, %l6, %g1      ! Bit 1 in L2 Control Status Register
  add  %g1, %g7,%g1
  mov   0x2, %l0
  stx   %l0, [%g1]

store_to_L2_1:
  setx  TEST_DATA1, %l0, %g5

store_to_L2_way0_1:
  setx  0x2800aa40, %l0, %g2  ! bits [21_1:18] select way
  stx %g5, [%g2]
  membar #Sync
  stx %g5, [%g2+8]
  membar #Sync

L2_diag_load_1:
  setx  0x3ffff8, %l0, %l2      ! Mask for extracting [21:3]
  setx  L2_ENTRY_PA1, %l0, %g4
  and   %g2, %l2, %g5           !g2 has L2 PA,
  or    %g5, %g4, %g5           !g5 now has Diagnostic Data Array address
  ldx   [%g5], %g6
  membar #Sync

! Flip one bits to inject error
  xor    %g6, 0x200, %g6
  stx   %g6, [%g5]
  membar #Sync

reading_back_0_1:                 !Load to L2 again to get the error
  setx  0x2800aa40, %l0, %g2
  ldx   [%g2], %l6
  membar #Sync

check_sw_err_trap_1:
  ! Check if a Software Recoverable Error Trap happened
  set   EXECUTED, %l0
  cmp   %o0, %l0
  bne   test_fail
  nop
  mov   TT_SW_Error, %l0
  cmp   %o1, %l0
  bne   test_fail
  nop

enable_l1_DCache_1:
  ldxa  [%g0] ASI_LSU_CONTROL, %l0
  or    %l0, 0x2, %l0
  stxa  %l0, [%g0] ASI_LSU_CONTROL


compute_error_1:
  mov   0x1, %l1
  sllx  %l1, L2ES_LDAU, %l7
  sllx  %l1, L2ES_VEC, %l3
  or    %l7, %l3, %l7
  mov   0x46, %l1                ! 7-bit Syndrome
  sllx  %l1, 21, %l3             ! Syndrome for [127_1:96] at [27_1:21]
  or    %l7, %l3, %l7
  sllx  %g4, L2ES_TID, %l3       ! ID of thread that encountered error
  or    %l7, %l3, %l7            ! %l7 has expected value
  membar #Sync


check_l2_ESR_1:
  setx  L2ES_PA0, %l6, %g1
  add  %g1, %g7,%g1
  ldx   [%g1], %l4
  membar #Sync

verify_ESR_1:
  cmp   %l7,  %l4                ! l7 has expected value l4 has actual value
  bne test_fail
  nop


check_l2_EAR_1:
  setx  L2EA_PA0, %l6, %l3
  add  %l3, %g7,%l3
  ldx   [%l3], %l4
  membar #Sync


  ba    test_pass
  nop


My_Recoverable_Sw_error_trap:
  ! Signal trap taken
  setx  EXECUTED, %l0, %o0
  ! save trap type value
  rdpr  %tt, %o1
  retry


/*******************************************************
 * Exit code
 *******************************************************/

test_pass:
ta  T_GOOD_TRAP

test_fail:
ta  T_BAD_TRAP
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: n2_err_l2_LDAC_all_tids.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define MAIN_PAGE_HV_ALSO
	39
	40
	41	#define L2_ENTRY_PA 0xa100000000
	42	#define L2_ENTRY_PA1 0xa200000040
	43	#define TEST_DATA1 0x5555555555555555
	44	#define L2_ENTRY_PA0 0x2020000008
	45	#define L2_ES_W1C_VALUE 0xc03ffff800000000
	46	#define SPARC_ES_W1C_VALUE 0xefffffff
	47	#define TT_SW_Error 0x40
	48
	49	#include "hboot.s"
	50	#include "asi_s.h"
	51	#include "err_defines.h"
	52
	53	.text
	54	.global main
	55	.global My_Recoverable_Sw_error_trap
	56
	57	main:
	58
	59
	60	! Boot code does not provide TLB translation for IO address space
	61	ta T_CHANGE_HPRIV
	62
	63	get_th_id_o0:
	64	ta T_RD_THID
65
66	cmp %o1, 0x0
67	be main_t0
68	nop
69
70	cmp %o1, 0x1
71	be main_t1
72	nop
73
74	cmp %o1, 0x2
75	be main_t1
76	nop
77
78	cmp %o1, 0x3
79	be main_t1
80	nop
81
82	cmp %o1, 0x4
83	be main_t1
84	nop
85
86	cmp %o1, 0x5
87	be main_t1
88	nop
89
90	cmp %o1, 0x6
91	be main_t1
92	nop
93
94	cmp %o1, 0x7
95	be main_t1
96	nop
97
98
99
100	main_t0:
101	disable_l1_DCache:
102	ldxa [%g0] ASI_LSU_CONTROL, %l0
103	! Remove bit 2
104	andn %l0, 0x2, %l0
105	stxa %l0, [%g0] ASI_LSU_CONTROL
106
107	enable_err_reporting:
108	setx L2EE_PA0, %l0, %l1
109	ldx [%l1], %l2
110	mov 0x3, %l0
111	or %l2, %l0, %l2
112	stx %l2, [%l1]
113
114
115
116	clear_l2_ESR:
117	setx L2_ES_W1C_VALUE, %l0, %l1
118	setx L2ES_PA0, %l6, %g1
119	stx %l1, [%g1]
120
121
122	set_L2_Directly_Mapped_Mode:
123	setx L2CS_PA0, %l6, %g1 ! Bit 1 in L2 Control Status Register
124	mov 0x2, %l0
125	stx %l0, [%g1]
126
127	store_to_L2:
128	setx TEST_DATA1, %l0, %g5
129
130	store_to_L2_way0:
131	setx 0x3200aa00, %l0, %g2 ! bits [21:18] select way
132	stx %g5, [%g2]
133	membar #Sync
134	stx %g5, [%g2+8]
135	membar #Sync
136
137	L2_diag_load:
138	setx 0x3ffff8, %l0, %l2 ! Mask for extracting [21:3]
139	setx L2_ENTRY_PA, %l0, %g4
140	and %g2, %l2, %g5 !g2 has L2 PA,
141	or %g5, %g4, %g5 !g5 now has Diagnostic Data Array address
142	ldx [%g5], %g6
143	membar #Sync
144
145	! Flip one bits to inject error
146	xor %g6, 0x200, %g6
147	stx %g6, [%g5]
148	membar #Sync
149
150	reading_back_0: !Load to L2 again to get the error
151	setx 0x3200aa00, %l0, %g2
152	ldx [%g2], %l6
153	membar #Sync
154
155	check_sw_err_trap:
156	! Check if a Software Recoverable Error Trap happened
157	set EXECUTED, %l0
158	cmp %o0, %l0
159	bne test_fail
160	nop
161	mov TT_SW_Error, %l0
162	cmp %o1, %l0
163	bne test_fail
164	nop
165
166
167	enable_l1_DCache:
168	ldxa [%g0] ASI_LSU_CONTROL, %l0
169	or %l0, 0x2, %l0
170	stxa %l0, [%g0] ASI_LSU_CONTROL
171
172
173	compute_error:
174	mov 0x1, %l1
175	sllx %l1, L2ES_LDAC, %l7
176	sllx %l1, L2ES_VEC, %l3
177	or %l7, %l3, %l7
178	mov 0x46, %l1 ! 7-bit Syndrome
179	sllx %l1, 21, %l3 ! Syndrome for [127:96] at [27:21]
180	or %l7, %l3, %l7
181	sllx %g4, L2ES_TID, %l3 ! ID of thread that encountered error
182	or %l7, %l3, %l7 ! %l7 has expected value
183	membar #Sync
184
185
186	check_l2_ESR:
187	setx L2ES_PA0, %l6, %g1
188	ldx [%g1], %l4
189	membar #Sync
190
191	verify_ESR:
192	cmp %l7, %l4 ! l7 has expected value l4 has actula value
193	bne test_fail
194
195
196	check_l2_EAR:
197	setx L2EA_PA0, %l6, %l3
198	ldx [%l3], %l4
199	membar #Sync
200
201
202	To_Thread_1:
203	setx 0x3800aaf0, %l0, %g2 ! bits [21_1:18] select way
204	setx 0xffffffffffffffff, %l0, %l6 ! bits [21_1:18] select way
205	stx %l6, [%g2]
206	membar #Sync
207
208
209	ba test_pass
210	nop
211
212	main_t1:
213
214	setx 0x3800aaf0, %l0, %g2 ! bits [21_1:18] select way
215	setx 0x1010101010101010, %l0, %l6 ! bits [21_1:18] select way
216	setx 0xffffffffffffffff, %l0, %l5 ! bits [21_1:18] select way
217	stx %l6, [%g2]
218	membar #Sync
219
220	!From_Thread_1:
221	! ldx [%g2], %l4
222	! membar #Sync
223	! cmp %l4,%l5
224	! bne From_Thread_1
225	! nop
226
227
228	set 0x40, %g7 ! g7 has L2 Bank 1 Addr
229
230	nop
231	disable_l1_DCache_1:
232	ldxa [%g0] ASI_LSU_CONTROL, %l0
233	! Remove bit 2
234	andn %l0, 0x2, %l0
235	stxa %l0, [%g0] ASI_LSU_CONTROL
236
237	enable_err_reporting_1:
238	setx L2EE_PA0, %l0, %l1
239	add %l1, %g7,%l1
240	ldx [%l1], %l2
241	mov 0x3, %l0
242	or %l2, %l0, %l2
243	stx %l2, [%l1]
244
245	clear_l2_ESR_1:
246	setx L2_ES_W1C_VALUE, %l0, %l1
247	setx L2ES_PA0, %l6, %g1
248	add %g1, %g7,%g1
249	stx %l1, [%g1]
250
251
252	set_L2_Directly_Mapped_Mode_1:
253	setx L2CS_PA0, %l6, %g1 ! Bit 1 in L2 Control Status Register
254	add %g1, %g7,%g1
255	mov 0x2, %l0
256	stx %l0, [%g1]
257
258	store_to_L2_1:
259	setx TEST_DATA1, %l0, %g5
260
261	store_to_L2_way0_1:
262	setx 0x2800aa40, %l0, %g2 ! bits [21_1:18] select way
263	stx %g5, [%g2]
264	membar #Sync
265	stx %g5, [%g2+8]
266	membar #Sync
267
268	L2_diag_load_1:
269	setx 0x3ffff8, %l0, %l2 ! Mask for extracting [21:3]
270	setx L2_ENTRY_PA1, %l0, %g4
271	and %g2, %l2, %g5 !g2 has L2 PA,
272	or %g5, %g4, %g5 !g5 now has Diagnostic Data Array address
273	ldx [%g5], %g6
274	membar #Sync
275
276	! Flip one bits to inject error
277	xor %g6, 0x200, %g6
278	stx %g6, [%g5]
279	membar #Sync
280
281	reading_back_0_1: !Load to L2 again to get the error
282	setx 0x2800aa40, %l0, %g2
283	ldx [%g2], %l6
284	membar #Sync
285
286	check_sw_err_trap_1:
287	! Check if a Software Recoverable Error Trap happened
288	set EXECUTED, %l0
289	cmp %o0, %l0
290	bne test_fail
291	nop
292	mov TT_SW_Error, %l0
293	cmp %o1, %l0
294	bne test_fail
295	nop
296
297	enable_l1_DCache_1:
298	ldxa [%g0] ASI_LSU_CONTROL, %l0
299	or %l0, 0x2, %l0
300	stxa %l0, [%g0] ASI_LSU_CONTROL
301
302
303	compute_error_1:
304	mov 0x1, %l1
305	sllx %l1, L2ES_LDAU, %l7
306	sllx %l1, L2ES_VEC, %l3
307	or %l7, %l3, %l7
308	mov 0x46, %l1 ! 7-bit Syndrome
309	sllx %l1, 21, %l3 ! Syndrome for [127_1:96] at [27_1:21]
310	or %l7, %l3, %l7
311	sllx %g4, L2ES_TID, %l3 ! ID of thread that encountered error
312	or %l7, %l3, %l7 ! %l7 has expected value
313	membar #Sync
314
315
316	check_l2_ESR_1:
317	setx L2ES_PA0, %l6, %g1
318	add %g1, %g7,%g1
319	ldx [%g1], %l4
320	membar #Sync
321
322	verify_ESR_1:
323	cmp %l7, %l4 ! l7 has expected value l4 has actual value
324	bne test_fail
325	nop
326
327
328	check_l2_EAR_1:
329	setx L2EA_PA0, %l6, %l3
330	add %l3, %g7,%l3
331	ldx [%l3], %l4
332	membar #Sync
333
334
335
336	ba test_pass
337	nop
338
339
340
341
342
343
344	My_Recoverable_Sw_error_trap:
345	! Signal trap taken
346	setx EXECUTED, %l0, %o0
347	! save trap type value
348	rdpr %tt, %o1
349	retry
350
351
352	/*******************************************************
353	* Exit code
354	*******************************************************/
355
356	test_pass:
357	ta T_GOOD_TRAP
358
359	test_fail:
360	ta T_BAD_TRAP