[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / l2 / n2_err_l2_LDAC_st_cecc_trap.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: n2_err_l2_LDAC_st_cecc_trap.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define MAIN_PAGE_HV_ALSO


#define  L2_ENTRY_PA        0xa000000000
#define  TEST_DATA1         0x5555555555555555
#define	 L2_ENTRY_PA0       0x2020000008
#define L2_ES_W1C_VALUE     0xc03ffff800000000
#define	 SPARC_ES_W1C_VALUE 0xefffffff
#define  TT_SW_Error        0x40

#include "hboot.s"
#include "asi_s.h"
#include "err_defines.h"

.text
.global	 main
.global  My_Corrected_ECC_error_trap


main:


  ! Boot code does not provide TLB translation for IO address space
  ta    T_CHANGE_HPRIV


disable_l1_DCache:
  ldxa  [%g0] ASI_LSU_CONTROL, %l0
  ! Remove bit 2
  andn  %l0, 0x2, %l0
  stxa  %l0, [%g0] ASI_LSU_CONTROL

enable_err_reporting:
  setx L2EE_PA0, %l0, %l1
  ldx  [%l1], %l2
  mov  0x1, %l0
  or   %l2, %l0, %l2
  stx  %l2, [%l1]


clear_l2_ESR:
  setx  L2_ES_W1C_VALUE, %l0, %l1
  setx  L2ES_PA0, %l6, %g1
  stx   %l1, [%g1]


set_L2_Directly_Mapped_Mode:
  setx  L2CS_PA0, %l6, %g1      ! Bit 1 in L2 Control Status Register
  mov   0x2, %l0
  stx   %l0, [%g1]

store_to_L2:
  setx  TEST_DATA1, %l0, %g5

store_to_L2_way0:
  setx	0x202000aa00, %l0, %g2  ! bits [21:18] select way
  stx %g5, [%g2] 
  stx %g5, [%g2+8]
  membar #Sync

L2_diag_load:
  setx  0x3ffff8, %l0, %l2      ! Mask for extracting [21:3]
  setx	L2_ENTRY_PA, %l0, %g4
  and   %g2, %l2, %g5           !g2 has L2 PA, 
  or	%g5, %g4, %g5           !g5 now has Diagnostic Data Array address 
  ldx	[%g5], %g6
  membar #Sync

! Flip one bits to inject error
  xor	 %g6, 0x200, %g6
  stx	%g6, [%g5]
  membar #Sync

reading_back_0:                 !Partial Store to byte 1 again to get the error
  setx  0x202000aa00, %l0, %g2
  stb   %g0, [%g2+1]            !note; error was injected on byte 3 (big endian)
  membar #Sync  


enable_l1_DCache:
  ldxa  [%g0] ASI_LSU_CONTROL, %l0
  or    %l0, 0x2, %l0
  stxa  %l0, [%g0] ASI_LSU_CONTROL


compute_error:
  mov   0x1, %l1
  sllx  %l1, L2ES_LDAC, %l7
  sllx  %l1, L2ES_VEC, %l3
  or    %l7, %l3, %l7
  sllx  %l1, L2ES_RW, %l3
  or    %l7, %l3, %l7
  mov   0x46, %l1                ! 7-bit Syndrome
  sllx  %l1, 21, %l3             ! Syndrome for [127:96] at [27:21]
  or    %l7, %l3, %l7
  sllx  %g4, L2ES_TID, %l3       ! ID of thread that encountered error
  or    %l7, %l3, %l7            ! %l7 has expected value
  membar #Sync


check_l2_ESR:
  setx  L2ES_PA0, %l6, %g1
  ldx   [%g1], %l4
  membar #Sync

verify_ESR:
  cmp   %l7,  %l4                ! l7 has expected value l4 has actula value
  bne test_fail


check_l2_EAR:
  setx  L2EA_PA0, %l6, %l3
  ldx   [%l3], %l4
  membar #Sync

  ba    test_pass
  nop

  ! Check if a Corrected ECC Trap happened
check_error_trap:
  setx  EXECUTED, %l1, %l0
  cmp   %o0, %l0
  bne   test_fail
  nop
  mov   TT_Corrected_ECC, %l0
  cmp   %o1, %l0
  bne   test_fail
  nop

  ba    test_pass
  nop

My_Corrected_ECC_error_trap:
  ! Signal trap taken
  setx  EXECUTED, %l0, %o0
  ! save trap type value
  rdpr  %tt, %o1
//  retry
  done
  nop


/*******************************************************
 * Exit code
 *******************************************************/

test_pass:
ta  T_GOOD_TRAP

test_fail:
ta  T_BAD_TRAP
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: n2_err_l2_LDAC_st_cecc_trap.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define MAIN_PAGE_HV_ALSO
	39
	40
	41	#define L2_ENTRY_PA 0xa000000000
	42	#define TEST_DATA1 0x5555555555555555
	43	#define L2_ENTRY_PA0 0x2020000008
	44	#define L2_ES_W1C_VALUE 0xc03ffff800000000
	45	#define SPARC_ES_W1C_VALUE 0xefffffff
	46	#define TT_SW_Error 0x40
	47
	48	#include "hboot.s"
	49	#include "asi_s.h"
	50	#include "err_defines.h"
	51
	52	.text
	53	.global main
	54	.global My_Corrected_ECC_error_trap
	55
	56
	57	main:
	58
	59
	60	! Boot code does not provide TLB translation for IO address space
	61	ta T_CHANGE_HPRIV
	62
	63
	64	disable_l1_DCache:
65	ldxa [%g0] ASI_LSU_CONTROL, %l0
66	! Remove bit 2
67	andn %l0, 0x2, %l0
68	stxa %l0, [%g0] ASI_LSU_CONTROL
69
70	enable_err_reporting:
71	setx L2EE_PA0, %l0, %l1
72	ldx [%l1], %l2
73	mov 0x1, %l0
74	or %l2, %l0, %l2
75	stx %l2, [%l1]
76
77
78	clear_l2_ESR:
79	setx L2_ES_W1C_VALUE, %l0, %l1
80	setx L2ES_PA0, %l6, %g1
81	stx %l1, [%g1]
82
83
84	set_L2_Directly_Mapped_Mode:
85	setx L2CS_PA0, %l6, %g1 ! Bit 1 in L2 Control Status Register
86	mov 0x2, %l0
87	stx %l0, [%g1]
88
89	store_to_L2:
90	setx TEST_DATA1, %l0, %g5
91
92	store_to_L2_way0:
93	setx 0x202000aa00, %l0, %g2 ! bits [21:18] select way
94	stx %g5, [%g2]
95	stx %g5, [%g2+8]
96	membar #Sync
97
98	L2_diag_load:
99	setx 0x3ffff8, %l0, %l2 ! Mask for extracting [21:3]
100	setx L2_ENTRY_PA, %l0, %g4
101	and %g2, %l2, %g5 !g2 has L2 PA,
102	or %g5, %g4, %g5 !g5 now has Diagnostic Data Array address
103	ldx [%g5], %g6
104	membar #Sync
105
106	! Flip one bits to inject error
107	xor %g6, 0x200, %g6
108	stx %g6, [%g5]
109	membar #Sync
110
111	reading_back_0: !Partial Store to byte 1 again to get the error
112	setx 0x202000aa00, %l0, %g2
113	stb %g0, [%g2+1] !note; error was injected on byte 3 (big endian)
114	membar #Sync
115
116
117	enable_l1_DCache:
118	ldxa [%g0] ASI_LSU_CONTROL, %l0
119	or %l0, 0x2, %l0
120	stxa %l0, [%g0] ASI_LSU_CONTROL
121
122
123	compute_error:
124	mov 0x1, %l1
125	sllx %l1, L2ES_LDAC, %l7
126	sllx %l1, L2ES_VEC, %l3
127	or %l7, %l3, %l7
128	sllx %l1, L2ES_RW, %l3
129	or %l7, %l3, %l7
130	mov 0x46, %l1 ! 7-bit Syndrome
131	sllx %l1, 21, %l3 ! Syndrome for [127:96] at [27:21]
132	or %l7, %l3, %l7
133	sllx %g4, L2ES_TID, %l3 ! ID of thread that encountered error
134	or %l7, %l3, %l7 ! %l7 has expected value
135	membar #Sync
136
137
138	check_l2_ESR:
139	setx L2ES_PA0, %l6, %g1
140	ldx [%g1], %l4
141	membar #Sync
142
143	verify_ESR:
144	cmp %l7, %l4 ! l7 has expected value l4 has actula value
145	bne test_fail
146
147
148	check_l2_EAR:
149	setx L2EA_PA0, %l6, %l3
150	ldx [%l3], %l4
151	membar #Sync
152
153	ba test_pass
154	nop
155
156	! Check if a Corrected ECC Trap happened
157	check_error_trap:
158	setx EXECUTED, %l1, %l0
159	cmp %o0, %l0
160	bne test_fail
161	nop
162	mov TT_Corrected_ECC, %l0
163	cmp %o1, %l0
164	bne test_fail
165	nop
166
167	ba test_pass
168	nop
169
170	My_Corrected_ECC_error_trap:
171	! Signal trap taken
172	setx EXECUTED, %l0, %o0
173	! save trap type value
174	rdpr %tt, %o1
175	// retry
176	done
177	nop
178
179
180	/*******************************************************
181	* Exit code
182	*******************************************************/
183
184	test_pass:
185	ta T_GOOD_TRAP
186
187	test_fail:
188	ta T_BAD_TRAP