projects / OpenSPARC-T2-DV / blame
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| 86530b38 AT |
1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== | |
| 3 | * | |
| 4 | * OpenSPARC T2 Processor File: n2_err_l2_LDAU_cecc.s | |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 7 | * | |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 9 | * | |
| 10 | * This program is free software; you can redistribute it and/or modify | |
| 11 | * it under the terms of the GNU General Public License as published by | |
| 12 | * the Free Software Foundation; version 2 of the License. | |
| 13 | * | |
| 14 | * This program is distributed in the hope that it will be useful, | |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 17 | * GNU General Public License for more details. | |
| 18 | * | |
| 19 | * You should have received a copy of the GNU General Public License | |
| 20 | * along with this program; if not, write to the Free Software | |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 22 | * | |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license | |
| 24 | * choice is available it will apply instead, Sun elects to use only | |
| 25 | * the General Public License version 2 (GPLv2) at this time for any | |
| 26 | * software where a choice of GPL license versions is made | |
| 27 | * available with the language indicating that GPLv2 or any later version | |
| 28 | * may be used, or where a choice of which version of the GPL is applied is | |
| 29 | * otherwise unspecified. | |
| 30 | * | |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
| 33 | * have any questions. | |
| 34 | * | |
| 35 | * | |
| 36 | * ========== Copyright Header End ============================================ | |
| 37 | */ | |
| 38 | #define H_HT0_Corrected_ECC_error_0x63 My_Corrected_ECC_error_trap | |
| 39 | ||
| 40 | #define MAIN_PAGE_HV_ALSO | |
| 41 | ||
| 42 | ||
| 43 | #define L2_ENTRY_PA 0xa000000000 | |
| 44 | #define TEST_DATA1 0x5555555555555555 | |
| 45 | #define L2_ENTRY_PA0 0x2020000008 | |
| 46 | #define L2_ES_W1C_VALUE 0xc03ffff800000000 | |
| 47 | ||
| 48 | #include "hboot.s" | |
| 49 | #include "asi_s.h" | |
| 50 | #include "err_defines.h" | |
| 51 | ||
| 52 | .text | |
| 53 | .global main | |
| 54 | .global My_Corrected_ECC_error_trap | |
| 55 | ||
| 56 | main: | |
| 57 | ||
| 58 | ||
| 59 | ! Boot code does not provide TLB translation for IO address space | |
| 60 | ta T_CHANGE_HPRIV | |
| 61 | ||
| 62 | disable_l1_DCache: | |
| 63 | ldxa [%g0] ASI_LSU_CONTROL, %l0 | |
| 64 | ! Remove bit 2 | |
| 65 | andn %l0, 0x2, %l0 | |
| 66 | stxa %l0, [%g0] ASI_LSU_CONTROL | |
| 67 | ||
| 68 | clear_l2_ESR: | |
| 69 | setx L2_ES_W1C_VALUE, %l0, %l1 | |
| 70 | setx L2ES_PA0, %l6, %g1 | |
| 71 | stx %l1, [%g1] | |
| 72 | ||
| 73 | ||
| 74 | set_L2_Directly_Mapped_Mode: | |
| 75 | setx L2CS_PA0, %l6, %g1 | |
| 76 | mov 0x2, %l0 | |
| 77 | stx %l0, [%g1] | |
| 78 | ||
| 79 | store_to_L2: | |
| 80 | setx TEST_DATA1, %l0, %g5 | |
| 81 | ||
| 82 | store_to_L2_way0: | |
| 83 | setx 0x202000aa00, %l0, %g2 | |
| 84 | stx %g5, [%g2] | |
| 85 | stx %g5, [%g2+8] | |
| 86 | membar #Sync | |
| 87 | ||
| 88 | L2_diag_load: | |
| 89 | setx 0x3ffff8, %l0, %l2 ! Mask for extracting [21:3] | |
| 90 | setx L2_ENTRY_PA, %l0, %g4 | |
| 91 | and %g2, %l2, %g5 | |
| 92 | or %g5, %g4, %g5 | |
| 93 | ldx [%g5], %g6 | |
| 94 | membar #Sync | |
| 95 | ||
| 96 | ! Flip two bits | |
| 97 | xor %g6, 0x600, %g6 | |
| 98 | stx %g6, [%g5] | |
| 99 | membar #Sync | |
| 100 | ||
| 101 | reading_back_0: | |
| 102 | setx 0x202000aa00, %l0, %g2 | |
| 103 | ldx [%g2], %l6 | |
| 104 | membar #Sync | |
| 105 | ||
| 106 | ||
| 107 | enable_l1_DCache: | |
| 108 | ldxa [%g0] ASI_LSU_CONTROL, %l0 | |
| 109 | or %l0, 0x2, %l0 | |
| 110 | stxa %l0, [%g0] ASI_LSU_CONTROL | |
| 111 | ||
| 112 | compute_error: | |
| 113 | mov 0x1, %l1 | |
| 114 | sllx %l1, L2ES_LDAU, %l7 | |
| 115 | sllx %l1, L2ES_VEU, %l3 | |
| 116 | or %l7, %l3, %l7 | |
| 117 | !mov 0x46, %l1 ! 7-bit Syndrome | |
| 118 | !sllx %l1, 21, %l3 ! Syndrome for [127:96] at [27:21] | |
| 119 | !or %l7, %l3, %l7 | |
| 120 | !sllx %g4, L2ES_TID, %l3 ! ID of thread that encountered error | |
| 121 | !or %l7, %l3, %l7 ! %l7 has expected value | |
| 122 | membar #Sync | |
| 123 | ||
| 124 | ||
| 125 | check_l2_ESR: | |
| 126 | setx L2ES_PA0, %l6, %g1 | |
| 127 | ldx [%g1], %l4 | |
| 128 | membar #Sync | |
| 129 | ||
| 130 | cmp %l7, %l4 | |
| 131 | bne test_fail | |
| 132 | nop | |
| 133 | nop | |
| 134 | ||
| 135 | ||
| 136 | check_l2_EAR: | |
| 137 | setx L2EA_PA0, %l6, %l3 | |
| 138 | ldx [%l3], %l4 | |
| 139 | membar #Sync | |
| 140 | ||
| 141 | ba test_pass | |
| 142 | nop | |
| 143 | ||
| 144 | ||
| 145 | My_Corrected_ECC_error_trap: | |
| 146 | ! Signal trap taken | |
| 147 | setx EXECUTED, %l0, %o0 | |
| 148 | ! save trap type value | |
| 149 | rdpr %tt, %o1 | |
| 150 | retry | |
| 151 | ||
| 152 | /******************************************************* | |
| 153 | * Exit code | |
| 154 | *******************************************************/ | |
| 155 | ||
| 156 | test_pass: | |
| 157 | ta T_GOOD_TRAP | |
| 158 | ||
| 159 | test_fail: | |
| 160 | ta T_BAD_TRAP | |
| 161 | ||
| 162 | .data | |
| 163 | ||
| 164 | dtlb_entry: | |
| 165 | ! First word: Tag Access (Note: [12:0] context) | |
| 166 | ! Second word: Data Access TTE | |
| 167 | .xword 0x0000000020018044, 0x8000001130018023 | |
| 168 | ||
| 169 | ||
| 170 | ||
| 171 |