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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: n2_err_l2_LDAU_st_uecc_trap.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define MAIN_PAGE_HV_ALSO | |
39 | ||
40 | ||
41 | #define L2_ENTRY_PA 0xa000000000 | |
42 | #define TEST_DATA1 0x5555555555555555 | |
43 | #define L2_ENTRY_PA0 0x2020000008 | |
44 | #define L2_ES_W1C_VALUE 0xc03ffff800000000 | |
45 | #define TT_SW_Error 0x40 | |
46 | ||
47 | ||
48 | #include "hboot.s" | |
49 | #include "asi_s.h" | |
50 | #include "err_defines.h" | |
51 | ||
52 | .text | |
53 | .global main | |
54 | .global My_Recoverable_Sw_error_trap | |
55 | ||
56 | ||
57 | main: | |
58 | ||
59 | ||
60 | ! Boot code does not provide TLB translation for IO address space | |
61 | ta T_CHANGE_HPRIV | |
62 | ||
63 | disable_l1_DCache: | |
64 | ldxa [%g0] ASI_LSU_CONTROL, %l0 | |
65 | ! Remove bit 2 | |
66 | andn %l0, 0x2, %l0 | |
67 | stxa %l0, [%g0] ASI_LSU_CONTROL | |
68 | ||
69 | ||
70 | enable_err_reporting: | |
71 | setx L2EE_PA0, %l0, %l1 | |
72 | ldx [%l1], %l2 | |
73 | mov 0x3, %l0 | |
74 | or %l2, %l0, %l2 | |
75 | stx %l2, [%l1] | |
76 | ||
77 | clear_l2_ESR: | |
78 | setx L2_ES_W1C_VALUE, %l0, %l1 | |
79 | setx L2ES_PA0, %l6, %g1 | |
80 | stx %l1, [%g1] | |
81 | ||
82 | ||
83 | set_L2_Directly_Mapped_Mode: | |
84 | setx L2CS_PA0, %l6, %g1 | |
85 | mov 0x2, %l0 | |
86 | stx %l0, [%g1] | |
87 | ||
88 | store_to_L2: | |
89 | setx TEST_DATA1, %l0, %g5 | |
90 | ||
91 | store_to_L2_way0: | |
92 | setx 0x202000aa00, %l0, %g2 | |
93 | stx %g5, [%g2] | |
94 | stx %g5, [%g2+8] | |
95 | membar #Sync | |
96 | ||
97 | L2_diag_load: | |
98 | setx 0x3ffff8, %l0, %l2 ! Mask for extracting [21:3] | |
99 | setx L2_ENTRY_PA, %l0, %g4 | |
100 | and %g2, %l2, %g5 | |
101 | or %g5, %g4, %g5 | |
102 | ldx [%g5], %g6 | |
103 | membar #Sync | |
104 | ||
105 | ! Flip two bits | |
106 | xor %g6, 0x600, %g6 | |
107 | stx %g6, [%g5] | |
108 | membar #Sync | |
109 | ||
110 | reading_back_0: | |
111 | setx 0x202000aa00, %l0, %g2 | |
112 | stb %g0, [%g2 +1] ! Partial store | |
113 | membar #Sync | |
114 | ||
115 | ||
116 | enable_l1_DCache: | |
117 | ldxa [%g0] ASI_LSU_CONTROL, %l0 | |
118 | or %l0, 0x2, %l0 | |
119 | stxa %l0, [%g0] ASI_LSU_CONTROL | |
120 | ||
121 | compute_error: | |
122 | mov 0x1, %l1 | |
123 | sllx %l1, L2ES_LDAU, %l7 | |
124 | sllx %l1, L2ES_VEU, %l3 | |
125 | or %l7, %l3, %l7 | |
126 | sllx %l1, L2ES_RW, %l3 | |
127 | or %l7, %l3, %l7 | |
128 | !mov 0x46, %l1 ! 7-bit Syndrome | |
129 | !sllx %l1, 21, %l3 ! Syndrome for [127:96] at [27:21] | |
130 | !or %l7, %l3, %l7 | |
131 | !sllx %g4, L2ES_TID, %l3 ! ID of thread that encountered error | |
132 | !or %l7, %l3, %l7 ! %l7 has expected value | |
133 | membar #Sync | |
134 | ||
135 | ||
136 | check_l2_ESR: | |
137 | setx L2ES_PA0, %l6, %g1 | |
138 | ldx [%g1], %l4 | |
139 | membar #Sync | |
140 | ||
141 | ! Not Checking SYND in this test | |
142 | set 0xffffffff, %l3 | |
143 | andn %l4, %l3, %l4 | |
144 | ||
145 | verify_ESR: | |
146 | cmp %l7, %l4 | |
147 | bne test_fail | |
148 | nop | |
149 | nop | |
150 | ||
151 | ||
152 | check_l2_EAR: | |
153 | setx L2EA_PA0, %l6, %l3 | |
154 | ldx [%l3], %l4 | |
155 | membar #Sync | |
156 | ||
157 | ||
158 | verify_EAR: | |
159 | setx 0x202000aa00, %l0, %g2 | |
160 | cmp %g2, %l4 | |
161 | bne test_fail | |
162 | nop | |
163 | ||
164 | ||
165 | check_sw_err_trap: | |
166 | ! Check if a Software Recoverable Error Trap happened | |
167 | set EXECUTED, %l0 | |
168 | cmp %o0, %l0 | |
169 | bne test_fail | |
170 | nop | |
171 | mov TT_SW_Error, %l0 | |
172 | cmp %o1, %l0 | |
173 | bne test_fail | |
174 | nop | |
175 | ||
176 | ba test_pass | |
177 | nop | |
178 | ||
179 | My_Recoverable_Sw_error_trap: | |
180 | ! Signal trap taken | |
181 | setx EXECUTED, %l0, %o0 | |
182 | ! save trap type value | |
183 | rdpr %tt, %o1 | |
184 | // retry | |
185 | done | |
186 | nop | |
187 | ||
188 | ||
189 | ||
190 | /******************************************************* | |
191 | * Exit code | |
192 | *******************************************************/ | |
193 | ||
194 | test_pass: | |
195 | ta T_GOOD_TRAP | |
196 | ||
197 | test_fail: | |
198 | ta T_BAD_TRAP | |
199 |