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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: n2_err_l2_LTC_cecc_trap_L2off.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define MAIN_PAGE_HV_ALSO | |
39 | ||
40 | ||
41 | #define L2_ENTRY_PA 0xa400000000 | |
42 | #define TEST_DATA1 0x5555555555555555 | |
43 | #define L2_ENTRY_PA0 0x2020000008 | |
44 | #define L2_ES_W1C_VALUE 0xc03ffff800000000 | |
45 | ||
46 | #include "hboot.s" | |
47 | #include "asi_s.h" | |
48 | #include "err_defines.h" | |
49 | ||
50 | .text | |
51 | .global main | |
52 | .global My_Corrected_ECC_error_trap | |
53 | ||
54 | ||
55 | main: | |
56 | ||
57 | ! Boot code does not provide TLB translation for IO address space | |
58 | ta T_CHANGE_HPRIV | |
59 | ||
60 | disable_l1_DCache: | |
61 | ldxa [%g0] ASI_LSU_CONTROL, %l0 | |
62 | ! Remove bit 2 | |
63 | andn %l0, 0x2, %l0 | |
64 | stxa %l0, [%g0] ASI_LSU_CONTROL | |
65 | ||
66 | enable_err_reporting: | |
67 | setx L2EE_PA0, %l0, %l1 | |
68 | ldx [%l1], %l2 | |
69 | mov 0x3, %l0 | |
70 | or %l2, %l0, %l2 | |
71 | stx %l2, [%l1] | |
72 | ||
73 | ||
74 | clear_l2_ESR: | |
75 | setx L2_ES_W1C_VALUE, %l0, %l1 | |
76 | setx L2ES_PA0, %l6, %g1 | |
77 | stx %l1, [%g1] | |
78 | ||
79 | ||
80 | set_L2_off: | |
81 | setx L2CS_PA0, %l6, %g1 ! Bit 1 in L2 Control Status Register | |
82 | mov 0x1, %l0 | |
83 | stx %l0, [%g1] | |
84 | ||
85 | store_to_L2: | |
86 | setx TEST_DATA1, %l0, %g5 | |
87 | ||
88 | store_to_L2_way0: | |
89 | setx 0x202000aa00, %l0, %g2 ! bits [21:18] select way | |
90 | stx %g5, [%g2] | |
91 | stx %g5, [%g2+8] | |
92 | membar #Sync | |
93 | ||
94 | L2_diag_load: | |
95 | setx 0x3ffff8, %l0, %l2 ! Mask for extracting [21:3] | |
96 | setx L2_ENTRY_PA, %l0, %g4 | |
97 | and %g2, %l2, %g5 !g2 has L2 PA, | |
98 | or %g5, %g4, %g5 !g5 now has Diagnostic Data Array address | |
99 | ldx [%g5], %g6 | |
100 | membar #Sync | |
101 | ||
102 | ! Flip one bits to inject error | |
103 | xor %g6, 0x200, %g6 | |
104 | stx %g6, [%g5] | |
105 | membar #Sync | |
106 | ||
107 | !This should cause LTC | |
108 | reading_back_0: !Load to L2 again to get the LTC logged in ESR | |
109 | setx 0x202000aa00, %l0, %g2 | |
110 | ldx [%g2], %l6 | |
111 | membar #Sync | |
112 | ||
113 | reading_back_1: !Load miss to L2 again to get the error trap | |
114 | setx 0x202000ba00, %l0, %g2 | |
115 | ldx [%g2], %l6 | |
116 | membar #Sync | |
117 | ||
118 | /* | |
119 | ! Check if a Corrected ECC Trap happened | |
120 | check_error_trap: | |
121 | setx EXECUTED, %l1, %l0 | |
122 | cmp %o0, %l0 | |
123 | ! bne test_fail | |
124 | nop | |
125 | mov TT_Corrected_ECC, %l0 | |
126 | cmp %o1, %l0 | |
127 | !bne test_fail | |
128 | nop | |
129 | */ | |
130 | ||
131 | enable_l1_DCache: | |
132 | ldxa [%g0] ASI_LSU_CONTROL, %l0 | |
133 | or %l0, 0x2, %l0 | |
134 | stxa %l0, [%g0] ASI_LSU_CONTROL | |
135 | ||
136 | compute_error: | |
137 | mov 0x1, %l1 | |
138 | sllx %l1, L2ES_LTC, %l7 | |
139 | sllx %l1, L2ES_VEC, %l3 | |
140 | or %l7, %l3, %l7 | |
141 | ||
142 | ||
143 | check_l2_ESR: | |
144 | setx L2ES_PA0, %l6, %g1 | |
145 | ldx [%g1], %l4 | |
146 | membar #Sync | |
147 | ||
148 | cmp %g0, %l4 | |
149 | bne test_fail | |
150 | nop | |
151 | ||
152 | ||
153 | /* | |
154 | ||
155 | clr %g2 | |
156 | loop: | |
157 | inc %g2 | |
158 | cmp %g2, 0xff | |
159 | bne loop | |
160 | nop | |
161 | */ | |
162 | ||
163 | ||
164 | check_error_trap: | |
165 | cmp %o0, %g0 | |
166 | bne test_fail | |
167 | nop | |
168 | ||
169 | ba test_pass | |
170 | nop | |
171 | ||
172 | ! Disrupting hw_corrected_error trap handler | |
173 | My_Corrected_ECC_error_trap: | |
174 | ba test_fail | |
175 | nop | |
176 | ||
177 | ||
178 | /******************************************************* | |
179 | * Exit code | |
180 | *******************************************************/ | |
181 | ||
182 | test_pass: | |
183 | ta T_GOOD_TRAP | |
184 | ||
185 | test_fail: | |
186 | ta T_BAD_TRAP |