[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / l2 / n2_l2_ras_da_ce.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: n2_l2_ras_da_ce.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define MAIN_PAGE_HV_ALSO


#define  	L2_ENTRY_PA        	0xa000000000
#define  	TEST_DATA1         	0x5555555555555555
#define	 	L2_ENTRY_PA0       	0x30000008
#define 	L2_ES_W1C_VALUE    	0xc03ffff800000000
#define	 	SPARC_ES_W1C_VALUE 	0xefffffff
#define  	TT_SW_Error        	0x40

#define  	L2_ESR_MASK	0xf03ffffff0000000 
#define 	L2_VEC		36
#define		L2_LDWC		51
#define         L2_LDAC         53
 
#include "hboot.s"
#include "asi_s.h"
#include "err_defines.h"

.text
.global	 main

main:


  ! Boot code does not provide TLB translation for IO address space
	ta    T_CHANGE_HPRIV


disable_l1_DCache:
	ldxa  	[%g0] ASI_LSU_CONTROL, %l0
	! Remove bit 2
	andn  	%l0, 0x2, %l0
	stxa  	%l0, [%g0] ASI_LSU_CONTROL

set_L2_Directly_Mapped_Mode:
	setx  	L2CS_PA0, %l6, %g1      ! Bit 1 in L2 Control Status Register
	mov   	0x2, %l0
	stx   	%l0, [%g1]

store_to_L2:
	setx  	TEST_DATA1, %l0, %g5

store_to_L2_way0:
	setx	0x3000aa00, %l0, %g2  ! bits [21:18] select way
	stx 	%g5, [%g2] 
	stx 	%g5, [%g2+8]
	nop
	nop; nop; nop; nop; nop
        nop; nop; nop; nop; nop
        nop; nop; nop; nop; nop

	membar 	#Sync

L2_diag_load:
	setx  	0x3ffff8, %l0, %l2      ! Mask for extracting [21:3]
	setx	L2_ENTRY_PA, %l0, %g4
	and   	%g2, %l2, %g5           !g2 has L2 PA, 
	or	%g5, %g4, %g5           !g5 now has Diagnostic Data Array address 
	ldx	[%g5], %g6
	membar 	#Sync

! Flip one bits to inject error
	xor 	%g6, 0x200, %g6
	stx	%g6, [%g5]
	membar 	#Sync

reading_back_0:                 !Load to L2 again to get the error
	setx  	0x3000aa00, %l0, %g2
	ldx   	[%g2], %l6
	membar 	#Sync  


check_l2_ESR:
  	setx  	L2ES_PA0, %l6, %g1
  	ldx   	[%g1], %g2

	setx	L2_ESR_MASK, %g7, %g3
	and	%g2, %g3, %g4

	mov	0x1, %i1
	sllx	%i1, L2_VEC, %i2	
	sllx	%i1, L2_LDAC, %i3
	or 	%i2, %i3, %i4

	cmp	%g4, %i4
	bne	%xcc, test_fail
	nop

clear_l2_ESR:
	setx	L2_ES_W1C_VALUE, %g7, %g2
	stx	%g2, [%g1]
	membar	#Sync
     
check_l2_EAR:
	setx  	L2EA_PA0, %g7, %g1
	ldx   	[%g1], %g2
	setx  	0x3000aa00, %g7, %g3
	cmp	%g3, %g2
	bne	test_fail
	nop

clear_l2_EAR:
        stx     %g0, [%g1]
        membar  #Sync
    
	membar #Sync


/**********************************************
	LDWC
***********************************************/
write_back:         
	setx  0x1000aa00, %l0, %g2
	ldx   [%g2], %l6
	add	%g2, 0x200, %g2
        ldx   [%g2], %l6
	membar #Sync

        setx  0x2000aa00, %l0, %g2
        ldx   [%g2], %l6


check_l2_ESR_LDWC:
        setx  L2ES_PA0, %l6, %g1
        ldx   [%g1], %g2

        setx    L2_ESR_MASK, %g7, %g3
        and     %g2, %g3, %g4

        mov     0x1, %i1
        sllx    %i1, L2_VEC, %i2
        sllx    %i1, L2_LDWC, %i3
        or      %i2, %i3, %i4

        cmp     %g4, %i4
        bne     %xcc, test_fail
        nop

check_l2_EAR_LDWC:
        setx    L2EA_PA0, %g7, %g1
        ldx     [%g1], %g2
        setx    0x3000aa00, %g7, %g3
        cmp     %g3, %g2
        bne     test_fail
        nop


  ba    test_pass
  nop


/*******************************************************
 * Exit code
 *******************************************************/

test_pass:
	ta  T_GOOD_TRAP

test_fail:
	ta  T_BAD_TRAP
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: n2_l2_ras_da_ce.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define MAIN_PAGE_HV_ALSO
	39
	40
	41	#define L2_ENTRY_PA 0xa000000000
	42	#define TEST_DATA1 0x5555555555555555
	43	#define L2_ENTRY_PA0 0x30000008
	44	#define L2_ES_W1C_VALUE 0xc03ffff800000000
	45	#define SPARC_ES_W1C_VALUE 0xefffffff
	46	#define TT_SW_Error 0x40
	47
	48	#define L2_ESR_MASK 0xf03ffffff0000000
	49	#define L2_VEC 36
	50	#define L2_LDWC 51
	51	#define L2_LDAC 53
	52
	53	#include "hboot.s"
	54	#include "asi_s.h"
	55	#include "err_defines.h"
	56
	57	.text
	58	.global main
	59
	60	main:
	61
	62
	63	! Boot code does not provide TLB translation for IO address space
	64	ta T_CHANGE_HPRIV
65
66
67	disable_l1_DCache:
68	ldxa [%g0] ASI_LSU_CONTROL, %l0
69	! Remove bit 2
70	andn %l0, 0x2, %l0
71	stxa %l0, [%g0] ASI_LSU_CONTROL
72
73	set_L2_Directly_Mapped_Mode:
74	setx L2CS_PA0, %l6, %g1 ! Bit 1 in L2 Control Status Register
75	mov 0x2, %l0
76	stx %l0, [%g1]
77
78	store_to_L2:
79	setx TEST_DATA1, %l0, %g5
80
81	store_to_L2_way0:
82	setx 0x3000aa00, %l0, %g2 ! bits [21:18] select way
83	stx %g5, [%g2]
84	stx %g5, [%g2+8]
85	nop
86	nop; nop; nop; nop; nop
87	nop; nop; nop; nop; nop
88	nop; nop; nop; nop; nop
89
90	membar #Sync
91
92	L2_diag_load:
93	setx 0x3ffff8, %l0, %l2 ! Mask for extracting [21:3]
94	setx L2_ENTRY_PA, %l0, %g4
95	and %g2, %l2, %g5 !g2 has L2 PA,
96	or %g5, %g4, %g5 !g5 now has Diagnostic Data Array address
97	ldx [%g5], %g6
98	membar #Sync
99
100	! Flip one bits to inject error
101	xor %g6, 0x200, %g6
102	stx %g6, [%g5]
103	membar #Sync
104
105	reading_back_0: !Load to L2 again to get the error
106	setx 0x3000aa00, %l0, %g2
107	ldx [%g2], %l6
108	membar #Sync
109
110
111	check_l2_ESR:
112	setx L2ES_PA0, %l6, %g1
113	ldx [%g1], %g2
114
115	setx L2_ESR_MASK, %g7, %g3
116	and %g2, %g3, %g4
117
118	mov 0x1, %i1
119	sllx %i1, L2_VEC, %i2
120	sllx %i1, L2_LDAC, %i3
121	or %i2, %i3, %i4
122
123	cmp %g4, %i4
124	bne %xcc, test_fail
125	nop
126
127	clear_l2_ESR:
128	setx L2_ES_W1C_VALUE, %g7, %g2
129	stx %g2, [%g1]
130	membar #Sync
131
132	check_l2_EAR:
133	setx L2EA_PA0, %g7, %g1
134	ldx [%g1], %g2
135	setx 0x3000aa00, %g7, %g3
136	cmp %g3, %g2
137	bne test_fail
138	nop
139
140	clear_l2_EAR:
141	stx %g0, [%g1]
142	membar #Sync
143
144	membar #Sync
145
146
147	/**********************************************
148	LDWC
149	***********************************************/
150	write_back:
151	setx 0x1000aa00, %l0, %g2
152	ldx [%g2], %l6
153	add %g2, 0x200, %g2
154	ldx [%g2], %l6
155	membar #Sync
156
157	setx 0x2000aa00, %l0, %g2
158	ldx [%g2], %l6
159
160
161	check_l2_ESR_LDWC:
162	setx L2ES_PA0, %l6, %g1
163	ldx [%g1], %g2
164
165	setx L2_ESR_MASK, %g7, %g3
166	and %g2, %g3, %g4
167
168	mov 0x1, %i1
169	sllx %i1, L2_VEC, %i2
170	sllx %i1, L2_LDWC, %i3
171	or %i2, %i3, %i4
172
173	cmp %g4, %i4
174	bne %xcc, test_fail
175	nop
176
177	check_l2_EAR_LDWC:
178	setx L2EA_PA0, %g7, %g1
179	ldx [%g1], %g2
180	setx 0x3000aa00, %g7, %g3
181	cmp %g3, %g2
182	bne test_fail
183	nop
184
185
186	ba test_pass
187	nop
188
189
190
191	/*******************************************************
192	* Exit code
193	*******************************************************/
194
195	test_pass:
196	ta T_GOOD_TRAP
197
198	test_fail:
199	ta T_BAD_TRAP