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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: n2_err_L2_NotData.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define MAIN_PAGE_NUCLEUS_ALSO | |
39 | #define MAIN_PAGE_HV_ALSO | |
40 | ||
41 | #define DRAM_ERR_INJ_REG 0x8400000290 | |
42 | #define DRAM_ERR_STAT_REG 0x8400000280 | |
43 | #define L2_ERR_STAT_REG 0xAB00000000 | |
44 | #define L2_ERR_ADDR_REG 0xAC00000000 | |
45 | #define L2_NDDM_REG 0xAE00000000 | |
46 | ||
47 | #define TT_SW_Error 0x40 | |
48 | ||
49 | ||
50 | #define ERROR_ADDR 0x20200000 | |
51 | #define TEST_DATA0 0x1000100081c3e008 | |
52 | #define TEST_DATA1 0x2000200081c3e008 | |
53 | #define TEST_DATA2 0x3000300081c3e008 | |
54 | #define L2_ES_W1C_VALUE 0xc03ffff800000000 | |
55 | #define DRAM_ES_W1C_VALUE 0xfe00000000000000 | |
56 | ||
57 | #include "hboot.s" | |
58 | #include "asi_s.h" | |
59 | #include "err_defines.h" | |
60 | ||
61 | ||
62 | .text | |
63 | .global main | |
64 | ||
65 | ||
66 | ||
67 | ||
68 | main: | |
69 | ||
70 | ta T_CHANGE_HPRIV | |
71 | ||
72 | ||
73 | disable_l1: | |
74 | ldxa [%g0] ASI_LSU_CONTROL, %l0 | |
75 | ! Remove the lower 2 bits (I-Cache and D-Cache enables) | |
76 | andn %l0, 0x3, %l0 | |
77 | stxa %l0, [%g0] ASI_LSU_CONTROL | |
78 | ||
79 | setx 0x20040000, %l0, %g6 | |
80 | ||
81 | ||
82 | clear_dram_esr_0: | |
83 | ! Clear DRAM Error status register (Bit[63:57] write-1-clear) | |
84 | setx DRAM_ES_W1C_VALUE, %l0, %g4 | |
85 | setx DRAM_ERR_STAT_REG, %l3, %g5 | |
86 | stx %g4, [%g5] | |
87 | ||
88 | set_DRAM_error_inject_ch0: | |
89 | mov 0x602, %l1 ! ECC Mask (2-bit error) | |
90 | mov 0x1, %l2 | |
91 | sllx %l2, DRAM_EI_SSHOT, %l3 | |
92 | Or %l1, %l3, %l1 ! Set single shot ; | |
93 | mov 0x1, %l2 | |
94 | sllx %l2, DRAM_EI_ENB, %l3 | |
95 | or %l1, %l3, %l1 ! Enable error injection for the next write | |
96 | setx DRAM_ERR_INJ_REG, %l3, %g5 | |
97 | stx %l1, [%g5] | |
98 | membar 0x40 | |
99 | ||
100 | !enable_err_reporting: | |
101 | ! setx L2EE_PA0, %l0, %l1 | |
102 | ! ldx [%l1], %l2 | |
103 | ! mov 0x3, %l0 | |
104 | ! or %l2, %l0, %l2 | |
105 | ! stx %l2, [%l1] | |
106 | ||
107 | ! Write 1 to clear L2 Error status registers | |
108 | clear_l2_ESR: | |
109 | setx L2ES_PA0, %l3, %l4 | |
110 | stx %g4, [%l4] | |
111 | nop | |
112 | ||
113 | store_to_L2: | |
114 | setx TEST_DATA1, %l0, %g5 | |
115 | ||
116 | ||
117 | set_L2_Directly_Mapped_Mode: | |
118 | setx L2CS_PA0, %l6, %g1 | |
119 | mov 0x2, %l0 | |
120 | stx %l0, [%g1] | |
121 | ||
122 | ||
123 | store_to_L2_way0: | |
124 | setx 0x2000aa00, %l0, %g2 ! bits [21:18] select way | |
125 | stx %g5, [%g2] | |
126 | stx %g5, [%g2+8] | |
127 | membar #Sync | |
128 | ||
129 | ! Storing to same L2 way0 but different tag,this will write to mcu | |
130 | write_mcu_channel_0: | |
131 | setx 0x1000aa00, %l0, %g3 ! bits [21:18] select way | |
132 | stx %g5, [%g3] | |
133 | stx %g5, [%g3+8] | |
134 | membar #Sync | |
135 | ||
136 | read_error_address_ch0: | |
137 | ldx [%g2], %l1 | |
138 | membar #Sync | |
139 | ||
140 | ||
141 | check_DRAM_ESR_0: | |
142 | setx DRAM_ERR_STAT_REG, %l3, %g5 | |
143 | ldx [%g5], %l6 | |
144 | ||
145 | compute_dram_ESR: | |
146 | setx 0xffffffffffff0000, %l0,%o2 | |
147 | and %l6,%o2,%l6 | |
148 | mov 0x1, %l1 | |
149 | sllx %l1, DRAM_ES_DAU, %l0 | |
150 | ||
151 | verify_dram_ESR: | |
152 | cmp %l0, %l6 | |
153 | bne %xcc, test_fail | |
154 | nop | |
155 | ||
156 | check_L2_ESR_0: | |
157 | setx L2_ERR_STAT_REG, %l3, %g5 | |
158 | ldx [%g5], %l6 | |
159 | ||
160 | compute_L2_ESR: | |
161 | setx 0xfffffffff0000000, %l3, %l0 | |
162 | andcc %l0, %l6, %l5 ! Donot check L2ESR SYND bits | |
163 | mov 0x1, %l1 | |
164 | sllx %l1, L2ES_DAU, %l0 | |
165 | mov 0x1, %l1 | |
166 | sllx %l1, L2ES_VEU, %l2 | |
167 | or %l0, %l2, %l3 | |
168 | ||
169 | verify_L2_ESR: | |
170 | cmp %l6, %l3 | |
171 | bne %xcc, test_fail | |
172 | nop | |
173 | ||
174 | check_notData_reg: | |
175 | setx L2_NDDM_REG, %l3, %g5 | |
176 | ldx [%g5], %l6 | |
177 | ||
178 | compute_notData_reg: | |
179 | setx 0x200002000aa00, %l0, %l1 ! bits [21:18] select way | |
180 | setx 0x3ffffffffffc0, %l0,%o2 | |
181 | and %l6, %o2, %l6 | |
182 | cmp %l6, %l1 | |
183 | bne %xcc, test_fail | |
184 | nop | |
185 | ||
186 | setx L2EA_PA0, %l2, %l3 | |
187 | check_l2_EAR: | |
188 | ldx [%l3], %l4 | |
189 | ! Error address is the physical address of the cache line (PA[5:0] 0) | |
190 | setx 0x2000aa00, %l0, %l1 ! bits [21:18] select way | |
191 | setx 0xffffffffc0, %l0,%o2 | |
192 | and %l4, %o2, %l4 | |
193 | cmp %l4, %l1 | |
194 | bne %xcc, test_fail | |
195 | nop | |
196 | ||
197 | read_error_address_again: | |
198 | ldx [%g2], %l1 | |
199 | membar #Sync | |
200 | ||
201 | check_L2_ESR_0_meu: | |
202 | setx L2_ERR_STAT_REG, %l3, %g5 | |
203 | ldx [%g5], %l6 | |
204 | ||
205 | compute_L2_ESR_meu: | |
206 | setx 0xfffffffff0000000, %l3, %l0 | |
207 | andcc %l0, %l6, %l5 ! Donot check L2ESR SYND bits | |
208 | mov 0x1, %l1 | |
209 | sllx %l1, L2ES_DAU, %l0 | |
210 | mov 0x1, %l1 | |
211 | sllx %l1, L2ES_VEU, %l2 | |
212 | or %l0, %l2, %l3 | |
213 | !sllx %l1, L2ES_MEU, %l2 | |
214 | !or %l0, %l2, %l3 | |
215 | ||
216 | ||
217 | verify_L2_ESR_meu: | |
218 | cmp %l6, %l3 | |
219 | bne %xcc, test_fail | |
220 | nop | |
221 | setx L2EA_PA0, %l2, %l3 | |
222 | check_l2_EAR_meu: | |
223 | ldx [%l3], %l4 | |
224 | ! Error address is the physical address of the cache line (PA[5:0] 0) | |
225 | setx 0x2000aa00, %l0, %l1 ! bits [21:18] select way | |
226 | setx 0xffffffffc0, %l0,%o2 | |
227 | and %l4, %o2, %l4 | |
228 | cmp %l4, %l1 | |
229 | bne %xcc, test_fail | |
230 | nop | |
231 | ||
232 | check_notData_reg_meu: | |
233 | setx L2_NDDM_REG, %l3, %g5 | |
234 | ldx [%g5], %l6 | |
235 | ||
236 | compute_notData_reg_meu: | |
237 | setx 0xa00002000aa00, %l0, %l1 ! bits [21:18] select way | |
238 | cmp %l6, %l1 | |
239 | bne %xcc, test_fail | |
240 | nop | |
241 | ||
242 | ||
243 | ba test_pass | |
244 | nop | |
245 | ||
246 | /******************************************************* | |
247 | * Exit code | |
248 | *******************************************************/ | |
249 | ||
250 | test_pass: | |
251 | ta T_GOOD_TRAP | |
252 | ||
253 | ||
254 | test_fail: | |
255 | ta T_BAD_TRAP | |
256 | ||
257 | ||
258 |