[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / mcu / n2_err_adv_mcu_2.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: n2_err_adv_mcu_2.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO

#define  L2_ERR_STAT_REG    0xAB00000000
#define  L2_ERR_ADDR_REG    0xAC00000000

#define  TEST_DATA1         0x1000100081c3e008
#define  TEST_DATA2         0x2000200081c3e008
#define  L2_ES_W1C_VALUE    0xc03ffff800000000
#define  DRAM_ES_W1C_VALUE  0xfe00000000000000

#define  DRAM_ERR_INJ_REG   0x8400000290
#define  DRAM_ERR_STAT_REG  0x8400000280
#define	 ERROR_ADDR	    0x20200000

#define  DRAM_SCRUB_FREQ_REG  0x8400000018
#define  DRAM_SCRUB_ENB_REG    0x8400000040

#include "hboot.s"
#include "asi_s.h"
#include "err_defines.h"


.text
.global  main


main:
  ta T_CHANGE_HPRIV

disable_l1:
  ldxa  [%g0] ASI_LSU_CONTROL, %l0
  ! Remove the lower 2 bits (I-Cache and D-Cache enables)
  andn  %l0, 0x3, %l0
  stxa  %l0, [%g0] ASI_LSU_CONTROL

! begin
clear_DRAM_ESR_MCU0:
  clr %l0
  clr %l1
  setx  DRAM_ES_W1C_VALUE, %l0, %g2
  setx  0x8400000280, %l1, %g6
  stx   %g2, [%g6]
clear_L2_ESR_BANK_0_and_1:
  clr %l0
  clr %l1
  setx  L2_ES_W1C_VALUE, %l0, %g4
  setx  0xbb00000000, %l1, %g7
  stx   %g4, [%g7]
  setx  0xbb00000040, %l1, %g5
  stx   %g4, [%g5]

  clr %g1
  mov 0x1, %g1
  sllx %g1, 32, %g1
  clr %g2
  mov 0x1, %g2
  sllx %g2, 22, %g2
  clr %g3
  mov 100, %g3

ld_from_L2_bank0:
  ldx [%g1], %l1
  membar 0x40
  add %g1, %g2, %g1
  sub %g3, 1, %g3
  brnz %g3,ld_from_L2_bank0
  nop
  
 clr %g1
 mov 0x1, %g1
 sllx %g1, 32, %g1
 add %g1, 0x40, %g1
 clr %g2
 mov 0x1, %g2
 sllx %g2, 22, %g2
 clr %g3
 mov 100, %g3

ld_from_L2_bank1:
 ldx [%g1], %l1
 membar 0x40
 add %g1, %g2, %g1
 sub %g3, 1, %g3
 brnz %g3,ld_from_L2_bank1
 nop

check_DRAM_ESR_MCU0_DAC_and_MEC:
  clr %l1
  mov   0x1, %l1
  sllx  %l1, 61, %l1
  clr %l2
  mov   0x1, %l2
  sllx  %l2, 62, %l2
  or    %l1, %l2, %l1
  clr %l3
  set   0xffff, %l3
  ldx   [%g6], %l0
  andn  %l0, %l3, %l0
  cmp   %l0, %l1
  bne   %xcc, test_fail
  nop

check_L2_ESR_Bank_0_DAC_and_MEC:
  clr %l1
  mov   0x1, %l1
  sllx  %l1, 42, %l1
  clr %l2
  mov   0x1, %l2
  sllx  %l2, 62, %l2
  or    %l1, %l2, %l1
  clr %l3
  mov   0x1, %l3
  sllx  %l3, 36, %l3
  or    %l1, %l3, %l1
  ldx   [%g7], %l0
  cmp   %l0, %l1
  bne   %xcc, test_fail
  nop
check_L2_ESR_Bank_1_DAC_and_MEC:
  clr %l1
  mov   0x1, %l1
  sllx  %l1, 42, %l1
  clr %l2
  mov   0x1, %l2
  sllx  %l2, 62, %l2
  or    %l1, %l2, %l1
  clr %l3
  mov   0x1, %l3
  sllx  %l3, 36, %l3
  or    %l1, %l3, %l1
  ldx   [%g5], %l0
  cmp   %l0, %l1
  bne   %xcc, test_fail
  nop
  

clear_DRAM_ESR_MCU1:
  clr %l0
  clr %l1
  setx  DRAM_ES_W1C_VALUE, %l0, %g2
  setx  0x8400001280, %l1, %g6
  stx   %g2, [%g6]
clear_L2_ESR_BANK_2_and_3:
  clr %l0
  clr %l1
  setx  L2_ES_W1C_VALUE, %l0, %g4
  setx  0xbb00000080, %l1, %g7
  stx   %g4, [%g7]
  setx  0xbb000000c0, %l1, %g5
  stx   %g4, [%g5]
 
 clr %g1
 mov 0x1, %g1
 sllx %g1, 32, %g1
 add %g1, 0x80, %g1
 clr %g2
 mov 0x1, %g2
 sllx %g2, 22, %g2
 clr %g3
 mov 100, %g3

ld_from_L2_bank2:
 ldx [%g1], %l1
 membar 0x40
 add %g1, %g2, %g1
 sub %g3, 1, %g3
 brnz %g3,ld_from_L2_bank2
 nop
 
 clr %g1
 mov 0x1, %g1
 sllx %g1, 32, %g1
 add %g1, 0xc0, %g1
 clr %g2
 mov 0x1, %g2 
 sllx %g2, 22, %g2
 clr %g3
 mov 100, %g3

ld_from_L2_bank3:
 ldx [%g1], %l1
 membar 0x40
 add %g1, %g2, %g1
 sub %g3, 1, %g3
 brnz %g3,ld_from_L2_bank3
 nop

check_DRAM_ESR_MCU1_DAC_and_MEC:
  clr %l1
  mov   0x1, %l1
  sllx  %l1, 61, %l1
  clr %l2
  mov   0x1, %l2
  sllx  %l2, 62, %l2
  or    %l1, %l2, %l1
  clr %l3
  set   0xffff, %l3
  ldx   [%g6], %l0
  andn  %l0, %l3, %l0
  cmp   %l0, %l1
  bne   %xcc, test_fail
  nop

check_L2_ESR_Bank_2_DAC_and_MEC:
  clr %l1
  mov   0x1, %l1
  sllx  %l1, 42, %l1
  clr %l2
  mov   0x1, %l2
  sllx  %l2, 62, %l2
  or    %l1, %l2, %l1
  clr %l3
  mov   0x1, %l3
  sllx  %l3, 36, %l3
  or    %l1, %l3, %l1
  ldx   [%g7], %l0
  cmp   %l0, %l1
  bne   %xcc, test_fail
  nop
check_L2_ESR_Bank_3_DAC_and_MEC:
  clr %l1
  mov   0x1, %l1
  sllx  %l1, 42, %l1
  clr %l2
  mov   0x1, %l2
  sllx  %l2, 62, %l2
  or    %l1, %l2, %l1
  clr %l3
  mov   0x1, %l3
  sllx  %l3, 36, %l3
  or    %l1, %l3, %l1
  ldx   [%g5], %l0
  cmp   %l0, %l1
  bne   %xcc, test_fail
  nop
  

clear_DRAM_ESR_MCU2:
  clr %l0
  clr %l1
  setx  DRAM_ES_W1C_VALUE, %l0, %g2
  setx  0x8400002280, %l1, %g6
  stx   %g2, [%g6]
clear_L2_ESR_BANK_4_and_5:
  clr %l0
  clr %l1
  setx  L2_ES_W1C_VALUE, %l0, %g4
  setx  0xbb00000100, %l1, %g7
  stx   %g4, [%g7]
  setx  0xbb00000140, %l1, %g5
  stx   %g4, [%g5]
 
 clr %g1
 mov 0x1, %g1
 sllx %g1, 32, %g1
 add %g1, 0x100, %g1
 clr %g2
 mov 0x1, %g2
 sllx %g2, 22, %g2
 clr %g3
 mov 100, %g3

ld_from_L2_bank4:
 ldx [%g1], %l1
 membar 0x40
 add %g1, %g2, %g1
 sub %g3, 1, %g3
 brnz %g3,ld_from_L2_bank4
 nop
 
 clr %g1
 mov 0x1, %g1
 sllx %g1, 32, %g1
 add %g1, 0x140, %g1
 clr %g2
 mov 0x1, %g2
 sllx %g2, 22, %g2
 clr %g3
 mov 100, %g3

ld_from_L2_bank5:
 ldx [%g1], %l1
 membar 0x40
 add %g1, %g2, %g1
 sub %g3, 1, %g3
 brnz %g3,ld_from_L2_bank5
 nop

check_DRAM_ESR_MCU2_DAC_and_MEC:
  clr %l1
  mov   0x1, %l1
  sllx  %l1, 61, %l1
  clr %l2
  mov   0x1, %l2
  sllx  %l2, 62, %l2
  or    %l1, %l2, %l1
  clr %l3
  set   0xffff, %l3
  ldx   [%g6], %l0
  andn  %l0, %l3, %l0
  cmp   %l0, %l1
  bne   %xcc, test_fail
  nop

check_L2_ESR_Bank_4_DAC_and_MEC:
  clr %l1
  mov   0x1, %l1
  sllx  %l1, 42, %l1
  clr %l2
  mov   0x1, %l2
  sllx  %l2, 62, %l2
  or    %l1, %l2, %l1
  clr %l3
  mov   0x1, %l3
  sllx  %l3, 36, %l3
  or    %l1, %l3, %l1
  ldx   [%g7], %l0
  cmp   %l0, %l1
  bne   %xcc, test_fail
  nop
check_L2_ESR_Bank_5_DAC_and_MEC:
  clr %l1
  mov   0x1, %l1
  sllx  %l1, 42, %l1
  clr %l2
  mov   0x1, %l2
  sllx  %l2, 62, %l2
  or    %l1, %l2, %l1
  clr %l3
  mov   0x1, %l3
  sllx  %l3, 36, %l3
  or    %l1, %l3, %l1
  ldx   [%g5], %l0
  cmp   %l0, %l1
  bne   %xcc, test_fail
  nop
 

clear_DRAM_ESR_MCU3:
  clr %l0
  clr %l1
  setx  DRAM_ES_W1C_VALUE, %l0, %g2
  setx  0x8400003280, %l1, %g6
  stx   %g2, [%g6]
clear_L2_ESR_BANK_6_and_7:
  clr %l0
  clr %l1
  setx  L2_ES_W1C_VALUE, %l0, %g4
  setx  0xbb00000180, %l1, %g7
  stx   %g4, [%g7]
  setx  0xbb000001c0, %l1, %g5
  stx   %g4, [%g5]
 
 clr %g1
 mov 0x1, %g1
 sllx %g1, 32, %g1
 add %g1, 0x180, %g1
 clr %g2
 mov 0x1, %g2
 sllx %g2, 22, %g2
 clr %g3
 mov 100, %g3

ld_from_L2_bank6:
 ldx [%g1], %l1
 membar 0x40
 add %g1, %g2, %g1
 sub %g3, 1, %g3
 brnz %g3,ld_from_L2_bank6
 nop
 
 clr %g1
 mov 0x1, %g1
 sllx %g1, 32, %g1
 add %g1, 0x1c0, %g1
 clr %g2
 mov 0x1, %g2
 sllx %g2, 22, %g2
 clr %g3
 mov 100, %g3

ld_from_L2_bank7:
 ldx [%g1], %l1
 membar 0x40
 add %g1, %g2, %g1
 sub %g3, 1, %g3
 brnz %g3,ld_from_L2_bank7
 nop

check_DRAM_ESR_MCU3_DAC_and_MEC:
  clr %l1
  mov   0x1, %l1
  sllx  %l1, 61, %l1
  clr %l2
  mov   0x1, %l2
  sllx  %l2, 62, %l2
  or    %l1, %l2, %l1
  clr %l3
  set   0xffff, %l3
  ldx   [%g6], %l0
  andn  %l0, %l3, %l0
  cmp   %l0, %l1
  bne   %xcc, test_fail
  nop

check_L2_ESR_Bank_6_DAC_and_MEC:
  clr %l1
  mov   0x1, %l1
  sllx  %l1, 42, %l1
  clr %l2
  mov   0x1, %l2
  sllx  %l2, 62, %l2
  or    %l1, %l2, %l1
  clr %l3
  mov   0x1, %l3
  sllx  %l3, 36, %l3
  or    %l1, %l3, %l1
  ldx   [%g7], %l0
  cmp   %l0, %l1
  bne   %xcc, test_fail
  nop
check_L2_ESR_Bank_7_DAC_and_MEC:
  clr %l1
  mov   0x1, %l1
  sllx  %l1, 42, %l1
  clr %l2
  mov   0x1, %l2
  sllx  %l2, 62, %l2
  or    %l1, %l2, %l1
  clr %l3
  mov   0x1, %l3
  sllx  %l3, 36, %l3
  or    %l1, %l3, %l1
  ldx   [%g5], %l0
  cmp   %l0, %l1
  bne   %xcc, test_fail
  nop
 
  ba    test_pass
  nop

/*******************************************************
 * Exit code
 *******************************************************/

test_pass:
ta  T_GOOD_TRAP


test_fail:
ta  T_BAD_TRAP
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: n2_err_adv_mcu_2.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define MAIN_PAGE_NUCLEUS_ALSO
	39	#define MAIN_PAGE_HV_ALSO
	40
	41	#define L2_ERR_STAT_REG 0xAB00000000
	42	#define L2_ERR_ADDR_REG 0xAC00000000
	43
	44	#define TEST_DATA1 0x1000100081c3e008
	45	#define TEST_DATA2 0x2000200081c3e008
	46	#define L2_ES_W1C_VALUE 0xc03ffff800000000
	47	#define DRAM_ES_W1C_VALUE 0xfe00000000000000
	48
	49	#define DRAM_ERR_INJ_REG 0x8400000290
	50	#define DRAM_ERR_STAT_REG 0x8400000280
	51	#define ERROR_ADDR 0x20200000
	52
	53	#define DRAM_SCRUB_FREQ_REG 0x8400000018
	54	#define DRAM_SCRUB_ENB_REG 0x8400000040
	55
	56	#include "hboot.s"
	57	#include "asi_s.h"
	58	#include "err_defines.h"
	59
	60
	61	.text
	62	.global main
	63
	64
65	main:
66	ta T_CHANGE_HPRIV
67
68	disable_l1:
69	ldxa [%g0] ASI_LSU_CONTROL, %l0
70	! Remove the lower 2 bits (I-Cache and D-Cache enables)
71	andn %l0, 0x3, %l0
72	stxa %l0, [%g0] ASI_LSU_CONTROL
73
74	! begin
75	clear_DRAM_ESR_MCU0:
76	clr %l0
77	clr %l1
78	setx DRAM_ES_W1C_VALUE, %l0, %g2
79	setx 0x8400000280, %l1, %g6
80	stx %g2, [%g6]
81	clear_L2_ESR_BANK_0_and_1:
82	clr %l0
83	clr %l1
84	setx L2_ES_W1C_VALUE, %l0, %g4
85	setx 0xbb00000000, %l1, %g7
86	stx %g4, [%g7]
87	setx 0xbb00000040, %l1, %g5
88	stx %g4, [%g5]
89
90	clr %g1
91	mov 0x1, %g1
92	sllx %g1, 32, %g1
93	clr %g2
94	mov 0x1, %g2
95	sllx %g2, 22, %g2
96	clr %g3
97	mov 100, %g3
98
99	ld_from_L2_bank0:
100	ldx [%g1], %l1
101	membar 0x40
102	add %g1, %g2, %g1
103	sub %g3, 1, %g3
104	brnz %g3,ld_from_L2_bank0
105	nop
106
107	clr %g1
108	mov 0x1, %g1
109	sllx %g1, 32, %g1
110	add %g1, 0x40, %g1
111	clr %g2
112	mov 0x1, %g2
113	sllx %g2, 22, %g2
114	clr %g3
115	mov 100, %g3
116
117	ld_from_L2_bank1:
118	ldx [%g1], %l1
119	membar 0x40
120	add %g1, %g2, %g1
121	sub %g3, 1, %g3
122	brnz %g3,ld_from_L2_bank1
123	nop
124
125	check_DRAM_ESR_MCU0_DAC_and_MEC:
126	clr %l1
127	mov 0x1, %l1
128	sllx %l1, 61, %l1
129	clr %l2
130	mov 0x1, %l2
131	sllx %l2, 62, %l2
132	or %l1, %l2, %l1
133	clr %l3
134	set 0xffff, %l3
135	ldx [%g6], %l0
136	andn %l0, %l3, %l0
137	cmp %l0, %l1
138	bne %xcc, test_fail
139	nop
140
141	check_L2_ESR_Bank_0_DAC_and_MEC:
142	clr %l1
143	mov 0x1, %l1
144	sllx %l1, 42, %l1
145	clr %l2
146	mov 0x1, %l2
147	sllx %l2, 62, %l2
148	or %l1, %l2, %l1
149	clr %l3
150	mov 0x1, %l3
151	sllx %l3, 36, %l3
152	or %l1, %l3, %l1
153	ldx [%g7], %l0
154	cmp %l0, %l1
155	bne %xcc, test_fail
156	nop
157	check_L2_ESR_Bank_1_DAC_and_MEC:
158	clr %l1
159	mov 0x1, %l1
160	sllx %l1, 42, %l1
161	clr %l2
162	mov 0x1, %l2
163	sllx %l2, 62, %l2
164	or %l1, %l2, %l1
165	clr %l3
166	mov 0x1, %l3
167	sllx %l3, 36, %l3
168	or %l1, %l3, %l1
169	ldx [%g5], %l0
170	cmp %l0, %l1
171	bne %xcc, test_fail
172	nop
173
174
175	clear_DRAM_ESR_MCU1:
176	clr %l0
177	clr %l1
178	setx DRAM_ES_W1C_VALUE, %l0, %g2
179	setx 0x8400001280, %l1, %g6
180	stx %g2, [%g6]
181	clear_L2_ESR_BANK_2_and_3:
182	clr %l0
183	clr %l1
184	setx L2_ES_W1C_VALUE, %l0, %g4
185	setx 0xbb00000080, %l1, %g7
186	stx %g4, [%g7]
187	setx 0xbb000000c0, %l1, %g5
188	stx %g4, [%g5]
189
190	clr %g1
191	mov 0x1, %g1
192	sllx %g1, 32, %g1
193	add %g1, 0x80, %g1
194	clr %g2
195	mov 0x1, %g2
196	sllx %g2, 22, %g2
197	clr %g3
198	mov 100, %g3
199
200	ld_from_L2_bank2:
201	ldx [%g1], %l1
202	membar 0x40
203	add %g1, %g2, %g1
204	sub %g3, 1, %g3
205	brnz %g3,ld_from_L2_bank2
206	nop
207
208	clr %g1
209	mov 0x1, %g1
210	sllx %g1, 32, %g1
211	add %g1, 0xc0, %g1
212	clr %g2
213	mov 0x1, %g2
214	sllx %g2, 22, %g2
215	clr %g3
216	mov 100, %g3
217
218	ld_from_L2_bank3:
219	ldx [%g1], %l1
220	membar 0x40
221	add %g1, %g2, %g1
222	sub %g3, 1, %g3
223	brnz %g3,ld_from_L2_bank3
224	nop
225
226	check_DRAM_ESR_MCU1_DAC_and_MEC:
227	clr %l1
228	mov 0x1, %l1
229	sllx %l1, 61, %l1
230	clr %l2
231	mov 0x1, %l2
232	sllx %l2, 62, %l2
233	or %l1, %l2, %l1
234	clr %l3
235	set 0xffff, %l3
236	ldx [%g6], %l0
237	andn %l0, %l3, %l0
238	cmp %l0, %l1
239	bne %xcc, test_fail
240	nop
241
242	check_L2_ESR_Bank_2_DAC_and_MEC:
243	clr %l1
244	mov 0x1, %l1
245	sllx %l1, 42, %l1
246	clr %l2
247	mov 0x1, %l2
248	sllx %l2, 62, %l2
249	or %l1, %l2, %l1
250	clr %l3
251	mov 0x1, %l3
252	sllx %l3, 36, %l3
253	or %l1, %l3, %l1
254	ldx [%g7], %l0
255	cmp %l0, %l1
256	bne %xcc, test_fail
257	nop
258	check_L2_ESR_Bank_3_DAC_and_MEC:
259	clr %l1
260	mov 0x1, %l1
261	sllx %l1, 42, %l1
262	clr %l2
263	mov 0x1, %l2
264	sllx %l2, 62, %l2
265	or %l1, %l2, %l1
266	clr %l3
267	mov 0x1, %l3
268	sllx %l3, 36, %l3
269	or %l1, %l3, %l1
270	ldx [%g5], %l0
271	cmp %l0, %l1
272	bne %xcc, test_fail
273	nop
274
275
276	clear_DRAM_ESR_MCU2:
277	clr %l0
278	clr %l1
279	setx DRAM_ES_W1C_VALUE, %l0, %g2
280	setx 0x8400002280, %l1, %g6
281	stx %g2, [%g6]
282	clear_L2_ESR_BANK_4_and_5:
283	clr %l0
284	clr %l1
285	setx L2_ES_W1C_VALUE, %l0, %g4
286	setx 0xbb00000100, %l1, %g7
287	stx %g4, [%g7]
288	setx 0xbb00000140, %l1, %g5
289	stx %g4, [%g5]
290
291	clr %g1
292	mov 0x1, %g1
293	sllx %g1, 32, %g1
294	add %g1, 0x100, %g1
295	clr %g2
296	mov 0x1, %g2
297	sllx %g2, 22, %g2
298	clr %g3
299	mov 100, %g3
300
301	ld_from_L2_bank4:
302	ldx [%g1], %l1
303	membar 0x40
304	add %g1, %g2, %g1
305	sub %g3, 1, %g3
306	brnz %g3,ld_from_L2_bank4
307	nop
308
309	clr %g1
310	mov 0x1, %g1
311	sllx %g1, 32, %g1
312	add %g1, 0x140, %g1
313	clr %g2
314	mov 0x1, %g2
315	sllx %g2, 22, %g2
316	clr %g3
317	mov 100, %g3
318
319	ld_from_L2_bank5:
320	ldx [%g1], %l1
321	membar 0x40
322	add %g1, %g2, %g1
323	sub %g3, 1, %g3
324	brnz %g3,ld_from_L2_bank5
325	nop
326
327	check_DRAM_ESR_MCU2_DAC_and_MEC:
328	clr %l1
329	mov 0x1, %l1
330	sllx %l1, 61, %l1
331	clr %l2
332	mov 0x1, %l2
333	sllx %l2, 62, %l2
334	or %l1, %l2, %l1
335	clr %l3
336	set 0xffff, %l3
337	ldx [%g6], %l0
338	andn %l0, %l3, %l0
339	cmp %l0, %l1
340	bne %xcc, test_fail
341	nop
342
343	check_L2_ESR_Bank_4_DAC_and_MEC:
344	clr %l1
345	mov 0x1, %l1
346	sllx %l1, 42, %l1
347	clr %l2
348	mov 0x1, %l2
349	sllx %l2, 62, %l2
350	or %l1, %l2, %l1
351	clr %l3
352	mov 0x1, %l3
353	sllx %l3, 36, %l3
354	or %l1, %l3, %l1
355	ldx [%g7], %l0
356	cmp %l0, %l1
357	bne %xcc, test_fail
358	nop
359	check_L2_ESR_Bank_5_DAC_and_MEC:
360	clr %l1
361	mov 0x1, %l1
362	sllx %l1, 42, %l1
363	clr %l2
364	mov 0x1, %l2
365	sllx %l2, 62, %l2
366	or %l1, %l2, %l1
367	clr %l3
368	mov 0x1, %l3
369	sllx %l3, 36, %l3
370	or %l1, %l3, %l1
371	ldx [%g5], %l0
372	cmp %l0, %l1
373	bne %xcc, test_fail
374	nop
375
376
377	clear_DRAM_ESR_MCU3:
378	clr %l0
379	clr %l1
380	setx DRAM_ES_W1C_VALUE, %l0, %g2
381	setx 0x8400003280, %l1, %g6
382	stx %g2, [%g6]
383	clear_L2_ESR_BANK_6_and_7:
384	clr %l0
385	clr %l1
386	setx L2_ES_W1C_VALUE, %l0, %g4
387	setx 0xbb00000180, %l1, %g7
388	stx %g4, [%g7]
389	setx 0xbb000001c0, %l1, %g5
390	stx %g4, [%g5]
391
392	clr %g1
393	mov 0x1, %g1
394	sllx %g1, 32, %g1
395	add %g1, 0x180, %g1
396	clr %g2
397	mov 0x1, %g2
398	sllx %g2, 22, %g2
399	clr %g3
400	mov 100, %g3
401
402	ld_from_L2_bank6:
403	ldx [%g1], %l1
404	membar 0x40
405	add %g1, %g2, %g1
406	sub %g3, 1, %g3
407	brnz %g3,ld_from_L2_bank6
408	nop
409
410	clr %g1
411	mov 0x1, %g1
412	sllx %g1, 32, %g1
413	add %g1, 0x1c0, %g1
414	clr %g2
415	mov 0x1, %g2
416	sllx %g2, 22, %g2
417	clr %g3
418	mov 100, %g3
419
420	ld_from_L2_bank7:
421	ldx [%g1], %l1
422	membar 0x40
423	add %g1, %g2, %g1
424	sub %g3, 1, %g3
425	brnz %g3,ld_from_L2_bank7
426	nop
427
428	check_DRAM_ESR_MCU3_DAC_and_MEC:
429	clr %l1
430	mov 0x1, %l1
431	sllx %l1, 61, %l1
432	clr %l2
433	mov 0x1, %l2
434	sllx %l2, 62, %l2
435	or %l1, %l2, %l1
436	clr %l3
437	set 0xffff, %l3
438	ldx [%g6], %l0
439	andn %l0, %l3, %l0
440	cmp %l0, %l1
441	bne %xcc, test_fail
442	nop
443
444	check_L2_ESR_Bank_6_DAC_and_MEC:
445	clr %l1
446	mov 0x1, %l1
447	sllx %l1, 42, %l1
448	clr %l2
449	mov 0x1, %l2
450	sllx %l2, 62, %l2
451	or %l1, %l2, %l1
452	clr %l3
453	mov 0x1, %l3
454	sllx %l3, 36, %l3
455	or %l1, %l3, %l1
456	ldx [%g7], %l0
457	cmp %l0, %l1
458	bne %xcc, test_fail
459	nop
460	check_L2_ESR_Bank_7_DAC_and_MEC:
461	clr %l1
462	mov 0x1, %l1
463	sllx %l1, 42, %l1
464	clr %l2
465	mov 0x1, %l2
466	sllx %l2, 62, %l2
467	or %l1, %l2, %l1
468	clr %l3
469	mov 0x1, %l3
470	sllx %l3, 36, %l3
471	or %l1, %l3, %l1
472	ldx [%g5], %l0
473	cmp %l0, %l1
474	bne %xcc, test_fail
475	nop
476
477	ba test_pass
478	nop
479
480	/*******************************************************
481	* Exit code
482	*******************************************************/
483
484	test_pass:
485	ta T_GOOD_TRAP
486
487
488	test_fail:
489	ta T_BAD_TRAP
490
491