[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / mcu / n2_err_adv_mcu_3.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: n2_err_adv_mcu_3.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO

#define  L2_ERR_STAT_REG    0xAB00000000
#define  L2_ERR_ADDR_REG    0xAC00000000

#define  TEST_DATA1         0x1000100081c3e008
#define  TEST_DATA2         0x2000200081c3e008
#define  L2_ES_W1C_VALUE    0xc03ffff800000000
#define  DRAM_ES_W1C_VALUE  0xfe00000000000000

#define  DRAM_ERR_INJ_REG   0x8400000290
#define  DRAM_ERR_STAT_REG  0x8400000280
#define	 ERROR_ADDR	    0x20200000

#define  DRAM_SCRUB_FREQ_REG  0x8400000018
#define  DRAM_SCRUB_ENB_REG    0x8400000040

#include "hboot.s"
#include "asi_s.h"
#include "err_defines.h"


.text
.global  main


main:
  ta T_CHANGE_HPRIV

! begin
get_th_id_o0:
  ta  T_RD_THID
  cmp  %o1, 0x0
  be  main_t0
  nop
  cmp  %o1, 0x1
  be  main_t1
  nop
  cmp  %o1, 0x2
  be  main_t2
  nop
  cmp  %o1, 0x3
  be  main_t3
  nop
  cmp  %o1, 0x4
  be  main_t4
  nop
  cmp  %o1, 0x5
  be  main_t5
  nop
  cmp  %o1, 0x6
  be  main_t6
  nop
  cmp  %o1, 0x7
  be  main_t7
  nop

main_t0:
  ba L2B0_Init
  nop

L2B0_Init:
disable_l1:
  ldxa  [%g0] ASI_LSU_CONTROL, %l0
  ! Remove the lower 2 bits (I-Cache and D-Cache enables)
  andn  %l0, 0x3, %l0
  stxa  %l0, [%g0] ASI_LSU_CONTROL


clear_DRAM_ESR_MCU0_B0:
  clr %l0
  clr %l1
  setx  DRAM_ES_W1C_VALUE, %l0, %g2
  setx  0x8400000280, %l1, %g6
  stx   %g2, [%g6]
clear_L2_ESR_BANK_0:
  clr %l0
  clr %l1
  setx  L2_ES_W1C_VALUE, %l0, %g4
  setx  0xbb00000000, %l1, %g7
  stx   %g4, [%g7]

  clr %g1
  mov 0x1, %g1
  sllx %g1, 32, %g1
  clr %g2
  mov 0x1, %g2
  sllx %g2, 22, %g2
  clr %g3
  mov 100, %g3

ld_from_L2_bank0:
  ldx [%g1], %l7
  membar 0x40
  add %g1, %g2, %g1
  sub %g3, 1, %g3
  brnz %g3,ld_from_L2_bank0
  nop
  
check_DRAM_ESR_MCU0_DAC_and_MEC_B0:
  clr %l1
  mov   0x1, %l1
  sllx  %l1, 61, %l1
  clr %l2
  mov   0x1, %l2
  sllx  %l2, 62, %l2
  or    %l1, %l2, %l1
  clr %l3
  set   0xffff, %l3
  ldx   [%g6], %l0
  andn  %l0, %l3, %l0
  cmp   %l0, %l1
  bne   %xcc, test_fail
  nop

check_L2_ESR_Bank_0_DAC_and_MEC:
  clr %l1
  mov   0x1, %l1
  sllx  %l1, 42, %l1
  clr %l2
  mov   0x1, %l2
  sllx  %l2, 62, %l2
  or    %l1, %l2, %l1
  clr %l3
  mov   0x1, %l3
  sllx  %l3, 36, %l3
  or    %l1, %l3, %l1
  ldx   [%g7], %l0
  clr %l2
  clr %l3
  setx 0xf03fffffffffffff, %l2, %l3 !get rid of VCID [59:54]
  and %l0, %l3, %l0
  cmp   %l0, %l1
  bne   %xcc, test_fail
  nop
  
  ba    test_pass
  nop

main_t1:
  ba L2B1_Init
  nop

L2B1_Init:

clear_DRAM_ESR_MCU0_B1:
  clr %l0
  clr %l1
  setx  DRAM_ES_W1C_VALUE, %l0, %g2
  setx  0x8400000280, %l1, %g6
  stx   %g2, [%g6]
clear_L2_ESR_BANK_1:
  clr %l0
  clr %l1
  setx  L2_ES_W1C_VALUE, %l0, %g4
  setx  0xbb00000040, %l1, %g7
  stx   %g4, [%g7]

 clr %g1
 mov 0x1, %g1
 sllx %g1, 32, %g1
 add %g1, 0x40, %g1
 clr %g2
 mov 0x1, %g2
 sllx %g2, 22, %g2
 clr %g3
 mov 100, %g3

ld_from_L2_bank1:
 ldx [%g1], %l7
 membar 0x40
 add %g1, %g2, %g1
 sub %g3, 1, %g3
 brnz %g3,ld_from_L2_bank1
 nop

check_DRAM_ESR_MCU0_DAC_and_MEC_B1:
  clr %l1
  mov   0x1, %l1
  sllx  %l1, 61, %l1
  clr %l2
  mov   0x1, %l2
  sllx  %l2, 62, %l2
  or    %l1, %l2, %l1
  clr %l3
  set   0xffff, %l3
  ldx   [%g6], %l0
  andn  %l0, %l3, %l0
  cmp   %l0, %l1
  bne   %xcc, test_fail
  nop

check_L2_ESR_Bank_1_DAC_and_MEC:
  clr %l1
  mov   0x1, %l1
  sllx  %l1, 42, %l1
  clr %l2
  mov   0x1, %l2
  sllx  %l2, 62, %l2
  or    %l1, %l2, %l1
  clr %l3
  mov   0x1, %l3
  sllx  %l3, 36, %l3
  or    %l1, %l3, %l1
  ldx   [%g7], %l0
  clr %l2
  clr %l3
  setx 0xf03fffffffffffff, %l2, %l3 !get rid of VCID [59:54]
  and %l0, %l3, %l0
  cmp   %l0, %l1
  bne   %xcc, test_fail
  nop
  
  ba    test_pass
  nop

main_t2:
  ba L2B2_Init
  nop

L2B2_Init:

clear_DRAM_ESR_MCU1_B2:
  clr %l0
  clr %l1
  setx  DRAM_ES_W1C_VALUE, %l0, %g2
  setx  0x8400001280, %l1, %g6
  stx   %g2, [%g6]
clear_L2_ESR_BANK_2:
  clr %l0
  clr %l1
  setx  L2_ES_W1C_VALUE, %l0, %g4
  setx  0xbb00000080, %l1, %g7
  stx   %g4, [%g7]
 
 clr %g1
 mov 0x1, %g1
 sllx %g1, 32, %g1
 add %g1, 0x80, %g1
 clr %g2
 mov 0x1, %g2
 sllx %g2, 22, %g2
 clr %g3
 mov 100, %g3

ld_from_L2_bank2:
 ldx [%g1], %l7
 membar 0x40
 add %g1, %g2, %g1
 sub %g3, 1, %g3
 brnz %g3,ld_from_L2_bank2
 nop

check_DRAM_ESR_MCU1_DAC_and_MEC_B2:
  clr %l1
  mov   0x1, %l1
  sllx  %l1, 61, %l1
  clr %l2
  mov   0x1, %l2
  sllx  %l2, 62, %l2
  or    %l1, %l2, %l1
  clr %l3
  set   0xffff, %l3
  ldx   [%g6], %l0
  andn  %l0, %l3, %l0
  cmp   %l0, %l1
  bne   %xcc, test_fail
  nop

check_L2_ESR_Bank_2_DAC_and_MEC:
  clr %l1
  mov   0x1, %l1
  sllx  %l1, 42, %l1
  clr %l2
  mov   0x1, %l2
  sllx  %l2, 62, %l2
  or    %l1, %l2, %l1
  clr %l3
  mov   0x1, %l3
  sllx  %l3, 36, %l3
  or    %l1, %l3, %l1
  ldx   [%g7], %l0
  clr %l2
  clr %l3
  setx 0xf03fffffffffffff, %l2, %l3 !get rid of VCID [59:54]
  and %l0, %l3, %l0
  cmp   %l0, %l1
  bne   %xcc, test_fail
  nop

  ba    test_pass
  nop

main_t3:
  ba L2B3_Init
  nop

L2B3_Init:

clear_DRAM_ESR_MCU1_B3:
  clr %l0
  clr %l1
  setx  DRAM_ES_W1C_VALUE, %l0, %g2
  setx  0x8400001280, %l1, %g6
  stx   %g2, [%g6]
clear_L2_ESR_BANK_3:
  clr %l0
  clr %l1
  setx  L2_ES_W1C_VALUE, %l0, %g4
  setx  0xbb000000c0, %l1, %g7
  stx   %g4, [%g7]
 
 clr %g1
 mov 0x1, %g1
 sllx %g1, 32, %g1
 add %g1, 0xc0, %g1
 clr %g2
 mov 0x1, %g2 
 sllx %g2, 22, %g2
 clr %g3
 mov 100, %g3

ld_from_L2_bank3:
 ldx [%g1], %l7
 membar 0x40
 add %g1, %g2, %g1
 sub %g3, 1, %g3
 brnz %g3,ld_from_L2_bank3
 nop

check_DRAM_ESR_MCU1_DAC_and_MEC_B3:
  clr %l1
  mov   0x1, %l1
  sllx  %l1, 61, %l1
  clr %l2
  mov   0x1, %l2
  sllx  %l2, 62, %l2
  or    %l1, %l2, %l1
  clr %l3
  set   0xffff, %l3
  ldx   [%g6], %l0
  andn  %l0, %l3, %l0
  cmp   %l0, %l1
  bne   %xcc, test_fail
  nop

check_L2_ESR_Bank_3_DAC_and_MEC:
  clr %l1
  mov   0x1, %l1
  sllx  %l1, 42, %l1
  clr %l2
  mov   0x1, %l2
  sllx  %l2, 62, %l2
  or    %l1, %l2, %l1
  clr %l3
  mov   0x1, %l3
  sllx  %l3, 36, %l3
  or    %l1, %l3, %l1
  ldx   [%g7], %l0
  clr %l2
  clr %l3
  setx 0xf03fffffffffffff, %l2, %l3 !get rid of VCID [59:54]
  and %l0, %l3, %l0
  cmp   %l0, %l1
  bne   %xcc, test_fail
  nop
  
  ba    test_pass
  nop

main_t4:
  ba L2B4_Init
  nop

L2B4_Init:

clear_DRAM_ESR_MCU2_B4:
  clr %l0
  clr %l1
  setx  DRAM_ES_W1C_VALUE, %l0, %g2
  setx  0x8400002280, %l1, %g6
  stx   %g2, [%g6]
clear_L2_ESR_BANK_4:
  clr %l0
  clr %l1
  setx  L2_ES_W1C_VALUE, %l0, %g4
  setx  0xbb00000100, %l1, %g7
  stx   %g4, [%g7]
 
 clr %g1
 mov 0x1, %g1
 sllx %g1, 32, %g1
 add %g1, 0x100, %g1
 clr %g2
 mov 0x1, %g2
 sllx %g2, 22, %g2
 clr %g3
 mov 100, %g3

ld_from_L2_bank4:
 ldx [%g1], %l7
 membar 0x40
 add %g1, %g2, %g1
 sub %g3, 1, %g3
 brnz %g3,ld_from_L2_bank4
 nop

check_DRAM_ESR_MCU2_DAC_and_MEC_B4:
  clr %l1
  mov   0x1, %l1
  sllx  %l1, 61, %l1
  clr %l2
  mov   0x1, %l2
  sllx  %l2, 62, %l2
  or    %l1, %l2, %l1
  clr %l3
  set   0xffff, %l3
  ldx   [%g6], %l0
  andn  %l0, %l3, %l0
  cmp   %l0, %l1
  bne   %xcc, test_fail
  nop

check_L2_ESR_Bank_4_DAC_and_MEC:
  clr %l1
  mov   0x1, %l1
  sllx  %l1, 42, %l1
  clr %l2
  mov   0x1, %l2
  sllx  %l2, 62, %l2
  or    %l1, %l2, %l1
  clr %l3
  mov   0x1, %l3
  sllx  %l3, 36, %l3
  or    %l1, %l3, %l1
  ldx   [%g7], %l0
  clr %l2
  clr %l3
  setx 0xf03fffffffffffff, %l2, %l3 !get rid of VCID [59:54]
  and %l0, %l3, %l0
  cmp   %l0, %l1
  bne   %xcc, test_fail
  nop

  ba    test_pass
  nop

main_t5:
  ba L2B5_Init
  nop

L2B5_Init:

clear_DRAM_ESR_MCU2_B5:
  clr %l0
  clr %l1
  setx  DRAM_ES_W1C_VALUE, %l0, %g2
  setx  0x8400002280, %l1, %g6
  stx   %g2, [%g6]
clear_L2_ESR_BANK_5:
  clr %l0
  clr %l1
  setx  L2_ES_W1C_VALUE, %l0, %g4
  setx  0xbb00000140, %l1, %g7
  stx   %g4, [%g7]
 
 clr %g1
 mov 0x1, %g1
 sllx %g1, 32, %g1
 add %g1, 0x140, %g1
 clr %g2
 mov 0x1, %g2
 sllx %g2, 22, %g2
 clr %g3
 mov 100, %g3

ld_from_L2_bank5:
 ldx [%g1], %l7
 membar 0x40
 add %g1, %g2, %g1
 sub %g3, 1, %g3
 brnz %g3,ld_from_L2_bank5
 nop

check_DRAM_ESR_MCU2_DAC_and_MEC_B5:
  clr %l1
  mov   0x1, %l1
  sllx  %l1, 61, %l1
  clr %l2
  mov   0x1, %l2
  sllx  %l2, 62, %l2
  or    %l1, %l2, %l1
  clr %l3
  set   0xffff, %l3
  ldx   [%g6], %l0
  andn  %l0, %l3, %l0
  cmp   %l0, %l1
  bne   %xcc, test_fail
  nop

check_L2_ESR_Bank_5_DAC_and_MEC:
  clr %l1
  mov   0x1, %l1
  sllx  %l1, 42, %l1
  clr %l2
  mov   0x1, %l2
  sllx  %l2, 62, %l2
  or    %l1, %l2, %l1
  clr %l3
  mov   0x1, %l3
  sllx  %l3, 36, %l3
  or    %l1, %l3, %l1
  ldx   [%g7], %l0
  clr %l2
  clr %l3
  setx 0xf03fffffffffffff, %l2, %l3 !get rid of VCID [59:54]
  and %l0, %l3, %l0
  cmp   %l0, %l1
  bne   %xcc, test_fail
  nop
 
  ba    test_pass
  nop

main_t6:
  ba L2B6_Init
  nop

L2B6_Init:
  
clear_DRAM_ESR_MCU3_B6:
  clr %l0
  clr %l1
  setx  DRAM_ES_W1C_VALUE, %l0, %g2
  setx  0x8400003280, %l1, %g6
  stx   %g2, [%g6]
clear_L2_ESR_BANK_6:
  clr %l0
  clr %l1
  setx  L2_ES_W1C_VALUE, %l0, %g4
  setx  0xbb00000180, %l1, %g7
  stx   %g4, [%g7]
 
 clr %g1
 mov 0x1, %g1
 sllx %g1, 32, %g1
 add %g1, 0x180, %g1
 clr %g2
 mov 0x1, %g2
 sllx %g2, 22, %g2
 clr %g3
 mov 100, %g3

ld_from_L2_bank6:
 ldx [%g1], %l7
 membar 0x40
 add %g1, %g2, %g1
 sub %g3, 1, %g3
 brnz %g3,ld_from_L2_bank6
 nop

check_DRAM_ESR_MCU3_DAC_and_MEC_B6:
  clr %l1
  mov   0x1, %l1
  sllx  %l1, 61, %l1
  clr %l2
  mov   0x1, %l2
  sllx  %l2, 62, %l2
  or    %l1, %l2, %l1
  clr %l3
  set   0xffff, %l3
  ldx   [%g6], %l0
  andn  %l0, %l3, %l0
  cmp   %l0, %l1
  bne   %xcc, test_fail
  nop

check_L2_ESR_Bank_6_DAC_and_MEC:
  clr %l1
  mov   0x1, %l1
  sllx  %l1, 42, %l1
  clr %l2
  mov   0x1, %l2
  sllx  %l2, 62, %l2
  or    %l1, %l2, %l1
  clr %l3
  mov   0x1, %l3
  sllx  %l3, 36, %l3
  or    %l1, %l3, %l1
  ldx   [%g7], %l0
  clr %l2
  clr %l3
  setx 0xf03fffffffffffff, %l2, %l3 !get rid of VCID [59:54]
  and %l0, %l3, %l0
  cmp   %l0, %l1
  bne   %xcc, test_fail
  nop

  ba    test_pass
  nop

main_t7:
  ba L2B7_Init
  nop

L2B7_Init:
  
clear_DRAM_ESR_MCU3_B7:
  clr %l0
  clr %l1
  setx  DRAM_ES_W1C_VALUE, %l0, %g2
  setx  0x8400003280, %l1, %g6
  stx   %g2, [%g6]
clear_L2_ESR_BANK_7:
  clr %l0
  clr %l1
  setx  L2_ES_W1C_VALUE, %l0, %g4
  setx  0xbb000001c0, %l1, %g7
  stx   %g4, [%g7]
 
 clr %g1
 mov 0x1, %g1
 sllx %g1, 32, %g1
 add %g1, 0x1c0, %g1
 clr %g2
 mov 0x1, %g2
 sllx %g2, 22, %g2
 clr %g3
 mov 100, %g3

ld_from_L2_bank7:
 ldx [%g1], %l7
 membar 0x40
 add %g1, %g2, %g1
 sub %g3, 1, %g3
 brnz %g3,ld_from_L2_bank7
 nop

check_DRAM_ESR_MCU3_DAC_and_MEC_B7:
  clr %l1
  mov   0x1, %l1
  sllx  %l1, 61, %l1
  clr %l2
  mov   0x1, %l2
  sllx  %l2, 62, %l2
  or    %l1, %l2, %l1
  clr %l3
  set   0xffff, %l3
  ldx   [%g6], %l0
  andn  %l0, %l3, %l0
  cmp   %l0, %l1
  bne   %xcc, test_fail
  nop

check_L2_ESR_Bank_7_DAC_and_MEC:
  clr %l1
  mov   0x1, %l1
  sllx  %l1, 42, %l1
  clr %l2
  mov   0x1, %l2
  sllx  %l2, 62, %l2
  or    %l1, %l2, %l1
  clr %l3
  mov   0x1, %l3
  sllx  %l3, 36, %l3
  or    %l1, %l3, %l1
  ldx   [%g7], %l0
  clr %l2
  clr %l3
  setx 0xf03fffffffffffff, %l2, %l3 !get rid of VCID [59:54]
  and %l0, %l3, %l0
  cmp   %l0, %l1
  bne   %xcc, test_fail
  nop
 
  ba    test_pass
  nop

/*******************************************************
 * Exit code
 *******************************************************/

test_pass:
ta  T_GOOD_TRAP


test_fail:
ta  T_BAD_TRAP
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: n2_err_adv_mcu_3.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define MAIN_PAGE_NUCLEUS_ALSO
	39	#define MAIN_PAGE_HV_ALSO
	40
	41	#define L2_ERR_STAT_REG 0xAB00000000
	42	#define L2_ERR_ADDR_REG 0xAC00000000
	43
	44	#define TEST_DATA1 0x1000100081c3e008
	45	#define TEST_DATA2 0x2000200081c3e008
	46	#define L2_ES_W1C_VALUE 0xc03ffff800000000
	47	#define DRAM_ES_W1C_VALUE 0xfe00000000000000
	48
	49	#define DRAM_ERR_INJ_REG 0x8400000290
	50	#define DRAM_ERR_STAT_REG 0x8400000280
	51	#define ERROR_ADDR 0x20200000
	52
	53	#define DRAM_SCRUB_FREQ_REG 0x8400000018
	54	#define DRAM_SCRUB_ENB_REG 0x8400000040
	55
	56	#include "hboot.s"
	57	#include "asi_s.h"
	58	#include "err_defines.h"
	59
	60
	61	.text
	62	.global main
	63
	64
65	main:
66	ta T_CHANGE_HPRIV
67
68	! begin
69	get_th_id_o0:
70	ta T_RD_THID
71	cmp %o1, 0x0
72	be main_t0
73	nop
74	cmp %o1, 0x1
75	be main_t1
76	nop
77	cmp %o1, 0x2
78	be main_t2
79	nop
80	cmp %o1, 0x3
81	be main_t3
82	nop
83	cmp %o1, 0x4
84	be main_t4
85	nop
86	cmp %o1, 0x5
87	be main_t5
88	nop
89	cmp %o1, 0x6
90	be main_t6
91	nop
92	cmp %o1, 0x7
93	be main_t7
94	nop
95
96	main_t0:
97	ba L2B0_Init
98	nop
99
100	L2B0_Init:
101	disable_l1:
102	ldxa [%g0] ASI_LSU_CONTROL, %l0
103	! Remove the lower 2 bits (I-Cache and D-Cache enables)
104	andn %l0, 0x3, %l0
105	stxa %l0, [%g0] ASI_LSU_CONTROL
106
107
108	clear_DRAM_ESR_MCU0_B0:
109	clr %l0
110	clr %l1
111	setx DRAM_ES_W1C_VALUE, %l0, %g2
112	setx 0x8400000280, %l1, %g6
113	stx %g2, [%g6]
114	clear_L2_ESR_BANK_0:
115	clr %l0
116	clr %l1
117	setx L2_ES_W1C_VALUE, %l0, %g4
118	setx 0xbb00000000, %l1, %g7
119	stx %g4, [%g7]
120
121	clr %g1
122	mov 0x1, %g1
123	sllx %g1, 32, %g1
124	clr %g2
125	mov 0x1, %g2
126	sllx %g2, 22, %g2
127	clr %g3
128	mov 100, %g3
129
130	ld_from_L2_bank0:
131	ldx [%g1], %l7
132	membar 0x40
133	add %g1, %g2, %g1
134	sub %g3, 1, %g3
135	brnz %g3,ld_from_L2_bank0
136	nop
137
138	check_DRAM_ESR_MCU0_DAC_and_MEC_B0:
139	clr %l1
140	mov 0x1, %l1
141	sllx %l1, 61, %l1
142	clr %l2
143	mov 0x1, %l2
144	sllx %l2, 62, %l2
145	or %l1, %l2, %l1
146	clr %l3
147	set 0xffff, %l3
148	ldx [%g6], %l0
149	andn %l0, %l3, %l0
150	cmp %l0, %l1
151	bne %xcc, test_fail
152	nop
153
154	check_L2_ESR_Bank_0_DAC_and_MEC:
155	clr %l1
156	mov 0x1, %l1
157	sllx %l1, 42, %l1
158	clr %l2
159	mov 0x1, %l2
160	sllx %l2, 62, %l2
161	or %l1, %l2, %l1
162	clr %l3
163	mov 0x1, %l3
164	sllx %l3, 36, %l3
165	or %l1, %l3, %l1
166	ldx [%g7], %l0
167	clr %l2
168	clr %l3
169	setx 0xf03fffffffffffff, %l2, %l3 !get rid of VCID [59:54]
170	and %l0, %l3, %l0
171	cmp %l0, %l1
172	bne %xcc, test_fail
173	nop
174
175	ba test_pass
176	nop
177
178	main_t1:
179	ba L2B1_Init
180	nop
181
182	L2B1_Init:
183
184	clear_DRAM_ESR_MCU0_B1:
185	clr %l0
186	clr %l1
187	setx DRAM_ES_W1C_VALUE, %l0, %g2
188	setx 0x8400000280, %l1, %g6
189	stx %g2, [%g6]
190	clear_L2_ESR_BANK_1:
191	clr %l0
192	clr %l1
193	setx L2_ES_W1C_VALUE, %l0, %g4
194	setx 0xbb00000040, %l1, %g7
195	stx %g4, [%g7]
196
197	clr %g1
198	mov 0x1, %g1
199	sllx %g1, 32, %g1
200	add %g1, 0x40, %g1
201	clr %g2
202	mov 0x1, %g2
203	sllx %g2, 22, %g2
204	clr %g3
205	mov 100, %g3
206
207	ld_from_L2_bank1:
208	ldx [%g1], %l7
209	membar 0x40
210	add %g1, %g2, %g1
211	sub %g3, 1, %g3
212	brnz %g3,ld_from_L2_bank1
213	nop
214
215	check_DRAM_ESR_MCU0_DAC_and_MEC_B1:
216	clr %l1
217	mov 0x1, %l1
218	sllx %l1, 61, %l1
219	clr %l2
220	mov 0x1, %l2
221	sllx %l2, 62, %l2
222	or %l1, %l2, %l1
223	clr %l3
224	set 0xffff, %l3
225	ldx [%g6], %l0
226	andn %l0, %l3, %l0
227	cmp %l0, %l1
228	bne %xcc, test_fail
229	nop
230
231	check_L2_ESR_Bank_1_DAC_and_MEC:
232	clr %l1
233	mov 0x1, %l1
234	sllx %l1, 42, %l1
235	clr %l2
236	mov 0x1, %l2
237	sllx %l2, 62, %l2
238	or %l1, %l2, %l1
239	clr %l3
240	mov 0x1, %l3
241	sllx %l3, 36, %l3
242	or %l1, %l3, %l1
243	ldx [%g7], %l0
244	clr %l2
245	clr %l3
246	setx 0xf03fffffffffffff, %l2, %l3 !get rid of VCID [59:54]
247	and %l0, %l3, %l0
248	cmp %l0, %l1
249	bne %xcc, test_fail
250	nop
251
252	ba test_pass
253	nop
254
255	main_t2:
256	ba L2B2_Init
257	nop
258
259	L2B2_Init:
260
261	clear_DRAM_ESR_MCU1_B2:
262	clr %l0
263	clr %l1
264	setx DRAM_ES_W1C_VALUE, %l0, %g2
265	setx 0x8400001280, %l1, %g6
266	stx %g2, [%g6]
267	clear_L2_ESR_BANK_2:
268	clr %l0
269	clr %l1
270	setx L2_ES_W1C_VALUE, %l0, %g4
271	setx 0xbb00000080, %l1, %g7
272	stx %g4, [%g7]
273
274	clr %g1
275	mov 0x1, %g1
276	sllx %g1, 32, %g1
277	add %g1, 0x80, %g1
278	clr %g2
279	mov 0x1, %g2
280	sllx %g2, 22, %g2
281	clr %g3
282	mov 100, %g3
283
284	ld_from_L2_bank2:
285	ldx [%g1], %l7
286	membar 0x40
287	add %g1, %g2, %g1
288	sub %g3, 1, %g3
289	brnz %g3,ld_from_L2_bank2
290	nop
291
292	check_DRAM_ESR_MCU1_DAC_and_MEC_B2:
293	clr %l1
294	mov 0x1, %l1
295	sllx %l1, 61, %l1
296	clr %l2
297	mov 0x1, %l2
298	sllx %l2, 62, %l2
299	or %l1, %l2, %l1
300	clr %l3
301	set 0xffff, %l3
302	ldx [%g6], %l0
303	andn %l0, %l3, %l0
304	cmp %l0, %l1
305	bne %xcc, test_fail
306	nop
307
308	check_L2_ESR_Bank_2_DAC_and_MEC:
309	clr %l1
310	mov 0x1, %l1
311	sllx %l1, 42, %l1
312	clr %l2
313	mov 0x1, %l2
314	sllx %l2, 62, %l2
315	or %l1, %l2, %l1
316	clr %l3
317	mov 0x1, %l3
318	sllx %l3, 36, %l3
319	or %l1, %l3, %l1
320	ldx [%g7], %l0
321	clr %l2
322	clr %l3
323	setx 0xf03fffffffffffff, %l2, %l3 !get rid of VCID [59:54]
324	and %l0, %l3, %l0
325	cmp %l0, %l1
326	bne %xcc, test_fail
327	nop
328
329	ba test_pass
330	nop
331
332	main_t3:
333	ba L2B3_Init
334	nop
335
336	L2B3_Init:
337
338	clear_DRAM_ESR_MCU1_B3:
339	clr %l0
340	clr %l1
341	setx DRAM_ES_W1C_VALUE, %l0, %g2
342	setx 0x8400001280, %l1, %g6
343	stx %g2, [%g6]
344	clear_L2_ESR_BANK_3:
345	clr %l0
346	clr %l1
347	setx L2_ES_W1C_VALUE, %l0, %g4
348	setx 0xbb000000c0, %l1, %g7
349	stx %g4, [%g7]
350
351	clr %g1
352	mov 0x1, %g1
353	sllx %g1, 32, %g1
354	add %g1, 0xc0, %g1
355	clr %g2
356	mov 0x1, %g2
357	sllx %g2, 22, %g2
358	clr %g3
359	mov 100, %g3
360
361	ld_from_L2_bank3:
362	ldx [%g1], %l7
363	membar 0x40
364	add %g1, %g2, %g1
365	sub %g3, 1, %g3
366	brnz %g3,ld_from_L2_bank3
367	nop
368
369	check_DRAM_ESR_MCU1_DAC_and_MEC_B3:
370	clr %l1
371	mov 0x1, %l1
372	sllx %l1, 61, %l1
373	clr %l2
374	mov 0x1, %l2
375	sllx %l2, 62, %l2
376	or %l1, %l2, %l1
377	clr %l3
378	set 0xffff, %l3
379	ldx [%g6], %l0
380	andn %l0, %l3, %l0
381	cmp %l0, %l1
382	bne %xcc, test_fail
383	nop
384
385	check_L2_ESR_Bank_3_DAC_and_MEC:
386	clr %l1
387	mov 0x1, %l1
388	sllx %l1, 42, %l1
389	clr %l2
390	mov 0x1, %l2
391	sllx %l2, 62, %l2
392	or %l1, %l2, %l1
393	clr %l3
394	mov 0x1, %l3
395	sllx %l3, 36, %l3
396	or %l1, %l3, %l1
397	ldx [%g7], %l0
398	clr %l2
399	clr %l3
400	setx 0xf03fffffffffffff, %l2, %l3 !get rid of VCID [59:54]
401	and %l0, %l3, %l0
402	cmp %l0, %l1
403	bne %xcc, test_fail
404	nop
405
406	ba test_pass
407	nop
408
409	main_t4:
410	ba L2B4_Init
411	nop
412
413	L2B4_Init:
414
415	clear_DRAM_ESR_MCU2_B4:
416	clr %l0
417	clr %l1
418	setx DRAM_ES_W1C_VALUE, %l0, %g2
419	setx 0x8400002280, %l1, %g6
420	stx %g2, [%g6]
421	clear_L2_ESR_BANK_4:
422	clr %l0
423	clr %l1
424	setx L2_ES_W1C_VALUE, %l0, %g4
425	setx 0xbb00000100, %l1, %g7
426	stx %g4, [%g7]
427
428	clr %g1
429	mov 0x1, %g1
430	sllx %g1, 32, %g1
431	add %g1, 0x100, %g1
432	clr %g2
433	mov 0x1, %g2
434	sllx %g2, 22, %g2
435	clr %g3
436	mov 100, %g3
437
438	ld_from_L2_bank4:
439	ldx [%g1], %l7
440	membar 0x40
441	add %g1, %g2, %g1
442	sub %g3, 1, %g3
443	brnz %g3,ld_from_L2_bank4
444	nop
445
446	check_DRAM_ESR_MCU2_DAC_and_MEC_B4:
447	clr %l1
448	mov 0x1, %l1
449	sllx %l1, 61, %l1
450	clr %l2
451	mov 0x1, %l2
452	sllx %l2, 62, %l2
453	or %l1, %l2, %l1
454	clr %l3
455	set 0xffff, %l3
456	ldx [%g6], %l0
457	andn %l0, %l3, %l0
458	cmp %l0, %l1
459	bne %xcc, test_fail
460	nop
461
462	check_L2_ESR_Bank_4_DAC_and_MEC:
463	clr %l1
464	mov 0x1, %l1
465	sllx %l1, 42, %l1
466	clr %l2
467	mov 0x1, %l2
468	sllx %l2, 62, %l2
469	or %l1, %l2, %l1
470	clr %l3
471	mov 0x1, %l3
472	sllx %l3, 36, %l3
473	or %l1, %l3, %l1
474	ldx [%g7], %l0
475	clr %l2
476	clr %l3
477	setx 0xf03fffffffffffff, %l2, %l3 !get rid of VCID [59:54]
478	and %l0, %l3, %l0
479	cmp %l0, %l1
480	bne %xcc, test_fail
481	nop
482
483	ba test_pass
484	nop
485
486	main_t5:
487	ba L2B5_Init
488	nop
489
490	L2B5_Init:
491
492	clear_DRAM_ESR_MCU2_B5:
493	clr %l0
494	clr %l1
495	setx DRAM_ES_W1C_VALUE, %l0, %g2
496	setx 0x8400002280, %l1, %g6
497	stx %g2, [%g6]
498	clear_L2_ESR_BANK_5:
499	clr %l0
500	clr %l1
501	setx L2_ES_W1C_VALUE, %l0, %g4
502	setx 0xbb00000140, %l1, %g7
503	stx %g4, [%g7]
504
505	clr %g1
506	mov 0x1, %g1
507	sllx %g1, 32, %g1
508	add %g1, 0x140, %g1
509	clr %g2
510	mov 0x1, %g2
511	sllx %g2, 22, %g2
512	clr %g3
513	mov 100, %g3
514
515	ld_from_L2_bank5:
516	ldx [%g1], %l7
517	membar 0x40
518	add %g1, %g2, %g1
519	sub %g3, 1, %g3
520	brnz %g3,ld_from_L2_bank5
521	nop
522
523	check_DRAM_ESR_MCU2_DAC_and_MEC_B5:
524	clr %l1
525	mov 0x1, %l1
526	sllx %l1, 61, %l1
527	clr %l2
528	mov 0x1, %l2
529	sllx %l2, 62, %l2
530	or %l1, %l2, %l1
531	clr %l3
532	set 0xffff, %l3
533	ldx [%g6], %l0
534	andn %l0, %l3, %l0
535	cmp %l0, %l1
536	bne %xcc, test_fail
537	nop
538
539	check_L2_ESR_Bank_5_DAC_and_MEC:
540	clr %l1
541	mov 0x1, %l1
542	sllx %l1, 42, %l1
543	clr %l2
544	mov 0x1, %l2
545	sllx %l2, 62, %l2
546	or %l1, %l2, %l1
547	clr %l3
548	mov 0x1, %l3
549	sllx %l3, 36, %l3
550	or %l1, %l3, %l1
551	ldx [%g7], %l0
552	clr %l2
553	clr %l3
554	setx 0xf03fffffffffffff, %l2, %l3 !get rid of VCID [59:54]
555	and %l0, %l3, %l0
556	cmp %l0, %l1
557	bne %xcc, test_fail
558	nop
559
560	ba test_pass
561	nop
562
563	main_t6:
564	ba L2B6_Init
565	nop
566
567	L2B6_Init:
568
569	clear_DRAM_ESR_MCU3_B6:
570	clr %l0
571	clr %l1
572	setx DRAM_ES_W1C_VALUE, %l0, %g2
573	setx 0x8400003280, %l1, %g6
574	stx %g2, [%g6]
575	clear_L2_ESR_BANK_6:
576	clr %l0
577	clr %l1
578	setx L2_ES_W1C_VALUE, %l0, %g4
579	setx 0xbb00000180, %l1, %g7
580	stx %g4, [%g7]
581
582	clr %g1
583	mov 0x1, %g1
584	sllx %g1, 32, %g1
585	add %g1, 0x180, %g1
586	clr %g2
587	mov 0x1, %g2
588	sllx %g2, 22, %g2
589	clr %g3
590	mov 100, %g3
591
592	ld_from_L2_bank6:
593	ldx [%g1], %l7
594	membar 0x40
595	add %g1, %g2, %g1
596	sub %g3, 1, %g3
597	brnz %g3,ld_from_L2_bank6
598	nop
599
600	check_DRAM_ESR_MCU3_DAC_and_MEC_B6:
601	clr %l1
602	mov 0x1, %l1
603	sllx %l1, 61, %l1
604	clr %l2
605	mov 0x1, %l2
606	sllx %l2, 62, %l2
607	or %l1, %l2, %l1
608	clr %l3
609	set 0xffff, %l3
610	ldx [%g6], %l0
611	andn %l0, %l3, %l0
612	cmp %l0, %l1
613	bne %xcc, test_fail
614	nop
615
616	check_L2_ESR_Bank_6_DAC_and_MEC:
617	clr %l1
618	mov 0x1, %l1
619	sllx %l1, 42, %l1
620	clr %l2
621	mov 0x1, %l2
622	sllx %l2, 62, %l2
623	or %l1, %l2, %l1
624	clr %l3
625	mov 0x1, %l3
626	sllx %l3, 36, %l3
627	or %l1, %l3, %l1
628	ldx [%g7], %l0
629	clr %l2
630	clr %l3
631	setx 0xf03fffffffffffff, %l2, %l3 !get rid of VCID [59:54]
632	and %l0, %l3, %l0
633	cmp %l0, %l1
634	bne %xcc, test_fail
635	nop
636
637	ba test_pass
638	nop
639
640	main_t7:
641	ba L2B7_Init
642	nop
643
644	L2B7_Init:
645
646	clear_DRAM_ESR_MCU3_B7:
647	clr %l0
648	clr %l1
649	setx DRAM_ES_W1C_VALUE, %l0, %g2
650	setx 0x8400003280, %l1, %g6
651	stx %g2, [%g6]
652	clear_L2_ESR_BANK_7:
653	clr %l0
654	clr %l1
655	setx L2_ES_W1C_VALUE, %l0, %g4
656	setx 0xbb000001c0, %l1, %g7
657	stx %g4, [%g7]
658
659	clr %g1
660	mov 0x1, %g1
661	sllx %g1, 32, %g1
662	add %g1, 0x1c0, %g1
663	clr %g2
664	mov 0x1, %g2
665	sllx %g2, 22, %g2
666	clr %g3
667	mov 100, %g3
668
669	ld_from_L2_bank7:
670	ldx [%g1], %l7
671	membar 0x40
672	add %g1, %g2, %g1
673	sub %g3, 1, %g3
674	brnz %g3,ld_from_L2_bank7
675	nop
676
677	check_DRAM_ESR_MCU3_DAC_and_MEC_B7:
678	clr %l1
679	mov 0x1, %l1
680	sllx %l1, 61, %l1
681	clr %l2
682	mov 0x1, %l2
683	sllx %l2, 62, %l2
684	or %l1, %l2, %l1
685	clr %l3
686	set 0xffff, %l3
687	ldx [%g6], %l0
688	andn %l0, %l3, %l0
689	cmp %l0, %l1
690	bne %xcc, test_fail
691	nop
692
693	check_L2_ESR_Bank_7_DAC_and_MEC:
694	clr %l1
695	mov 0x1, %l1
696	sllx %l1, 42, %l1
697	clr %l2
698	mov 0x1, %l2
699	sllx %l2, 62, %l2
700	or %l1, %l2, %l1
701	clr %l3
702	mov 0x1, %l3
703	sllx %l3, 36, %l3
704	or %l1, %l3, %l1
705	ldx [%g7], %l0
706	clr %l2
707	clr %l3
708	setx 0xf03fffffffffffff, %l2, %l3 !get rid of VCID [59:54]
709	and %l0, %l3, %l0
710	cmp %l0, %l1
711	bne %xcc, test_fail
712	nop
713
714	ba test_pass
715	nop
716
717	/*******************************************************
718	* Exit code
719	*******************************************************/
720
721	test_pass:
722	ta T_GOOD_TRAP
723
724
725	test_fail:
726	ta T_BAD_TRAP
727