Commit | Line | Data |
---|---|---|
86530b38 AT |
1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: n2_err_adv_mcu_CRC_MULTI_ECC.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define MAIN_PAGE_NUCLEUS_ALSO | |
39 | #define MAIN_PAGE_HV_ALSO | |
40 | ||
41 | #define L2_ERR_STAT_REG 0xAB00000000 | |
42 | #define L2_ERR_ADDR_REG 0xAC00000000 | |
43 | ||
44 | #define TEST_DATA1 0x1000100081c3e008 | |
45 | #define TEST_DATA2 0x2000200081c3e008 | |
46 | #define L2_ES_W1C_VALUE 0xc03ffff800000000 | |
47 | #define DRAM_ES_W1C_VALUE 0xfe00000000000000 | |
48 | ||
49 | #define DRAM_ERR_INJ_REG 0x8400000290 | |
50 | #define DRAM_ERR_STAT_REG 0x8400000280 | |
51 | #define ERROR_ADDR 0x20200000 | |
52 | ||
53 | #define DRAM_SCRUB_FREQ_REG 0x8400000018 | |
54 | #define DRAM_SCRUB_ENB_REG 0x8400000040 | |
55 | ||
56 | #include "hboot.s" | |
57 | #include "asi_s.h" | |
58 | #include "err_defines.h" | |
59 | ||
60 | ||
61 | .text | |
62 | .global main | |
63 | ||
64 | ||
65 | main: | |
66 | ta T_CHANGE_HPRIV | |
67 | ||
68 | disable_l1: | |
69 | ldxa [%g0] ASI_LSU_CONTROL, %l0 | |
70 | ! Remove the lower 2 bits (I-Cache and D-Cache enables) | |
71 | andn %l0, 0x3, %l0 | |
72 | stxa %l0, [%g0] ASI_LSU_CONTROL | |
73 | ||
74 | ! begin | |
75 | clear_DRAM_ESR: | |
76 | clr %l0 | |
77 | clr %l1 | |
78 | setx DRAM_ES_W1C_VALUE, %l0, %g2 | |
79 | setx 0x8400000280, %l1, %g6 | |
80 | stx %g2, [%g6] | |
81 | clear_L2_ESR: | |
82 | clr %l0 | |
83 | clr %l1 | |
84 | setx L2_ES_W1C_VALUE, %l0, %g4 | |
85 | setx 0xbb00000000, %l1, %g7 | |
86 | stx %g4, [%g7] | |
87 | ||
88 | set_DRAM_error_inject_mcu0: | |
89 | mov 0x2, %l1 | |
90 | !mov 0x1, %l2 | |
91 | !sllx %l2, DRAM_EI_SSHOT, %l2 | |
92 | !or %l1, %l2, %l1 | |
93 | mov 0x1, %l3 | |
94 | sllx %l3, 31, %l3 | |
95 | or %l1, %l3, %l1 | |
96 | setx 0x8400000290, %l0, %g4 | |
97 | stx %l1, [%g4] | |
98 | membar 0x40 | |
99 | ||
100 | set_L2_Direct_Mapped_Mode: | |
101 | clr %l0 | |
102 | clr %g1 | |
103 | setx 0xa900000000, %l0, %g1 | |
104 | mov 0x2, %l0 | |
105 | stx %l0, [%g1] | |
106 | membar 0x40 | |
107 | ||
108 | clr %g1 | |
109 | clr %g2 | |
110 | clr %l1 | |
111 | setx 0x0123456789abcdef, %l1, %g2 | |
112 | clr %l2 | |
113 | mov 0x1, %l2 | |
114 | sllx %l2, 22, %l2 | |
115 | clr %l3 | |
116 | mov 100, %l3 | |
117 | st_to_L2_way0_and_MCU0: | |
118 | stx %g2, [%g1] | |
119 | membar 0x40 | |
120 | clr %l4 | |
121 | add %g1, %l2, %l4 | |
122 | stx %g2, [%l4] | |
123 | membar 0x40 | |
124 | add %g1, 0x200, %g1 | |
125 | sub %l3, 1, %l3 | |
126 | brnz %l3,st_to_L2_way0_and_MCU0 | |
127 | nop | |
128 | ||
129 | clr %g1 | |
130 | clr %l2 | |
131 | mov 200, %l2 | |
132 | ld_from_error_and_nonerror_address: | |
133 | ld [%g1], %l1 | |
134 | membar 0x40 | |
135 | add %g1, 0x100, %g1 | |
136 | sub %l2, 1, %l2 | |
137 | brnz %l2,ld_from_error_and_nonerror_address | |
138 | nop | |
139 | ||
140 | clr %g1 | |
141 | mov 0x1, %g1 | |
142 | sllx %g1, 32, %g1 | |
143 | clr %g2 | |
144 | mov 0x1, %g2 | |
145 | sllx %g2, 22, %g2 | |
146 | clr %g3 | |
147 | mov 100, %g3 | |
148 | ||
149 | ld_from_L2_bank0_for_CRC: | |
150 | ldx [%g1], %l1 | |
151 | membar 0x40 | |
152 | add %g1, %g2, %g1 | |
153 | sub %g3, 1, %g3 | |
154 | brnz %g3,ld_from_L2_bank0_for_CRC | |
155 | nop | |
156 | ||
157 | check_DRAM_ESR_FBR: | |
158 | !clr %l1 | |
159 | !mov 0x1, %l1 | |
160 | !sllx %l1, 54, %l1 | |
161 | !clr %l2 | |
162 | !mov 0x1, %l2 | |
163 | !sllx %l2, 62, %l2 | |
164 | !or %l1, %l2, %l1 | |
165 | !clr %l3 | |
166 | !mov 0x1, %l3 | |
167 | !sllx %l3, 61, %l3 | |
168 | !or %l1, %l3, %l1 | |
169 | ldx [%g6], %l0 | |
170 | clr %l4 | |
171 | set 0xffff, %l4 | |
172 | andn %l0, %l4, %l0 | |
173 | !cmp %l0, %l1 | |
174 | !bne %xcc, test_fail | |
175 | !nop | |
176 | ||
177 | check_L2_ESR_DSC: | |
178 | !clr %l1 | |
179 | !mov 0x1, %l1 | |
180 | !sllx %l1, 38, %l1 | |
181 | !clr %l2 | |
182 | !mov 0x1, %l2 | |
183 | !sllx %l2, 42, %l2 | |
184 | !or %l1, %l2, %l1 | |
185 | !clr %l3 | |
186 | !mov 0x1, %l3 | |
187 | !sllx %l3, 36, %l3 | |
188 | !or %l1, %l3, %l1 | |
189 | !clr %l4 | |
190 | !mov 0x1, %l4 | |
191 | !sllx %l4, 62, %l4 | |
192 | !or %l1, %l4, %l1 | |
193 | ldx [%g7], %l0 | |
194 | !cmp %l0, %l1 | |
195 | !bne %xcc, test_fail | |
196 | !nop | |
197 | ||
198 | clr %g5 | |
199 | clr %l6 | |
200 | setx 0x8400000288, %l6, %g5 | |
201 | clr %l7 | |
202 | ldx [%g5], %l7 | |
203 | membar 0x40 | |
204 | clr %g5 | |
205 | clr %l6 | |
206 | setx 0xbc00000000, %l6, %g5 | |
207 | clr %l7 | |
208 | ldx [%g5], %l7 | |
209 | membar 0x40 | |
210 | clr %g5 | |
211 | clr %l6 | |
212 | setx 0xbc00000040, %l6, %g5 | |
213 | clr %l7 | |
214 | ldx [%g5], %l7 | |
215 | membar 0x40 | |
216 | ||
217 | ba test_pass | |
218 | nop | |
219 | ||
220 | /******************************************************* | |
221 | * Exit code | |
222 | *******************************************************/ | |
223 | ||
224 | test_pass: | |
225 | ta T_GOOD_TRAP | |
226 | ||
227 | test_fail: | |
228 | ta T_BAD_TRAP | |
229 |