projects / OpenSPARC-T2-DV / blame
? search:
summary | tags | clone url | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / mcu / n2_err_adv_mcu_trap_h.s
CommitLineData
86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: n2_err_adv_mcu_trap_h.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#include "mcu_init.s"
39
40
41 setx 0xf49329e47f5709d5, %g5, %r17 !64 bit data
42 setx 0x70a9ffe2826e1f25, %g5, %r19 !64 bit data
43 setx 0xc697226b5ac86d81, %g5, %r24 !64 bit data
44
45 setx 0x80900000, %g5, %r18 !40 bit addr
46 setx 0x80f00000, %g5, %r16 !40 bit addr
47
48 mov 1, %g2
49
501:
51 wr %g0, 4, %asi
52
53 !before IJ_generate
54
55myinst_1:
56!note: quad word is 16 bytes, double word is 8 bytes, word is 4 bytes, half word is 2 bytes
57myinst_2:
58 .word 0xe2348000 ! 1: STH_R sth %r17, [%r18 + %r0]
59 setx 0x0000400000, %l0, %l1
60 add %r18, %l1, %r18
61 add %r16, %l1, %r16
62!note: the 2nd store will evict the 1st store to memory
63 .word 0xe2b48080 ! 1: STHA_R stha %r17, [%r18 + %r0] 0x04
64myinst_4:
65 .word 0xe86c8000 ! 1: LDSTUB_R ldstub %r20, [%r18 + %r0]
66myinst_5:
67 .word 0xc36c8000 ! 1: PREFETCH_R prefetch [%r18 + %r0], #one_read
68myinst_6:
69 .word 0xe3e4a013 ! 1: CASA_R casa [%r18] %asi, %r19, %r17
70
71 wr %g0, 4, %asi
72
73myinst_7:
74 .word 0xd0dc0080 ! 1: LDXA_R ldxa [%r16, %r0] 0x04, %r8
75myinst_8:
76 .word 0xe2f40080 ! 1: STXA_R stxa %r17, [%r16 + %r0] 0x04
77myinst_9:
78 .word 0xe3f42018 ! 1: CASXA_R casxa [%r16]%asi, %r24, %r17
79
80 !after IJ_generate
81
82 add %r18, 48, %r18
83 add %r16, 48, %r16
84
85 dec %g2
86 brnz %g2, 1b
87 nop
88
89
90 setx 0xcea373f097c33f29, %g5, %r17 !64 bit data
91 setx 0xba2183541cc0a478, %g5, %r19 !64 bit data
92 setx 0x958213587001c0ce, %g5, %r24 !64 bit data
93
94 setx 0x80300000, %g5, %r18 !40 bit addr
95 setx 0x80300000, %g5, %r16 !40 bit addr
96
97 mov 3, %g2
98
991:
100 wr %g0, 4, %asi
101
102 !before IJ_generate
103
104myinst_10:
105!note: quad word is 16 bytes, double word is 8 bytes, word is 4 bytes, half word is 2 bytes
106 .word 0xe8948080 ! 1: LDUHA_R lduha [%r18, %r0] 0x04, %r20
107myinst_11:
108 .word 0xe22c8000 ! 1: STB_R stb %r17, [%r18 + %r0]
109 setx 0x0000400000, %l0, %l1
110 add %r18, %l1, %r18
111 add %r16, %l1, %r16
112!note: the 2nd store will evict the 1st store to memory
113 .word 0xe22c8000 ! 1: STB_R stb %r17, [%r18 + %r0]
114myinst_13:
115 .word 0xe86c8000 ! 1: LDSTUB_R ldstub %r20, [%r18 + %r0]
116myinst_14:
117 .word 0xc36c8000 ! 1: PREFETCH_R prefetch [%r18 + %r0], #one_read
118myinst_15:
119 .word 0xe3e4a013 ! 1: CASA_R casa [%r18] %asi, %r19, %r17
120
121 wr %g0, 4, %asi
122
123myinst_16:
124 .word 0xd05c0000 ! 1: LDX_R ldx [%r16 + %r0], %r8
125myinst_17:
126 .word 0xe2f40080 ! 1: STXA_R stxa %r17, [%r16 + %r0] 0x04
127myinst_18:
128 .word 0xe3f42018 ! 1: CASXA_R casxa [%r16]%asi, %r24, %r17
129
130 !after IJ_generate
131
132 add %r18, 48, %r18
133 add %r16, 32, %r16
134
135 dec %g2
136 brnz %g2, 1b
137 nop
138
139
140 setx 0xb0bf1ee97861c614, %g5, %r17 !64 bit data
141 setx 0x5112225340e249b2, %g5, %r19 !64 bit data
142 setx 0xc651adb586f5cc7c, %g5, %r24 !64 bit data
143
144 setx 0x80c00000, %g5, %r18 !40 bit addr
145 setx 0x80000000, %g5, %r16 !40 bit addr
146
147 mov 1, %g2
148
1491:
150 wr %g0, 4, %asi
151
152 !before IJ_generate
153
154myinst_19:
155!note: quad word is 16 bytes, double word is 8 bytes, word is 4 bytes, half word is 2 bytes
156 .word 0xe8048000 ! 2: LDUW_R lduw [%r18 + %r0], %r20
157myinst_20:
158 .word 0xe2348000 ! 1: STH_R sth %r17, [%r18 + %r0]
159 setx 0x0000400000, %l0, %l1
160 add %r18, %l1, %r18
161 add %r16, %l1, %r16
162!note: the 2nd store will evict the 1st store to memory
163 .word 0xe22c8000 ! 1: STB_R stb %r17, [%r18 + %r0]
164myinst_22:
165 .word 0xe86c8000 ! 1: LDSTUB_R ldstub %r20, [%r18 + %r0]
166myinst_23:
167 .word 0xc3ec8080 ! 1: PREFETCHA_R prefetcha [%r18, %r0] 0x04, #one_read
168myinst_24:
169 .word 0xe3e4a013 ! 1: CASA_R casa [%r18] %asi, %r19, %r17
170
171 wr %g0, 4, %asi
172
173myinst_25:
174 .word 0xd05c0000 ! 1: LDX_R ldx [%r16 + %r0], %r8
175myinst_26:
176 .word 0xe2f40080 ! 1: STXA_R stxa %r17, [%r16 + %r0] 0x04
177myinst_27:
178 .word 0xe3f42018 ! 1: CASXA_R casxa [%r16]%asi, %r24, %r17
179
180 !after IJ_generate
181
182 add %r18, 16, %r18
183 add %r16, 0, %r16
184
185 dec %g2
186 brnz %g2, 1b
187 nop
188
189
190 setx 0x7cd98ee6d6309320, %g5, %r17 !64 bit data
191 setx 0xec91f5828cd4df90, %g5, %r19 !64 bit data
192 setx 0x8144a761ed49a47f, %g5, %r24 !64 bit data
193
194 setx 0x80900000, %g5, %r18 !40 bit addr
195 setx 0x80400000, %g5, %r16 !40 bit addr
196
197 mov 3, %g2
198
1991:
200 wr %g0, 4, %asi
201
202 !before IJ_generate
203
204myinst_28:
205!note: quad word is 16 bytes, double word is 8 bytes, word is 4 bytes, half word is 2 bytes
206 .word 0xe8148000 ! 3: LDUH_R lduh [%r18 + %r0], %r20
207myinst_29:
208 .word 0xe2a48080 ! 1: STWA_R stwa %r17, [%r18 + %r0] 0x04
209 setx 0x0000400000, %l0, %l1
210 add %r18, %l1, %r18
211 add %r16, %l1, %r16
212!note: the 2nd store will evict the 1st store to memory
213 .word 0xe2248000 ! 1: STW_R stw %r17, [%r18 + %r0]
214myinst_31:
215 .word 0xe86c8000 ! 1: LDSTUB_R ldstub %r20, [%r18 + %r0]
216myinst_32:
217 .word 0xc3ec8080 ! 1: PREFETCHA_R prefetcha [%r18, %r0] 0x04, #one_read
218myinst_33:
219 .word 0xe3e4a013 ! 1: CASA_R casa [%r18] %asi, %r19, %r17
220
221 wr %g0, 4, %asi
222
223myinst_34:
224 .word 0xd0dc0080 ! 1: LDXA_R ldxa [%r16, %r0] 0x04, %r8
225myinst_35:
226 .word 0xe2f40080 ! 1: STXA_R stxa %r17, [%r16 + %r0] 0x04
227myinst_36:
228 .word 0xe3f42018 ! 1: CASXA_R casxa [%r16]%asi, %r24, %r17
229
230 !after IJ_generate
231
232 add %r18, 32, %r18
233 add %r16, 0, %r16
234
235 dec %g2
236 brnz %g2, 1b
237 nop
238
239
240 setx 0xae49a2c8121fd64d, %g5, %r17 !64 bit data
241 setx 0xa47036f8425976e1, %g5, %r19 !64 bit data
242 setx 0xfc690373087a20d0, %g5, %r24 !64 bit data
243
244 setx 0x80500000, %g5, %r18 !40 bit addr
245 setx 0x80f00000, %g5, %r16 !40 bit addr
246
247 mov 1, %g2
248
2491:
250 wr %g0, 4, %asi
251
252 !before IJ_generate
253
254myinst_37:
255!note: quad word is 16 bytes, double word is 8 bytes, word is 4 bytes, half word is 2 bytes
256 .word 0xe8548000 ! 4: LDSH_R ldsh [%r18 + %r0], %r20
257myinst_38:
258 .word 0xe2b48080 ! 1: STHA_R stha %r17, [%r18 + %r0] 0x04
259 setx 0x0000400000, %l0, %l1
260 add %r18, %l1, %r18
261 add %r16, %l1, %r16
262!note: the 2nd store will evict the 1st store to memory
263 .word 0xe22c8000 ! 1: STB_R stb %r17, [%r18 + %r0]
264myinst_40:
265 .word 0xe8ec8080 ! 1: LDSTUBA_R ldstuba %r20, [%r18 + %r0] 0x04
266myinst_41:
267 .word 0xc3ec8080 ! 1: PREFETCHA_R prefetcha [%r18, %r0] 0x04, #one_read
268myinst_42:
269 .word 0xe3e4a013 ! 1: CASA_R casa [%r18] %asi, %r19, %r17
270
271 wr %g0, 4, %asi
272
273myinst_43:
274 .word 0xd05c0000 ! 1: LDX_R ldx [%r16 + %r0], %r8
275myinst_44:
276 .word 0xe2f40080 ! 1: STXA_R stxa %r17, [%r16 + %r0] 0x04
277myinst_45:
278 .word 0xe3f42018 ! 1: CASXA_R casxa [%r16]%asi, %r24, %r17
279
280 !after IJ_generate
281
282 add %r18, 0, %r18
283 add %r16, 48, %r16
284
285 dec %g2
286 brnz %g2, 1b
287 nop
288
289
290 setx 0x603441645d6ba07d, %g5, %r17 !64 bit data
291 setx 0xa95f108b842819d1, %g5, %r19 !64 bit data
292 setx 0x3bb55f3682135956, %g5, %r24 !64 bit data
293
294 setx 0x80700000, %g5, %r18 !40 bit addr
295 setx 0x80600000, %g5, %r16 !40 bit addr
296
297 mov 3, %g2
298
2991:
300 wr %g0, 4, %asi
301
302 !before IJ_generate
303
304myinst_46:
305!note: quad word is 16 bytes, double word is 8 bytes, word is 4 bytes, half word is 2 bytes
306 .word 0xe8448000 ! 5: LDSW_R ldsw [%r18 + %r0], %r20
307myinst_47:
308 .word 0xe2b48080 ! 1: STHA_R stha %r17, [%r18 + %r0] 0x04
309 setx 0x0000400000, %l0, %l1
310 add %r18, %l1, %r18
311 add %r16, %l1, %r16
312!note: the 2nd store will evict the 1st store to memory
313 .word 0xe2a48080 ! 1: STWA_R stwa %r17, [%r18 + %r0] 0x04
314myinst_49:
315 .word 0xe8ec8080 ! 1: LDSTUBA_R ldstuba %r20, [%r18 + %r0] 0x04
316myinst_50:
317 .word 0xc36c8000 ! 1: PREFETCH_R prefetch [%r18 + %r0], #one_read
318myinst_51:
319 .word 0xe3e4a013 ! 1: CASA_R casa [%r18] %asi, %r19, %r17
320
321 wr %g0, 4, %asi
322
323myinst_52:
324 .word 0xd0dc0080 ! 1: LDXA_R ldxa [%r16, %r0] 0x04, %r8
325myinst_53:
326 .word 0xe2740000 ! 1: STX_R stx %r17, [%r16 + %r0]
327myinst_54:
328 .word 0xe3f42018 ! 1: CASXA_R casxa [%r16]%asi, %r24, %r17
329
330 !after IJ_generate
331
332 add %r18, 32, %r18
333 add %r16, 32, %r16
334
335 dec %g2
336 brnz %g2, 1b
337 nop
338
339
340 setx 0x4116ca14109f00ff, %g5, %r17 !64 bit data
341 setx 0xc11f0b13023f93a2, %g5, %r19 !64 bit data
342 setx 0xd10bc3646b9a545e, %g5, %r24 !64 bit data
343
344 setx 0x80600000, %g5, %r18 !40 bit addr
345 setx 0x80f00000, %g5, %r16 !40 bit addr
346
347 mov 3, %g2
348
3491:
350 wr %g0, 4, %asi
351
352 !before IJ_generate
353
354myinst_55:
355!note: quad word is 16 bytes, double word is 8 bytes, word is 4 bytes, half word is 2 bytes
356 .word 0xe8048000 ! 6: LDUW_R lduw [%r18 + %r0], %r20
357myinst_56:
358 .word 0xe2348000 ! 1: STH_R sth %r17, [%r18 + %r0]
359 setx 0x0000400000, %l0, %l1
360 add %r18, %l1, %r18
361 add %r16, %l1, %r16
362!note: the 2nd store will evict the 1st store to memory
363 .word 0xe2ac8080 ! 1: STBA_R stba %r17, [%r18 + %r0] 0x04
364myinst_58:
365 .word 0xe86c8000 ! 1: LDSTUB_R ldstub %r20, [%r18 + %r0]
366myinst_59:
367 .word 0xc3ec8080 ! 1: PREFETCHA_R prefetcha [%r18, %r0] 0x04, #one_read
368myinst_60:
369 .word 0xe3e4a013 ! 1: CASA_R casa [%r18] %asi, %r19, %r17
370
371 wr %g0, 4, %asi
372
373myinst_61:
374 .word 0xd05c0000 ! 1: LDX_R ldx [%r16 + %r0], %r8
375myinst_62:
376 .word 0xe2740000 ! 1: STX_R stx %r17, [%r16 + %r0]
377myinst_63:
378 .word 0xe3f42018 ! 1: CASXA_R casxa [%r16]%asi, %r24, %r17
379
380 !after IJ_generate
381
382 add %r18, 32, %r18
383 add %r16, 48, %r16
384
385 dec %g2
386 brnz %g2, 1b
387 nop
388
389
390 setx 0x19bd772f309e0767, %g5, %r17 !64 bit data
391 setx 0x2310aeb16e6e1826, %g5, %r19 !64 bit data
392 setx 0xced2c81555ad88b2, %g5, %r24 !64 bit data
393
394 setx 0x80700000, %g5, %r18 !40 bit addr
395 setx 0x80600000, %g5, %r16 !40 bit addr
396
397 mov 3, %g2
398
3991:
400 wr %g0, 4, %asi
401
402 !before IJ_generate
403
404myinst_64:
405!note: quad word is 16 bytes, double word is 8 bytes, word is 4 bytes, half word is 2 bytes
406 .word 0xe84c8000 ! 7: LDSB_R ldsb [%r18 + %r0], %r20
407myinst_65:
408 .word 0xe2b48080 ! 1: STHA_R stha %r17, [%r18 + %r0] 0x04
409 setx 0x0000400000, %l0, %l1
410 add %r18, %l1, %r18
411 add %r16, %l1, %r16
412!note: the 2nd store will evict the 1st store to memory
413 .word 0xe2a48080 ! 1: STWA_R stwa %r17, [%r18 + %r0] 0x04
414myinst_67:
415 .word 0xe86c8000 ! 1: LDSTUB_R ldstub %r20, [%r18 + %r0]
416myinst_68:
417 .word 0xc36c8000 ! 1: PREFETCH_R prefetch [%r18 + %r0], #one_read
418myinst_69:
419 .word 0xe3e4a013 ! 1: CASA_R casa [%r18] %asi, %r19, %r17
420
421 wr %g0, 4, %asi
422
423myinst_70:
424 .word 0xd05c0000 ! 1: LDX_R ldx [%r16 + %r0], %r8
425myinst_71:
426 .word 0xe2740000 ! 1: STX_R stx %r17, [%r16 + %r0]
427myinst_72:
428 .word 0xe3f42018 ! 1: CASXA_R casxa [%r16]%asi, %r24, %r17
429
430 !after IJ_generate
431
432 add %r18, 0, %r18
433 add %r16, 48, %r16
434
435 dec %g2
436 brnz %g2, 1b
437 nop
438
439
440 setx 0x7966720ec0aa3014, %g5, %r17 !64 bit data
441 setx 0xb7055810cd15872e, %g5, %r19 !64 bit data
442 setx 0x926b2cf52d6b06d6, %g5, %r24 !64 bit data
443
444 setx 0x80700000, %g5, %r18 !40 bit addr
445 setx 0x80d00000, %g5, %r16 !40 bit addr
446
447 mov 1, %g2
448
4491:
450 wr %g0, 4, %asi
451
452 !before IJ_generate
453
454myinst_73:
455!note: quad word is 16 bytes, double word is 8 bytes, word is 4 bytes, half word is 2 bytes
456 .word 0xe88c8080 ! 8: LDUBA_R lduba [%r18, %r0] 0x04, %r20
457myinst_74:
458 .word 0xe2ac8080 ! 1: STBA_R stba %r17, [%r18 + %r0] 0x04
459 setx 0x0000400000, %l0, %l1
460 add %r18, %l1, %r18
461 add %r16, %l1, %r16
462!note: the 2nd store will evict the 1st store to memory
463 .word 0xe2348000 ! 1: STH_R sth %r17, [%r18 + %r0]
464myinst_76:
465 .word 0xe8ec8080 ! 1: LDSTUBA_R ldstuba %r20, [%r18 + %r0] 0x04
466myinst_77:
467 .word 0xc3ec8080 ! 1: PREFETCHA_R prefetcha [%r18, %r0] 0x04, #one_read
468myinst_78:
469 .word 0xe3e4a013 ! 1: CASA_R casa [%r18] %asi, %r19, %r17
470
471 wr %g0, 4, %asi
472
473myinst_79:
474 .word 0xd0dc0080 ! 1: LDXA_R ldxa [%r16, %r0] 0x04, %r8
475myinst_80:
476 .word 0xe2740000 ! 1: STX_R stx %r17, [%r16 + %r0]
477myinst_81:
478 .word 0xe3f42018 ! 1: CASXA_R casxa [%r16]%asi, %r24, %r17
479
480 !after IJ_generate
481
482 add %r18, 0, %r18
483 add %r16, 16, %r16
484
485 dec %g2
486 brnz %g2, 1b
487 nop
488
489
490 setx 0x5d56071a3bb174b9, %g5, %r17 !64 bit data
491 setx 0x4e71628e93bd08dc, %g5, %r19 !64 bit data
492 setx 0x44a6781217861218, %g5, %r24 !64 bit data
493
494 setx 0x80a00000, %g5, %r18 !40 bit addr
495 setx 0x80a00000, %g5, %r16 !40 bit addr
496
497 mov 3, %g2
498
4991:
500 wr %g0, 4, %asi
501
502 !before IJ_generate
503
504myinst_82:
505!note: quad word is 16 bytes, double word is 8 bytes, word is 4 bytes, half word is 2 bytes
506 .word 0xe8448000 ! 9: LDSW_R ldsw [%r18 + %r0], %r20
507myinst_83:
508 .word 0xe22c8000 ! 1: STB_R stb %r17, [%r18 + %r0]
509 setx 0x0000400000, %l0, %l1
510 add %r18, %l1, %r18
511 add %r16, %l1, %r16
512!note: the 2nd store will evict the 1st store to memory
513 .word 0xe2248000 ! 1: STW_R stw %r17, [%r18 + %r0]
514myinst_85:
515 .word 0xe8ec8080 ! 1: LDSTUBA_R ldstuba %r20, [%r18 + %r0] 0x04
516myinst_86:
517 .word 0xc3ec8080 ! 1: PREFETCHA_R prefetcha [%r18, %r0] 0x04, #one_read
518myinst_87:
519 .word 0xe3e4a013 ! 1: CASA_R casa [%r18] %asi, %r19, %r17
520
521 wr %g0, 4, %asi
522
523myinst_88:
524 .word 0xd05c0000 ! 1: LDX_R ldx [%r16 + %r0], %r8
525myinst_89:
526 .word 0xe2740000 ! 1: STX_R stx %r17, [%r16 + %r0]
527myinst_90:
528 .word 0xe3f42018 ! 1: CASXA_R casxa [%r16]%asi, %r24, %r17
529
530 !after IJ_generate
531
532 add %r18, 32, %r18
533 add %r16, 48, %r16
534
535 dec %g2
536 brnz %g2, 1b
537 nop
538
539
540 setx 0xb8c3e9ac9ce27908, %g5, %r17 !64 bit data
541 setx 0x3750908c8b201bfd, %g5, %r19 !64 bit data
542 setx 0x748f25f714a57e2d, %g5, %r24 !64 bit data
543
544 setx 0x80100000, %g5, %r18 !40 bit addr
545 setx 0x80500000, %g5, %r16 !40 bit addr
546
547 mov 1, %g2
548
5491:
550 wr %g0, 4, %asi
551
552 !before IJ_generate
553
554myinst_91:
555!note: quad word is 16 bytes, double word is 8 bytes, word is 4 bytes, half word is 2 bytes
556 .word 0xe8148000 ! 10: LDUH_R lduh [%r18 + %r0], %r20
557myinst_92:
558 .word 0xe2ac8080 ! 1: STBA_R stba %r17, [%r18 + %r0] 0x04
559 setx 0x0000400000, %l0, %l1
560 add %r18, %l1, %r18
561 add %r16, %l1, %r16
562!note: the 2nd store will evict the 1st store to memory
563 .word 0xe2248000 ! 1: STW_R stw %r17, [%r18 + %r0]
564myinst_94:
565 .word 0xe86c8000 ! 1: LDSTUB_R ldstub %r20, [%r18 + %r0]
566myinst_95:
567 .word 0xc36c8000 ! 1: PREFETCH_R prefetch [%r18 + %r0], #one_read
568myinst_96:
569 .word 0xe3e4a013 ! 1: CASA_R casa [%r18] %asi, %r19, %r17
570
571 wr %g0, 4, %asi
572
573myinst_97:
574 .word 0xd0dc0080 ! 1: LDXA_R ldxa [%r16, %r0] 0x04, %r8
575myinst_98:
576 .word 0xe2740000 ! 1: STX_R stx %r17, [%r16 + %r0]
577myinst_99:
578 .word 0xe3f42018 ! 1: CASXA_R casxa [%r16]%asi, %r24, %r17
579
580 !after IJ_generate
581
582 add %r18, 16, %r18
583 add %r16, 0, %r16
584
585 dec %g2
586 brnz %g2, 1b
587 nop
588
589
590 setx 0x8f4949d0b46eee71, %g5, %r17 !64 bit data
591 setx 0x5eef141bd9ee5c9c, %g5, %r19 !64 bit data
592 setx 0xb542d02b02b11e5c, %g5, %r24 !64 bit data
593
594 setx 0x80300000, %g5, %r18 !40 bit addr
595 setx 0x80e00000, %g5, %r16 !40 bit addr
596
597 mov 1, %g2
598
5991:
600 wr %g0, 4, %asi
601
602 !before IJ_generate
603
604myinst_100:
605!note: quad word is 16 bytes, double word is 8 bytes, word is 4 bytes, half word is 2 bytes
606 .word 0xe8cc8080 ! 11: LDSBA_R ldsba [%r18, %r0] 0x04, %r20
607myinst_101:
608 .word 0xe2ac8080 ! 1: STBA_R stba %r17, [%r18 + %r0] 0x04
609 setx 0x0000400000, %l0, %l1
610 add %r18, %l1, %r18
611 add %r16, %l1, %r16
612!note: the 2nd store will evict the 1st store to memory
613 .word 0xe2348000 ! 1: STH_R sth %r17, [%r18 + %r0]
614myinst_103:
615 .word 0xe86c8000 ! 1: LDSTUB_R ldstub %r20, [%r18 + %r0]
616myinst_104:
617 .word 0xc36c8000 ! 1: PREFETCH_R prefetch [%r18 + %r0], #one_read
618myinst_105:
619 .word 0xe3e4a013 ! 1: CASA_R casa [%r18] %asi, %r19, %r17
620
621 wr %g0, 4, %asi
622
623myinst_106:
624 .word 0xd05c0000 ! 1: LDX_R ldx [%r16 + %r0], %r8
625myinst_107:
626 .word 0xe2f40080 ! 1: STXA_R stxa %r17, [%r16 + %r0] 0x04
627myinst_108:
628 .word 0xe3f42018 ! 1: CASXA_R casxa [%r16]%asi, %r24, %r17
629
630 !after IJ_generate
631
632 add %r18, 48, %r18
633 add %r16, 32, %r16
634
635 dec %g2
636 brnz %g2, 1b
637 nop
638
639
640 setx 0x0db59ad26afb5e20, %g5, %r17 !64 bit data
641 setx 0x9a2d08ed9f02194a, %g5, %r19 !64 bit data
642 setx 0xdc11604530e5e0ee, %g5, %r24 !64 bit data
643
644 setx 0x80f00000, %g5, %r18 !40 bit addr
645 setx 0x80400000, %g5, %r16 !40 bit addr
646
647 mov 1, %g2
648
6491:
650 wr %g0, 4, %asi
651
652 !before IJ_generate
653
654myinst_109:
655!note: quad word is 16 bytes, double word is 8 bytes, word is 4 bytes, half word is 2 bytes
656 .word 0xe8548000 ! 12: LDSH_R ldsh [%r18 + %r0], %r20
657myinst_110:
658 .word 0xe2a48080 ! 1: STWA_R stwa %r17, [%r18 + %r0] 0x04
659 setx 0x0000400000, %l0, %l1
660 add %r18, %l1, %r18
661 add %r16, %l1, %r16
662!note: the 2nd store will evict the 1st store to memory
663 .word 0xe2348000 ! 1: STH_R sth %r17, [%r18 + %r0]
664myinst_112:
665 .word 0xe86c8000 ! 1: LDSTUB_R ldstub %r20, [%r18 + %r0]
666myinst_113:
667 .word 0xc36c8000 ! 1: PREFETCH_R prefetch [%r18 + %r0], #one_read
668myinst_114:
669 .word 0xe3e4a013 ! 1: CASA_R casa [%r18] %asi, %r19, %r17
670
671 wr %g0, 4, %asi
672
673myinst_115:
674 .word 0xd05c0000 ! 1: LDX_R ldx [%r16 + %r0], %r8
675myinst_116:
676 .word 0xe2f40080 ! 1: STXA_R stxa %r17, [%r16 + %r0] 0x04
677myinst_117:
678 .word 0xe3f42018 ! 1: CASXA_R casxa [%r16]%asi, %r24, %r17
679
680 !after IJ_generate
681
682 add %r18, 0, %r18
683 add %r16, 0, %r16
684
685 dec %g2
686 brnz %g2, 1b
687 nop
688
689
690 setx 0x21bd18a0bd596047, %g5, %r17 !64 bit data
691 setx 0x427e151b179c15fa, %g5, %r19 !64 bit data
692 setx 0xee6e25cbcc45ccd3, %g5, %r24 !64 bit data
693
694 setx 0x80900000, %g5, %r18 !40 bit addr
695 setx 0x80900000, %g5, %r16 !40 bit addr
696
697 mov 3, %g2
698
6991:
700 wr %g0, 4, %asi
701
702 !before IJ_generate
703
704myinst_118:
705!note: quad word is 16 bytes, double word is 8 bytes, word is 4 bytes, half word is 2 bytes
706 .word 0xe8948080 ! 13: LDUHA_R lduha [%r18, %r0] 0x04, %r20
707myinst_119:
708 .word 0xe2b48080 ! 1: STHA_R stha %r17, [%r18 + %r0] 0x04
709 setx 0x0000400000, %l0, %l1
710 add %r18, %l1, %r18
711 add %r16, %l1, %r16
712!note: the 2nd store will evict the 1st store to memory
713 .word 0xe2b48080 ! 1: STHA_R stha %r17, [%r18 + %r0] 0x04
714myinst_121:
715 .word 0xe8ec8080 ! 1: LDSTUBA_R ldstuba %r20, [%r18 + %r0] 0x04
716myinst_122:
717 .word 0xc3ec8080 ! 1: PREFETCHA_R prefetcha [%r18, %r0] 0x04, #one_read
718myinst_123:
719 .word 0xe3e4a013 ! 1: CASA_R casa [%r18] %asi, %r19, %r17
720
721 wr %g0, 4, %asi
722
723myinst_124:
724 .word 0xd05c0000 ! 1: LDX_R ldx [%r16 + %r0], %r8
725myinst_125:
726 .word 0xe2f40080 ! 1: STXA_R stxa %r17, [%r16 + %r0] 0x04
727myinst_126:
728 .word 0xe3f42018 ! 1: CASXA_R casxa [%r16]%asi, %r24, %r17
729
730 !after IJ_generate
731
732 add %r18, 32, %r18
733 add %r16, 16, %r16
734
735 dec %g2
736 brnz %g2, 1b
737 nop
738
739
740 setx 0x0db228bd2ce01b3a, %g5, %r17 !64 bit data
741 setx 0x239a4acf0dc723cc, %g5, %r19 !64 bit data
742 setx 0x7dc5b656b82e437c, %g5, %r24 !64 bit data
743
744 setx 0x80f00000, %g5, %r18 !40 bit addr
745 setx 0x80600000, %g5, %r16 !40 bit addr
746
747 mov 1, %g2
748
7491:
750 wr %g0, 4, %asi
751
752 !before IJ_generate
753
754myinst_127:
755!note: quad word is 16 bytes, double word is 8 bytes, word is 4 bytes, half word is 2 bytes
756 .word 0xe8048000 ! 14: LDUW_R lduw [%r18 + %r0], %r20
757myinst_128:
758 .word 0xe2b48080 ! 1: STHA_R stha %r17, [%r18 + %r0] 0x04
759 setx 0x0000400000, %l0, %l1
760 add %r18, %l1, %r18
761 add %r16, %l1, %r16
762!note: the 2nd store will evict the 1st store to memory
763 .word 0xe2ac8080 ! 1: STBA_R stba %r17, [%r18 + %r0] 0x04
764myinst_130:
765 .word 0xe86c8000 ! 1: LDSTUB_R ldstub %r20, [%r18 + %r0]
766myinst_131:
767 .word 0xc36c8000 ! 1: PREFETCH_R prefetch [%r18 + %r0], #one_read
768myinst_132:
769 .word 0xe3e4a013 ! 1: CASA_R casa [%r18] %asi, %r19, %r17
770
771 wr %g0, 4, %asi
772
773myinst_133:
774 .word 0xd05c0000 ! 1: LDX_R ldx [%r16 + %r0], %r8
775myinst_134:
776 .word 0xe2f40080 ! 1: STXA_R stxa %r17, [%r16 + %r0] 0x04
777myinst_135:
778 .word 0xe3f42018 ! 1: CASXA_R casxa [%r16]%asi, %r24, %r17
779
780 !after IJ_generate
781
782 add %r18, 16, %r18
783 add %r16, 0, %r16
784
785 dec %g2
786 brnz %g2, 1b
787 nop
788
789
790 setx 0x0ccd780a0ab0272c, %g5, %r17 !64 bit data
791 setx 0x082387be63b6c69c, %g5, %r19 !64 bit data
792 setx 0x3b29d22752cd1a0c, %g5, %r24 !64 bit data
793
794 setx 0x80200000, %g5, %r18 !40 bit addr
795 setx 0x80f00000, %g5, %r16 !40 bit addr
796
797 mov 3, %g2
798
7991:
800 wr %g0, 4, %asi
801
802 !before IJ_generate
803
804myinst_136:
805!note: quad word is 16 bytes, double word is 8 bytes, word is 4 bytes, half word is 2 bytes
806 .word 0xe8548000 ! 15: LDSH_R ldsh [%r18 + %r0], %r20
807myinst_137:
808 .word 0xe2a48080 ! 1: STWA_R stwa %r17, [%r18 + %r0] 0x04
809 setx 0x0000400000, %l0, %l1
810 add %r18, %l1, %r18
811 add %r16, %l1, %r16
812!note: the 2nd store will evict the 1st store to memory
813 .word 0xe2ac8080 ! 1: STBA_R stba %r17, [%r18 + %r0] 0x04
814myinst_139:
815 .word 0xe8ec8080 ! 1: LDSTUBA_R ldstuba %r20, [%r18 + %r0] 0x04
816myinst_140:
817 .word 0xc36c8000 ! 1: PREFETCH_R prefetch [%r18 + %r0], #one_read
818myinst_141:
819 .word 0xe3e4a013 ! 1: CASA_R casa [%r18] %asi, %r19, %r17
820
821 wr %g0, 4, %asi
822
823myinst_142:
824 .word 0xd0dc0080 ! 1: LDXA_R ldxa [%r16, %r0] 0x04, %r8
825myinst_143:
826 .word 0xe2740000 ! 1: STX_R stx %r17, [%r16 + %r0]
827myinst_144:
828 .word 0xe3f42018 ! 1: CASXA_R casxa [%r16]%asi, %r24, %r17
829
830 !after IJ_generate
831
832 add %r18, 0, %r18
833 add %r16, 32, %r16
834
835 dec %g2
836 brnz %g2, 1b
837 nop
838
839
840 setx 0x735a567d214a2280, %g5, %r17 !64 bit data
841 setx 0x13ede71d58999234, %g5, %r19 !64 bit data
842 setx 0x11630a17dc799b86, %g5, %r24 !64 bit data
843
844 setx 0x80f00000, %g5, %r18 !40 bit addr
845 setx 0x80a00000, %g5, %r16 !40 bit addr
846
847 mov 3, %g2
848
8491:
850 wr %g0, 4, %asi
851
852 !before IJ_generate
853
854myinst_145:
855!note: quad word is 16 bytes, double word is 8 bytes, word is 4 bytes, half word is 2 bytes
856 .word 0xe8048000 ! 16: LDUW_R lduw [%r18 + %r0], %r20
857myinst_146:
858 .word 0xe2a48080 ! 1: STWA_R stwa %r17, [%r18 + %r0] 0x04
859 setx 0x0000400000, %l0, %l1
860 add %r18, %l1, %r18
861 add %r16, %l1, %r16
862!note: the 2nd store will evict the 1st store to memory
863 .word 0xe2b48080 ! 1: STHA_R stha %r17, [%r18 + %r0] 0x04
864myinst_148:
865 .word 0xe8ec8080 ! 1: LDSTUBA_R ldstuba %r20, [%r18 + %r0] 0x04
866myinst_149:
867 .word 0xc3ec8080 ! 1: PREFETCHA_R prefetcha [%r18, %r0] 0x04, #one_read
868myinst_150:
869 .word 0xe3e4a013 ! 1: CASA_R casa [%r18] %asi, %r19, %r17
870
871 wr %g0, 4, %asi
872
873myinst_151:
874 .word 0xd05c0000 ! 1: LDX_R ldx [%r16 + %r0], %r8
875myinst_152:
876 .word 0xe2740000 ! 1: STX_R stx %r17, [%r16 + %r0]
877myinst_153:
878 .word 0xe3f42018 ! 1: CASXA_R casxa [%r16]%asi, %r24, %r17
879
880 !after IJ_generate
881
882 add %r18, 48, %r18
883 add %r16, 48, %r16
884
885 dec %g2
886 brnz %g2, 1b
887 nop
888
889
890 setx 0x9d2c263f62193395, %g5, %r17 !64 bit data
891 setx 0xd5783014eff03f6c, %g5, %r19 !64 bit data
892 setx 0xe56de09b8d030648, %g5, %r24 !64 bit data
893
894 setx 0x80900000, %g5, %r18 !40 bit addr
895 setx 0x80d00000, %g5, %r16 !40 bit addr
896
897 mov 1, %g2
898
8991:
900 wr %g0, 4, %asi
901
902 !before IJ_generate
903
904myinst_154:
905!note: quad word is 16 bytes, double word is 8 bytes, word is 4 bytes, half word is 2 bytes
906 .word 0xe80c8000 ! 17: LDUB_R ldub [%r18 + %r0], %r20
907myinst_155:
908 .word 0xe2248000 ! 1: STW_R stw %r17, [%r18 + %r0]
909 setx 0x0000400000, %l0, %l1
910 add %r18, %l1, %r18
911 add %r16, %l1, %r16
912!note: the 2nd store will evict the 1st store to memory
913 .word 0xe2b48080 ! 1: STHA_R stha %r17, [%r18 + %r0] 0x04
914myinst_157:
915 .word 0xe8ec8080 ! 1: LDSTUBA_R ldstuba %r20, [%r18 + %r0] 0x04
916myinst_158:
917 .word 0xc36c8000 ! 1: PREFETCH_R prefetch [%r18 + %r0], #one_read
918myinst_159:
919 .word 0xe3e4a013 ! 1: CASA_R casa [%r18] %asi, %r19, %r17
920
921 wr %g0, 4, %asi
922
923myinst_160:
924 .word 0xd05c0000 ! 1: LDX_R ldx [%r16 + %r0], %r8
925myinst_161:
926 .word 0xe2740000 ! 1: STX_R stx %r17, [%r16 + %r0]
927myinst_162:
928 .word 0xe3f42018 ! 1: CASXA_R casxa [%r16]%asi, %r24, %r17
929
930 !after IJ_generate
931
932 add %r18, 16, %r18
933 add %r16, 32, %r16
934
935 dec %g2
936 brnz %g2, 1b
937 nop
938
939
940 setx 0x8a72f7309749ef5b, %g5, %r17 !64 bit data
941 setx 0x6c126d4552d06c66, %g5, %r19 !64 bit data
942 setx 0x642698f6a63d09f4, %g5, %r24 !64 bit data
943
944 setx 0x80200000, %g5, %r18 !40 bit addr
945 setx 0x80e00000, %g5, %r16 !40 bit addr
946
947 mov 3, %g2
948
9491:
950 wr %g0, 4, %asi
951
952 !before IJ_generate
953
954myinst_163:
955!note: quad word is 16 bytes, double word is 8 bytes, word is 4 bytes, half word is 2 bytes
956 .word 0xe80c8000 ! 18: LDUB_R ldub [%r18 + %r0], %r20
957myinst_164:
958 .word 0xe2348000 ! 1: STH_R sth %r17, [%r18 + %r0]
959 setx 0x0000400000, %l0, %l1
960 add %r18, %l1, %r18
961 add %r16, %l1, %r16
962!note: the 2nd store will evict the 1st store to memory
963 .word 0xe2348000 ! 1: STH_R sth %r17, [%r18 + %r0]
964myinst_166:
965 .word 0xe86c8000 ! 1: LDSTUB_R ldstub %r20, [%r18 + %r0]
966myinst_167:
967 .word 0xc3ec8080 ! 1: PREFETCHA_R prefetcha [%r18, %r0] 0x04, #one_read
968myinst_168:
969 .word 0xe3e4a013 ! 1: CASA_R casa [%r18] %asi, %r19, %r17
970
971 wr %g0, 4, %asi
972
973myinst_169:
974 .word 0xd05c0000 ! 1: LDX_R ldx [%r16 + %r0], %r8
975myinst_170:
976 .word 0xe2740000 ! 1: STX_R stx %r17, [%r16 + %r0]
977myinst_171:
978 .word 0xe3f42018 ! 1: CASXA_R casxa [%r16]%asi, %r24, %r17
979
980 !after IJ_generate
981
982 add %r18, 32, %r18
983 add %r16, 0, %r16
984
985 dec %g2
986 brnz %g2, 1b
987 nop
988
989
990 setx 0x4ccf64e712e8bd76, %g5, %r17 !64 bit data
991 setx 0x9fd6b27fb1b10f01, %g5, %r19 !64 bit data
992 setx 0x88e1648da3bb9a43, %g5, %r24 !64 bit data
993
994 setx 0x80f00000, %g5, %r18 !40 bit addr
995 setx 0x80600000, %g5, %r16 !40 bit addr
996
997 mov 3, %g2
998
9991:
1000 wr %g0, 4, %asi
1001
1002 !before IJ_generate
1003
1004myinst_172:
1005!note: quad word is 16 bytes, double word is 8 bytes, word is 4 bytes, half word is 2 bytes
1006 .word 0xe8c48080 ! 19: LDSWA_R ldswa [%r18, %r0] 0x04, %r20
1007myinst_173:
1008 .word 0xe2348000 ! 1: STH_R sth %r17, [%r18 + %r0]
1009 setx 0x0000400000, %l0, %l1
1010 add %r18, %l1, %r18
1011 add %r16, %l1, %r16
1012!note: the 2nd store will evict the 1st store to memory
1013 .word 0xe2348000 ! 1: STH_R sth %r17, [%r18 + %r0]
1014myinst_175:
1015 .word 0xe8ec8080 ! 1: LDSTUBA_R ldstuba %r20, [%r18 + %r0] 0x04
1016myinst_176:
1017 .word 0xc36c8000 ! 1: PREFETCH_R prefetch [%r18 + %r0], #one_read
1018myinst_177:
1019 .word 0xe3e4a013 ! 1: CASA_R casa [%r18] %asi, %r19, %r17
1020
1021 wr %g0, 4, %asi
1022
1023myinst_178:
1024 .word 0xd0dc0080 ! 1: LDXA_R ldxa [%r16, %r0] 0x04, %r8
1025myinst_179:
1026 .word 0xe2740000 ! 1: STX_R stx %r17, [%r16 + %r0]
1027myinst_180:
1028 .word 0xe3f42018 ! 1: CASXA_R casxa [%r16]%asi, %r24, %r17
1029
1030 !after IJ_generate
1031
1032 add %r18, 16, %r18
1033 add %r16, 32, %r16
1034
1035 dec %g2
1036 brnz %g2, 1b
1037 nop
1038
1039
1040 setx 0x193b90abdcb4e9c4, %g5, %r17 !64 bit data
1041 setx 0xb38cd8daa8fd2e7d, %g5, %r19 !64 bit data
1042 setx 0xc231c8837827b37a, %g5, %r24 !64 bit data
1043
1044 setx 0x80700000, %g5, %r18 !40 bit addr
1045 setx 0x80f00000, %g5, %r16 !40 bit addr
1046
1047 mov 1, %g2
1048
10491:
1050 wr %g0, 4, %asi
1051
1052 !before IJ_generate
1053
1054myinst_181:
1055!note: quad word is 16 bytes, double word is 8 bytes, word is 4 bytes, half word is 2 bytes
1056 .word 0xe8048000 ! 20: LDUW_R lduw [%r18 + %r0], %r20
1057myinst_182:
1058 .word 0xe2248000 ! 1: STW_R stw %r17, [%r18 + %r0]
1059 setx 0x0000400000, %l0, %l1
1060 add %r18, %l1, %r18
1061 add %r16, %l1, %r16
1062!note: the 2nd store will evict the 1st store to memory
1063 .word 0xe2248000 ! 1: STW_R stw %r17, [%r18 + %r0]
1064myinst_184:
1065 .word 0xe8ec8080 ! 1: LDSTUBA_R ldstuba %r20, [%r18 + %r0] 0x04
1066myinst_185:
1067 .word 0xc36c8000 ! 1: PREFETCH_R prefetch [%r18 + %r0], #one_read
1068myinst_186:
1069 .word 0xe3e4a013 ! 1: CASA_R casa [%r18] %asi, %r19, %r17
1070
1071 wr %g0, 4, %asi
1072
1073myinst_187:
1074 .word 0xd05c0000 ! 1: LDX_R ldx [%r16 + %r0], %r8
1075myinst_188:
1076 .word 0xe2740000 ! 1: STX_R stx %r17, [%r16 + %r0]
1077myinst_189:
1078 .word 0xe3f42018 ! 1: CASXA_R casxa [%r16]%asi, %r24, %r17
1079
1080 !after IJ_generate
1081
1082 add %r18, 48, %r18
1083 add %r16, 32, %r16
1084
1085 dec %g2
1086 brnz %g2, 1b
1087 nop
1088
1089
1090#include "mcu_finish.s"
1091
1092
1093
1094
1095SECTION .MyDATA_0 DATA_VA = 0x0000000080000000
1096attr_data {
1097 Name = .MyDATA_0,
1098 RA = 0x0000000080000000,
1099 PA = ra2pa(0x0000000080000000,0),
1100 part_0_ctx_zero_tsb_config_0,
1101 part_0_ctx_nonzero_tsb_config_0,
1102 TTE_G = 1,
1103 TTE_Context = PCONTEXT,
1104 TTE_V = 1,
1105 TTE_Size = 0,
1106 TTE_NFO = 0,
1107 TTE_IE = 0,
1108 TTE_Soft2 = 0,
1109 TTE_Diag = 0,
1110 TTE_Soft = 0,
1111 TTE_L = 0,
1112 TTE_CP = 1,
1113 TTE_CV = 0,
1114 TTE_E = 0,
1115 TTE_P = 0,
1116 TTE_W = 1
1117}
1118
1119
1120
1121
1122SECTION .MyDATA_1 DATA_VA = 0x0000000080100000
1123attr_data {
1124 Name = .MyDATA_1,
1125 RA = 0x0000000080100000,
1126 PA = ra2pa(0x0000000080100000,0),
1127 part_0_ctx_zero_tsb_config_0,
1128 part_0_ctx_nonzero_tsb_config_0,
1129 TTE_G = 1,
1130 TTE_Context = PCONTEXT,
1131 TTE_V = 1,
1132 TTE_Size = 0,
1133 TTE_NFO = 0,
1134 TTE_IE = 0,
1135 TTE_Soft2 = 0,
1136 TTE_Diag = 0,
1137 TTE_Soft = 0,
1138 TTE_L = 0,
1139 TTE_CP = 1,
1140 TTE_CV = 0,
1141 TTE_E = 0,
1142 TTE_P = 0,
1143 TTE_W = 1
1144}
1145
1146
1147
1148
1149SECTION .MyDATA_2 DATA_VA = 0x0000000080200000
1150attr_data {
1151 Name = .MyDATA_2,
1152 RA = 0x0000000080200000,
1153 PA = ra2pa(0x0000000080200000,0),
1154 part_0_ctx_zero_tsb_config_0,
1155 part_0_ctx_nonzero_tsb_config_0,
1156 TTE_G = 1,
1157 TTE_Context = PCONTEXT,
1158 TTE_V = 1,
1159 TTE_Size = 0,
1160 TTE_NFO = 0,
1161 TTE_IE = 0,
1162 TTE_Soft2 = 0,
1163 TTE_Diag = 0,
1164 TTE_Soft = 0,
1165 TTE_L = 0,
1166 TTE_CP = 1,
1167 TTE_CV = 0,
1168 TTE_E = 0,
1169 TTE_P = 0,
1170 TTE_W = 1
1171}
1172
1173
1174
1175
1176SECTION .MyDATA_3 DATA_VA = 0x0000000080300000
1177attr_data {
1178 Name = .MyDATA_3,
1179 RA = 0x0000000080300000,
1180 PA = ra2pa(0x0000000080300000,0),
1181 part_0_ctx_zero_tsb_config_0,
1182 part_0_ctx_nonzero_tsb_config_0,
1183 TTE_G = 1,
1184 TTE_Context = PCONTEXT,
1185 TTE_V = 1,
1186 TTE_Size = 0,
1187 TTE_NFO = 0,
1188 TTE_IE = 0,
1189 TTE_Soft2 = 0,
1190 TTE_Diag = 0,
1191 TTE_Soft = 0,
1192 TTE_L = 0,
1193 TTE_CP = 1,
1194 TTE_CV = 0,
1195 TTE_E = 0,
1196 TTE_P = 0,
1197 TTE_W = 1
1198}
1199
1200
1201
1202
1203SECTION .MyDATA_4 DATA_VA = 0x0000000080400000
1204attr_data {
1205 Name = .MyDATA_4,
1206 RA = 0x0000000080400000,
1207 PA = ra2pa(0x0000000080400000,0),
1208 part_0_ctx_zero_tsb_config_0,
1209 part_0_ctx_nonzero_tsb_config_0,
1210 TTE_G = 1,
1211 TTE_Context = PCONTEXT,
1212 TTE_V = 1,
1213 TTE_Size = 0,
1214 TTE_NFO = 0,
1215 TTE_IE = 0,
1216 TTE_Soft2 = 0,
1217 TTE_Diag = 0,
1218 TTE_Soft = 0,
1219 TTE_L = 0,
1220 TTE_CP = 1,
1221 TTE_CV = 0,
1222 TTE_E = 0,
1223 TTE_P = 0,
1224 TTE_W = 1
1225}
1226
1227
1228
1229
1230SECTION .MyDATA_5 DATA_VA = 0x0000000080500000
1231attr_data {
1232 Name = .MyDATA_5,
1233 RA = 0x0000000080500000,
1234 PA = ra2pa(0x0000000080500000,0),
1235 part_0_ctx_zero_tsb_config_0,
1236 part_0_ctx_nonzero_tsb_config_0,
1237 TTE_G = 1,
1238 TTE_Context = PCONTEXT,
1239 TTE_V = 1,
1240 TTE_Size = 0,
1241 TTE_NFO = 0,
1242 TTE_IE = 0,
1243 TTE_Soft2 = 0,
1244 TTE_Diag = 0,
1245 TTE_Soft = 0,
1246 TTE_L = 0,
1247 TTE_CP = 1,
1248 TTE_CV = 0,
1249 TTE_E = 0,
1250 TTE_P = 0,
1251 TTE_W = 1
1252}
1253
1254
1255
1256
1257SECTION .MyDATA_6 DATA_VA = 0x0000000080600000
1258attr_data {
1259 Name = .MyDATA_6,
1260 RA = 0x0000000080600000,
1261 PA = ra2pa(0x0000000080600000,0),
1262 part_0_ctx_zero_tsb_config_0,
1263 part_0_ctx_nonzero_tsb_config_0,
1264 TTE_G = 1,
1265 TTE_Context = PCONTEXT,
1266 TTE_V = 1,
1267 TTE_Size = 0,
1268 TTE_NFO = 0,
1269 TTE_IE = 0,
1270 TTE_Soft2 = 0,
1271 TTE_Diag = 0,
1272 TTE_Soft = 0,
1273 TTE_L = 0,
1274 TTE_CP = 1,
1275 TTE_CV = 0,
1276 TTE_E = 0,
1277 TTE_P = 0,
1278 TTE_W = 1
1279}
1280
1281
1282
1283
1284SECTION .MyDATA_7 DATA_VA = 0x0000000080700000
1285attr_data {
1286 Name = .MyDATA_7,
1287 RA = 0x0000000080700000,
1288 PA = ra2pa(0x0000000080700000,0),
1289 part_0_ctx_zero_tsb_config_0,
1290 part_0_ctx_nonzero_tsb_config_0,
1291 TTE_G = 1,
1292 TTE_Context = PCONTEXT,
1293 TTE_V = 1,
1294 TTE_Size = 0,
1295 TTE_NFO = 0,
1296 TTE_IE = 0,
1297 TTE_Soft2 = 0,
1298 TTE_Diag = 0,
1299 TTE_Soft = 0,
1300 TTE_L = 0,
1301 TTE_CP = 1,
1302 TTE_CV = 0,
1303 TTE_E = 0,
1304 TTE_P = 0,
1305 TTE_W = 1
1306}
1307
1308
1309
1310
1311SECTION .MyDATA_8 DATA_VA = 0x0000000080800000
1312attr_data {
1313 Name = .MyDATA_8,
1314 RA = 0x0000000080800000,
1315 PA = ra2pa(0x0000000080800000,0),
1316 part_0_ctx_zero_tsb_config_0,
1317 part_0_ctx_nonzero_tsb_config_0,
1318 TTE_G = 1,
1319 TTE_Context = PCONTEXT,
1320 TTE_V = 1,
1321 TTE_Size = 0,
1322 TTE_NFO = 0,
1323 TTE_IE = 0,
1324 TTE_Soft2 = 0,
1325 TTE_Diag = 0,
1326 TTE_Soft = 0,
1327 TTE_L = 0,
1328 TTE_CP = 1,
1329 TTE_CV = 0,
1330 TTE_E = 0,
1331 TTE_P = 0,
1332 TTE_W = 1
1333}
1334
1335
1336
1337
1338SECTION .MyDATA_9 DATA_VA = 0x0000000080900000
1339attr_data {
1340 Name = .MyDATA_9,
1341 RA = 0x0000000080900000,
1342 PA = ra2pa(0x0000000080900000,0),
1343 part_0_ctx_zero_tsb_config_0,
1344 part_0_ctx_nonzero_tsb_config_0,
1345 TTE_G = 1,
1346 TTE_Context = PCONTEXT,
1347 TTE_V = 1,
1348 TTE_Size = 0,
1349 TTE_NFO = 0,
1350 TTE_IE = 0,
1351 TTE_Soft2 = 0,
1352 TTE_Diag = 0,
1353 TTE_Soft = 0,
1354 TTE_L = 0,
1355 TTE_CP = 1,
1356 TTE_CV = 0,
1357 TTE_E = 0,
1358 TTE_P = 0,
1359 TTE_W = 1
1360}
1361
1362
1363
1364
1365SECTION .MyDATA_10 DATA_VA = 0x0000000080a00000
1366attr_data {
1367 Name = .MyDATA_10,
1368 RA = 0x0000000080a00000,
1369 PA = ra2pa(0x0000000080a00000,0),
1370 part_0_ctx_zero_tsb_config_0,
1371 part_0_ctx_nonzero_tsb_config_0,
1372 TTE_G = 1,
1373 TTE_Context = PCONTEXT,
1374 TTE_V = 1,
1375 TTE_Size = 0,
1376 TTE_NFO = 0,
1377 TTE_IE = 0,
1378 TTE_Soft2 = 0,
1379 TTE_Diag = 0,
1380 TTE_Soft = 0,
1381 TTE_L = 0,
1382 TTE_CP = 1,
1383 TTE_CV = 0,
1384 TTE_E = 0,
1385 TTE_P = 0,
1386 TTE_W = 1
1387}
1388
1389
1390
1391
1392SECTION .MyDATA_11 DATA_VA = 0x0000000080b00000
1393attr_data {
1394 Name = .MyDATA_11,
1395 RA = 0x0000000080b00000,
1396 PA = ra2pa(0x0000000080b00000,0),
1397 part_0_ctx_zero_tsb_config_0,
1398 part_0_ctx_nonzero_tsb_config_0,
1399 TTE_G = 1,
1400 TTE_Context = PCONTEXT,
1401 TTE_V = 1,
1402 TTE_Size = 0,
1403 TTE_NFO = 0,
1404 TTE_IE = 0,
1405 TTE_Soft2 = 0,
1406 TTE_Diag = 0,
1407 TTE_Soft = 0,
1408 TTE_L = 0,
1409 TTE_CP = 1,
1410 TTE_CV = 0,
1411 TTE_E = 0,
1412 TTE_P = 0,
1413 TTE_W = 1
1414}
1415
1416
1417
1418
1419SECTION .MyDATA_12 DATA_VA = 0x0000000080c00000
1420attr_data {
1421 Name = .MyDATA_12,
1422 RA = 0x0000000080c00000,
1423 PA = ra2pa(0x0000000080c00000,0),
1424 part_0_ctx_zero_tsb_config_0,
1425 part_0_ctx_nonzero_tsb_config_0,
1426 TTE_G = 1,
1427 TTE_Context = PCONTEXT,
1428 TTE_V = 1,
1429 TTE_Size = 0,
1430 TTE_NFO = 0,
1431 TTE_IE = 0,
1432 TTE_Soft2 = 0,
1433 TTE_Diag = 0,
1434 TTE_Soft = 0,
1435 TTE_L = 0,
1436 TTE_CP = 1,
1437 TTE_CV = 0,
1438 TTE_E = 0,
1439 TTE_P = 0,
1440 TTE_W = 1
1441}
1442
1443
1444
1445
1446SECTION .MyDATA_13 DATA_VA = 0x0000000080d00000
1447attr_data {
1448 Name = .MyDATA_13,
1449 RA = 0x0000000080d00000,
1450 PA = ra2pa(0x0000000080d00000,0),
1451 part_0_ctx_zero_tsb_config_0,
1452 part_0_ctx_nonzero_tsb_config_0,
1453 TTE_G = 1,
1454 TTE_Context = PCONTEXT,
1455 TTE_V = 1,
1456 TTE_Size = 0,
1457 TTE_NFO = 0,
1458 TTE_IE = 0,
1459 TTE_Soft2 = 0,
1460 TTE_Diag = 0,
1461 TTE_Soft = 0,
1462 TTE_L = 0,
1463 TTE_CP = 1,
1464 TTE_CV = 0,
1465 TTE_E = 0,
1466 TTE_P = 0,
1467 TTE_W = 1
1468}
1469
1470
1471
1472
1473SECTION .MyDATA_14 DATA_VA = 0x0000000080e00000
1474attr_data {
1475 Name = .MyDATA_14,
1476 RA = 0x0000000080e00000,
1477 PA = ra2pa(0x0000000080e00000,0),
1478 part_0_ctx_zero_tsb_config_0,
1479 part_0_ctx_nonzero_tsb_config_0,
1480 TTE_G = 1,
1481 TTE_Context = PCONTEXT,
1482 TTE_V = 1,
1483 TTE_Size = 0,
1484 TTE_NFO = 0,
1485 TTE_IE = 0,
1486 TTE_Soft2 = 0,
1487 TTE_Diag = 0,
1488 TTE_Soft = 0,
1489 TTE_L = 0,
1490 TTE_CP = 1,
1491 TTE_CV = 0,
1492 TTE_E = 0,
1493 TTE_P = 0,
1494 TTE_W = 1
1495}
1496
1497
1498
1499
1500SECTION .MyDATA_15 DATA_VA = 0x0000000080f00000
1501attr_data {
1502 Name = .MyDATA_15,
1503 RA = 0x0000000080f00000,
1504 PA = ra2pa(0x0000000080f00000,0),
1505 part_0_ctx_zero_tsb_config_0,
1506 part_0_ctx_nonzero_tsb_config_0,
1507 TTE_G = 1,
1508 TTE_Context = PCONTEXT,
1509 TTE_V = 1,
1510 TTE_Size = 0,
1511 TTE_NFO = 0,
1512 TTE_IE = 0,
1513 TTE_Soft2 = 0,
1514 TTE_Diag = 0,
1515 TTE_Soft = 0,
1516 TTE_L = 0,
1517 TTE_CP = 1,
1518 TTE_CV = 0,
1519 TTE_E = 0,
1520 TTE_P = 0,
1521 TTE_W = 1
1522}
1523
1524
1525
1526
1527#if 0
1528#endif
Full OpenSPARC design & verification tarball including full HDL.