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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: n2_err_dram_DSC.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define MAIN_PAGE_HV_ALSO | |
39 | ||
40 | #define DRAM_ERR_INJ_REG 0x8400000290 | |
41 | #define DRAM_ERR_STAT_REG 0x8400000280 | |
42 | #define L2_ERR_STAT_REG 0xAB00000000 | |
43 | #define L2_ERR_ADDR_REG 0xAC00000000 | |
44 | ||
45 | #define ERROR_ADDR 0x20200000 | |
46 | ||
47 | ||
48 | #define DRAM_CHANNEL_ADDR 0x2000 | |
49 | #define TEST_DATA1 0x1000100081c3e008 | |
50 | #define L2_ES_W1C_VALUE 0xc03ffff800000000 | |
51 | #define DRAM_ES_W1C_VALUE 0xfe00000000000000 | |
52 | #define DRAM_ESR_REG 0x8400000280 | |
53 | #define DRAM_ERR_INJ_REG 0x8400000290 | |
54 | #define DRAM_SCRB_FREQ_REG 0x8400000018 | |
55 | #define DRAM_SCRB_ENB_REG 0x8400000040 | |
56 | ||
57 | #include "hboot.s" | |
58 | #include "asi_s.h" | |
59 | #include "err_defines.h" | |
60 | ||
61 | ||
62 | ||
63 | .text | |
64 | .global main | |
65 | ||
66 | ||
67 | main: | |
68 | ||
69 | ! Boot code does not provide TLB translation for IO address space | |
70 | ta T_CHANGE_HPRIV | |
71 | ||
72 | setx TEST_DATA1, %l0, %g3 | |
73 | setx DRAM_ES_W1C_VALUE, %l0, %g4 | |
74 | setx DRAM_ESR_REG, %l0, %g5 | |
75 | setx L2ES_PA1, %l0, %g6 | |
76 | ||
77 | clear_DRAM_ESR: | |
78 | ! Clear DRAM Error status register (Bit[63:57] write-1-clear) | |
79 | stx %g4, [%g5] ! %g5 set to ESR Reg | |
80 | ||
81 | disable_L1: | |
82 | ldxa [%g0] ASI_LSU_CONTROL, %l0 | |
83 | ! Remove the lower 2 bits (I-Cache and D-Cache enables) | |
84 | andn %l0, 0x3, %l0 | |
85 | stxa %l0, [%g0] ASI_LSU_CONTROL | |
86 | ||
87 | ||
88 | clear_l2_ESR: | |
89 | ! Write 1 to clear L2 Error status registers | |
90 | setx L2_ES_W1C_VALUE, %l0, %l1 | |
91 | stx %l1, [%g6] | |
92 | nop | |
93 | ||
94 | set_DRAM_error_inject: | |
95 | ! Set up DRAM error injection | |
96 | mov 0x4, %l1 ! ECC Mask (single bit error) | |
97 | mov 0x1, %l2 | |
98 | sllx %l2, DRAM_EI_SSHOT, %l3 | |
99 | or %l1, %l3, %l1 ! Set single shot | |
100 | sllx %l2, DRAM_EI_ENB, %l3 | |
101 | or %l1, %l3, %l1 ! Enable error injection for the next write | |
102 | ||
103 | setx DRAM_ERR_INJ_REG, %l0, %l2 ! DRAM error injection | |
104 | stx %l1, [%l2] | |
105 | membar #Sync | |
106 | ||
107 | set_L2_Directly_Mapped_Mode: | |
108 | setx L2CS_PA0, %l6, %g1 ! Bit 1 in L2 Control Status Register | |
109 | mov 0x2, %l0 | |
110 | stx %l0, [%g1] | |
111 | membar #Sync | |
112 | nop | |
113 | ||
114 | ||
115 | store_to_L2_way0: | |
116 | setx 0x0003000000, %l0, %g2 ! bits [21:18] select way | |
117 | stx %g3, [%g2] | |
118 | stx %g3, [%g2+8] | |
119 | membar #Sync | |
120 | ||
121 | ||
122 | store_to_MCU: | |
123 | setx TEST_DATA1, %l2, %l1 | |
124 | setx 0x0002000000, %l0, %g1 ! bits [21:18] select way | |
125 | stx %l1, [%g1] | |
126 | stx %l1, [%g1+8] | |
127 | membar #Sync | |
128 | ||
129 | read_back_from_MCU: | |
130 | ldx [%g2], %l5 | |
131 | membar #Sync | |
132 | ||
133 | ||
134 | enable_l1: | |
135 | ldxa [%g0] ASI_LSU_CONTROL, %l0 | |
136 | or %l0, 0x3, %l0 | |
137 | stxa %l0, [%g0] ASI_LSU_CONTROL | |
138 | ||
139 | ||
140 | ||
141 | set_DRAM_scrub_frequency: | |
142 | setx DRAM_SCRB_FREQ_REG, %l0, %l1 | |
143 | mov 0x5, %l0 | |
144 | stx %l0, [%l1] | |
145 | membar #Sync | |
146 | ||
147 | enable_DRAM_scrub: | |
148 | setx DRAM_SCRB_ENB_REG, %l0, %l1 | |
149 | mov 0x1, %l0 | |
150 | stx %l0, [%l1] | |
151 | membar #Sync | |
152 | ||
153 | clr %g1 | |
154 | ||
155 | ||
156 | ||
157 | Loop: | |
158 | inc %g1 | |
159 | ! cmp %g1, 5 ! original number | |
160 | cmp %g1, 0x20 | |
161 | be check_DRAM_ESR | |
162 | ! be test_fail | |
163 | nop | |
164 | bne Loop | |
165 | nop | |
166 | ||
167 | check_DRAM_ESR: | |
168 | ldx [%g5], %l0 | |
169 | ||
170 | ||
171 | compute_expected_DRAM_ESR: | |
172 | ! Compute expected value of DRAM error status register | |
173 | mov 0x1, %l6 | |
174 | sllx %l6, DRAM_ES_DSC, %l7 | |
175 | ! Due to DDR design, a single shot for one clock cycle results in errors for two 16-Byte chunks | |
176 | ! This also implies that a disrupting 0x78 trap will follow a 0x32 precise trap | |
177 | sllx %l6, DRAM_ES_MEC, %l5 | |
178 | or %l7, %l5, %l7 | |
179 | ||
180 | ! Not checking syndrome because it varies with environment timing (e.g. different in cmp and ciop) | |
181 | set 0xffff, %l1 | |
182 | andn %l0, %l1, %l0 | |
183 | cmp %l0, %l7 | |
184 | bne %xcc, test_fail | |
185 | nop | |
186 | ||
187 | compute_expected_L2_ESR: | |
188 | ! Compute expected value of L2 error status register | |
189 | mov 0x1, %l1 | |
190 | sllx %l1, L2ES_DSC, %l0 | |
191 | ||
192 | check_l2_ESR: | |
193 | ldx [%g6], %l4 | |
194 | ||
195 | cmp %l4, %l0 | |
196 | bne %xcc, test_fail | |
197 | nop | |
198 | ||
199 | clr_DRAM_ESR: | |
200 | ! Clear DRAM Error status register | |
201 | stx %g4, [%g5] | |
202 | ||
203 | check_err_corrected: | |
204 | ! Check if error is corrected | |
205 | ldx [%g2], %l0 | |
206 | cmp %l0, %g3 | |
207 | bne %xcc, test_fail | |
208 | nop | |
209 | ||
210 | check_DRAM_ESR_again: | |
211 | ! Check DRAM ES again - should be zero | |
212 | ldx [%g5], %l0 | |
213 | brnz %l0, test_fail | |
214 | nop | |
215 | ||
216 | ba test_pass | |
217 | nop | |
218 | ||
219 | /******************************************************* | |
220 | * Exit code | |
221 | *******************************************************/ | |
222 | ||
223 | test_pass: | |
224 | ta T_GOOD_TRAP | |
225 | ||
226 | test_fail: | |
227 | ta T_BAD_TRAP | |
228 | ||
229 |