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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: n2_err_dram_DSC_trap.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap | |
39 | ||
40 | #define MAIN_PAGE_HV_ALSO | |
41 | ||
42 | #define DRAM_ERR_INJ_REG 0x8400000290 | |
43 | #define DRAM_ERR_STAT_REG 0x8400000280 | |
44 | #define L2_ERR_STAT_REG 0xAB00000000 | |
45 | #define L2_ERR_ADDR_REG 0xAC00000000 | |
46 | ||
47 | #define ERROR_ADDR 0x20200000 | |
48 | ||
49 | ||
50 | #define DRAM_CHANNEL_ADDR 0x2000 | |
51 | #define TEST_DATA1 0x1000100081c3e008 | |
52 | #define L2_ES_W1C_VALUE 0xc03ffff800000000 | |
53 | #define DRAM_ES_W1C_VALUE 0xfe00000000000000 | |
54 | #define DRAM_ESR_REG 0x8400000280 | |
55 | #define DRAM_ERR_INJ_REG 0x8400000290 | |
56 | #define DRAM_SCRB_FREQ_REG 0x8400000018 | |
57 | #define DRAM_SCRB_ENB_REG 0x8400000040 | |
58 | ||
59 | #include "hboot.s" | |
60 | #include "asi_s.h" | |
61 | #include "err_defines.h" | |
62 | ||
63 | ||
64 | ||
65 | .text | |
66 | .global main | |
67 | .global My_Corrected_ECC_error_trap | |
68 | ||
69 | ||
70 | ||
71 | main: | |
72 | ||
73 | ! Boot code does not provide TLB translation for IO address space | |
74 | ta T_CHANGE_HPRIV | |
75 | ||
76 | setx TEST_DATA1, %l0, %g3 | |
77 | setx DRAM_ES_W1C_VALUE, %l0, %g4 | |
78 | setx DRAM_ESR_REG, %l0, %g5 | |
79 | setx L2ES_PA1, %l0, %g6 | |
80 | ||
81 | clear_DRAM_ESR: | |
82 | ! Clear DRAM Error status register (Bit[63:57] write-1-clear) | |
83 | stx %g4, [%g5] ! %g5 set to ESR Reg | |
84 | ||
85 | disable_L1: | |
86 | ldxa [%g0] ASI_LSU_CONTROL, %l0 | |
87 | ! Remove the lower 2 bits (I-Cache and D-Cache enables) | |
88 | andn %l0, 0x3, %l0 | |
89 | stxa %l0, [%g0] ASI_LSU_CONTROL | |
90 | ||
91 | enable_err_reporting: | |
92 | setx L2EE_PA0, %l0, %l1 | |
93 | ldx [%l1], %l2 | |
94 | mov 0x1, %l0 | |
95 | or %l2, %l0, %l2 | |
96 | stx %l2, [%l1] | |
97 | ||
98 | ||
99 | clear_l2_ESR: | |
100 | ! Write 1 to clear L2 Error status registers | |
101 | setx L2_ES_W1C_VALUE, %l0, %l1 | |
102 | stx %l1, [%g6] | |
103 | nop | |
104 | ||
105 | set_DRAM_error_inject: | |
106 | ! Set up DRAM error injection | |
107 | mov 0x4, %l1 ! ECC Mask (single bit error) | |
108 | mov 0x1, %l2 | |
109 | sllx %l2, DRAM_EI_SSHOT, %l3 | |
110 | or %l1, %l3, %l1 ! Set single shot | |
111 | sllx %l2, DRAM_EI_ENB, %l3 | |
112 | or %l1, %l3, %l1 ! Enable error injection for the next write | |
113 | ||
114 | setx DRAM_ERR_INJ_REG, %l0, %l2 ! DRAM error injection | |
115 | stx %l1, [%l2] | |
116 | ||
117 | set_L2_Directly_Mapped_Mode: | |
118 | setx L2CS_PA0, %l6, %g1 ! Bit 1 in L2 Control Status Register | |
119 | mov 0x2, %l0 | |
120 | stx %l0, [%g1] | |
121 | nop | |
122 | ||
123 | ||
124 | store_to_L2_way0: | |
125 | setx 0x0003000000, %l0, %g2 ! bits [21:18] select way | |
126 | stx %g3, [%g2] | |
127 | stx %g3, [%g2+8] | |
128 | ||
129 | ||
130 | store_to_DRAM: | |
131 | setx TEST_DATA1, %l2, %l1 | |
132 | setx 0x0002000000, %l0, %g2 ! bits [21:18] select way | |
133 | stx %l1, [%g2] | |
134 | stx %l1, [%g2+8] | |
135 | ||
136 | ||
137 | ||
138 | enable_l1: | |
139 | ldxa [%g0] ASI_LSU_CONTROL, %l0 | |
140 | or %l0, 0x3, %l0 | |
141 | stxa %l0, [%g0] ASI_LSU_CONTROL | |
142 | ||
143 | set_DRAM_scrub_frequency: | |
144 | setx DRAM_SCRB_FREQ_REG, %l0, %l1 | |
145 | mov 0x5, %l0 | |
146 | stx %l0, [%l1] | |
147 | ||
148 | enable_DRAM_scrub: | |
149 | setx DRAM_SCRB_ENB_REG, %l0, %l1 | |
150 | mov 0x1, %l0 | |
151 | stx %l0, [%l1] | |
152 | ||
153 | clr %g1 | |
154 | ||
155 | ||
156 | ||
157 | Loop: | |
158 | inc %g1 | |
159 | ! cmp %g1, 5 ! original number | |
160 | cmp %g1, 0x20 | |
161 | bne Loop | |
162 | ! be test_fail | |
163 | nop | |
164 | ||
165 | be check_DRAM_ESR | |
166 | nop | |
167 | ||
168 | check_DRAM_ESR: | |
169 | ldx [%g5], %l0 | |
170 | ||
171 | ||
172 | compute_expected_DRAM_ESR: | |
173 | ! Compute expected value of DRAM error status register | |
174 | mov 0x1, %l6 | |
175 | sllx %l6, DRAM_ES_DSC, %l7 | |
176 | ! Due to DDR design, a single shot for one clock cycle results in errors for two 16-Byte chunks | |
177 | ! This also implies that a disrupting 0x78 trap will follow a 0x32 precise trap | |
178 | sllx %l6, DRAM_ES_MEC, %l5 | |
179 | or %l7, %l5, %l7 | |
180 | ||
181 | ! Not checking syndrome because it varies with environment timing (e.g. different in cmp and ciop) | |
182 | set 0xffff, %l1 | |
183 | andn %l0, %l1, %l0 | |
184 | cmp %l0, %l7 | |
185 | bne %xcc, test_fail | |
186 | nop | |
187 | ||
188 | compute_expected_L2_ESR: | |
189 | ! Compute expected value of L2 error status register | |
190 | mov 0x1, %l1 | |
191 | sllx %l1, L2ES_DSC, %l0 | |
192 | ||
193 | check_l2_ESR: | |
194 | ldx [%g6], %l4 | |
195 | ||
196 | cmp %l4, %l0 | |
197 | bne %xcc, test_fail | |
198 | nop | |
199 | ||
200 | clr_DRAM_ESR: | |
201 | ! Clear DRAM Error status register | |
202 | stx %g4, [%g5] | |
203 | ||
204 | check_err_corrected: | |
205 | ! Check if error is corrected | |
206 | ldx [%g2], %l0 | |
207 | cmp %l0, %g3 | |
208 | bne %xcc, test_fail | |
209 | nop | |
210 | ||
211 | check_DRAM_ESR_again: | |
212 | ! Check DRAM ES again - should be zero | |
213 | ldx [%g5], %l0 | |
214 | brnz %l0, test_fail | |
215 | nop | |
216 | ||
217 | ! Check if a Corrected ECC Trap happened | |
218 | check_error_trap: | |
219 | setx EXECUTED, %l1, %l0 | |
220 | cmp %o0, %l0 | |
221 | bne test_fail | |
222 | nop | |
223 | mov TT_Corrected_ECC, %l0 | |
224 | cmp %o1, %l0 | |
225 | bne test_fail | |
226 | nop | |
227 | ||
228 | ba test_pass | |
229 | nop | |
230 | ||
231 | My_Corrected_ECC_error_trap: | |
232 | ! Signal trap taken | |
233 | setx EXECUTED, %l0, %o0 | |
234 | ! save trap type value | |
235 | rdpr %tt, %o1 | |
236 | retry | |
237 | nop | |
238 | ||
239 | ||
240 | /******************************************************* | |
241 | * Exit code | |
242 | *******************************************************/ | |
243 | ||
244 | test_pass: | |
245 | ta T_GOOD_TRAP | |
246 | ||
247 | test_fail: | |
248 | ta T_BAD_TRAP | |
249 | ||
250 |