[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / mcu / n2_err_dram_DSU_trap.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: n2_err_dram_DSU_trap.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define H_HT0_Sw_Recoverable_Error_0x40  My_Recoverable_Sw_error_trap


#define MAIN_PAGE_HV_ALSO

#define	 DRAM_ERR_INJ_REG   0x8400000290
#define	 DRAM_ERR_STAT_REG  0x8400000280
#define	 L2_ERR_STAT_REG    0xAB00000000
#define	 L2_ERR_ADDR_REG    0xAC00000000

#define	 ERROR_ADDR	    0x20200000


#define  DRAM_CHANNEL_ADDR    0x2000
#define  TEST_DATA1            0x1000100081c3e008
#define  L2_ES_W1C_VALUE      0xc03ffff800000000
#define  DRAM_ES_W1C_VALUE    0xfe00000000000000
#define  DRAM_ESR_REG         0x8400000280
#define  DRAM_ERR_INJ_REG     0x8400000290
#define  DRAM_SCRB_FREQ_REG   0x8400000018
#define  DRAM_SCRB_ENB_REG    0x8400000040
#define  TT_SW_Error        0x40


#include "hboot.s"
#include "asi_s.h"
#include "err_defines.h"


.text
.global	 main
.global  My_Recoverable_Sw_error_trap


main:

  ! Boot code does not provide TLB translation for IO address space
  ta	T_CHANGE_HPRIV

  setx	TEST_DATA1, %l0, %g3
  setx	DRAM_ES_W1C_VALUE, %l0, %g4
  setx	DRAM_ESR_REG, %l0, %g5
  setx	L2ES_PA1, %l0, %g6

clear_DRAM_ESR:
  ! Clear DRAM Error status register (Bit[63:57] write-1-clear)
  stx	%g4, [%g5]            ! %g5 set to ESR Reg

disable_L1:
  ldxa	[%g0] ASI_LSU_CONTROL, %l0
  ! Remove the lower 2 bits (I-Cache and D-Cache enables)
  andn	%l0, 0x3, %l0
  stxa	%l0, [%g0] ASI_LSU_CONTROL

enable_err_reporting:
  setx L2EE_PA0, %l0, %l1
  ldx  [%l1], %l2
  mov  0x1, %l0
  or   %l2, %l0, %l2
  stx  %l2, [%l1]


clear_l2_ESR:
  ! Write 1 to clear L2 Error status registers
  setx	L2_ES_W1C_VALUE, %l0, %l1
  stx	%l1, [%g6]
  nop

set_DRAM_error_inject:
  ! Set up DRAM error injection
  mov	0x3, %l1		! ECC Mask (two bit error)
  mov	0x1, %l2
  sllx	%l2, DRAM_EI_SSHOT, %l3
  or	%l1, %l3, %l1		! Set single shot
  sllx	%l2, DRAM_EI_ENB, %l3
  or	%l1, %l3, %l1		! Enable error injection for the next write

  setx  DRAM_ERR_INJ_REG, %l0, %l2    ! DRAM error injection
  stx	%l1, [%l2]

set_L2_Directly_Mapped_Mode:
  setx  L2CS_PA0, %l6, %g1      ! Bit 1 in L2 Control Status Register
  mov   0x2, %l0
  stx   %l0, [%g1]
  nop

 
store_to_L2_way0:
  setx  0x0003000000, %l0, %g2  ! bits [21:18] select way
  stx %g3, [%g2]
  stx %g3, [%g2+8]


store_to_DRAM:
  setx	TEST_DATA1, %l2, %l1
  setx  0x0002000000, %l0, %g2  ! bits [21:18] select way
  stx	%l1, [%g2]
  stx   %l1, [%g2+8]


enable_l1:
  ldxa	[%g0] ASI_LSU_CONTROL, %l0
  or	%l0, 0x3, %l0
  stxa	%l0, [%g0] ASI_LSU_CONTROL

set_DRAM_scrub_frequency:
  setx	DRAM_SCRB_FREQ_REG, %l0, %l1
  mov	0x5, %l0
  stx	%l0, [%l1]

enable_DRAM_scrub:
  setx	DRAM_SCRB_ENB_REG, %l0, %l1
  mov	0x1, %l0
  stx	%l0, [%l1]

  clr	%g1


Loop:
  inc	%g1
 ! cmp	%g1, 5  ! original number
  cmp	%g1, 0x20
  be	check_DRAM_ESR
!  be	test_fail
  nop

  bne	Loop
  nop

check_DRAM_ESR:
  ldx	[%g5], %l0


compute_expected_DRAM_ESR:
  ! Compute expected value of DRAM error status register
  mov	0x1, %l6
  sllx	%l6, DRAM_ES_DSU, %l7
  ! Due to DDR design, a single shot for one clock cycle results in errors for two 16-Byte chunks
  ! This also implies that a disrupting 0x78 trap will follow a 0x32 precise trap
  sllx	%l6, DRAM_ES_MEU, %l5
  or	%l7, %l5, %l7

  ! Not checking syndrome because it varies with environment timing (e.g. different in cmp and ciop)
  set	0xffff, %l1
  andn	%l0, %l1, %l0

verify:
  cmp	%l0, %l7
  bne	%xcc, test_fail
  nop

compute_expected_L2_ESR:
  ! Compute expected value of L2 error status register
  mov	0x1, %l1
  sllx	%l1, L2ES_DSU, %l0

check_l2_ESR:
  ldx	[%g6], %l4

  cmp	%l4, %l0
  bne	%xcc, test_fail
  nop

clr_DRAM_ESR:
  ! Clear DRAM Error status register
  stx	%g4, [%g5]

check_err_corrected:
  ! Check if error is corrected
  ldx	[%g2], %l0
  cmp	%l0, %g3
  bne	%xcc, test_fail
  nop

check_DRAM_ESR_again:
  ! Check DRAM ES again - should be zero
  ldx	[%g5], %l0
  brnz	%l0, test_fail
  nop

check_sw_err_trap:
  ! Check if a Software Recoverable Error Trap happened
  set   EXECUTED, %l0
  cmp   %o0, %l0
  bne   test_fail
  nop
  mov   TT_SW_Error, %l0
  cmp   %o1, %l0
  bne   test_fail
  nop


My_Recoverable_Sw_error_trap:
  ! Signal trap taken
  setx  EXECUTED, %l0, %o0
  ! save trap type value
  rdpr  %tt, %o1
  retry
  nop


/*******************************************************
 * Exit code
 *******************************************************/

test_pass:
ta  T_GOOD_TRAP

test_fail:
ta  T_BAD_TRAP
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: n2_err_dram_DSU_trap.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
	39
	40
	41	#define MAIN_PAGE_HV_ALSO
	42
	43	#define DRAM_ERR_INJ_REG 0x8400000290
	44	#define DRAM_ERR_STAT_REG 0x8400000280
	45	#define L2_ERR_STAT_REG 0xAB00000000
	46	#define L2_ERR_ADDR_REG 0xAC00000000
	47
	48	#define ERROR_ADDR 0x20200000
	49
	50
	51	#define DRAM_CHANNEL_ADDR 0x2000
	52	#define TEST_DATA1 0x1000100081c3e008
	53	#define L2_ES_W1C_VALUE 0xc03ffff800000000
	54	#define DRAM_ES_W1C_VALUE 0xfe00000000000000
	55	#define DRAM_ESR_REG 0x8400000280
	56	#define DRAM_ERR_INJ_REG 0x8400000290
	57	#define DRAM_SCRB_FREQ_REG 0x8400000018
	58	#define DRAM_SCRB_ENB_REG 0x8400000040
	59	#define TT_SW_Error 0x40
	60
	61
	62	#include "hboot.s"
	63	#include "asi_s.h"
	64	#include "err_defines.h"
65
66
67
68	.text
69	.global main
70	.global My_Recoverable_Sw_error_trap
71
72
73
74	main:
75
76	! Boot code does not provide TLB translation for IO address space
77	ta T_CHANGE_HPRIV
78
79	setx TEST_DATA1, %l0, %g3
80	setx DRAM_ES_W1C_VALUE, %l0, %g4
81	setx DRAM_ESR_REG, %l0, %g5
82	setx L2ES_PA1, %l0, %g6
83
84	clear_DRAM_ESR:
85	! Clear DRAM Error status register (Bit[63:57] write-1-clear)
86	stx %g4, [%g5] ! %g5 set to ESR Reg
87
88	disable_L1:
89	ldxa [%g0] ASI_LSU_CONTROL, %l0
90	! Remove the lower 2 bits (I-Cache and D-Cache enables)
91	andn %l0, 0x3, %l0
92	stxa %l0, [%g0] ASI_LSU_CONTROL
93
94	enable_err_reporting:
95	setx L2EE_PA0, %l0, %l1
96	ldx [%l1], %l2
97	mov 0x1, %l0
98	or %l2, %l0, %l2
99	stx %l2, [%l1]
100
101
102	clear_l2_ESR:
103	! Write 1 to clear L2 Error status registers
104	setx L2_ES_W1C_VALUE, %l0, %l1
105	stx %l1, [%g6]
106	nop
107
108	set_DRAM_error_inject:
109	! Set up DRAM error injection
110	mov 0x3, %l1 ! ECC Mask (two bit error)
111	mov 0x1, %l2
112	sllx %l2, DRAM_EI_SSHOT, %l3
113	or %l1, %l3, %l1 ! Set single shot
114	sllx %l2, DRAM_EI_ENB, %l3
115	or %l1, %l3, %l1 ! Enable error injection for the next write
116
117	setx DRAM_ERR_INJ_REG, %l0, %l2 ! DRAM error injection
118	stx %l1, [%l2]
119
120	set_L2_Directly_Mapped_Mode:
121	setx L2CS_PA0, %l6, %g1 ! Bit 1 in L2 Control Status Register
122	mov 0x2, %l0
123	stx %l0, [%g1]
124	nop
125
126
127	store_to_L2_way0:
128	setx 0x0003000000, %l0, %g2 ! bits [21:18] select way
129	stx %g3, [%g2]
130	stx %g3, [%g2+8]
131
132
133	store_to_DRAM:
134	setx TEST_DATA1, %l2, %l1
135	setx 0x0002000000, %l0, %g2 ! bits [21:18] select way
136	stx %l1, [%g2]
137	stx %l1, [%g2+8]
138
139
140
141	enable_l1:
142	ldxa [%g0] ASI_LSU_CONTROL, %l0
143	or %l0, 0x3, %l0
144	stxa %l0, [%g0] ASI_LSU_CONTROL
145
146	set_DRAM_scrub_frequency:
147	setx DRAM_SCRB_FREQ_REG, %l0, %l1
148	mov 0x5, %l0
149	stx %l0, [%l1]
150
151	enable_DRAM_scrub:
152	setx DRAM_SCRB_ENB_REG, %l0, %l1
153	mov 0x1, %l0
154	stx %l0, [%l1]
155
156	clr %g1
157
158
159
160	Loop:
161	inc %g1
162	! cmp %g1, 5 ! original number
163	cmp %g1, 0x20
164	be check_DRAM_ESR
165	! be test_fail
166	nop
167
168	bne Loop
169	nop
170
171	check_DRAM_ESR:
172	ldx [%g5], %l0
173
174
175	compute_expected_DRAM_ESR:
176	! Compute expected value of DRAM error status register
177	mov 0x1, %l6
178	sllx %l6, DRAM_ES_DSU, %l7
179	! Due to DDR design, a single shot for one clock cycle results in errors for two 16-Byte chunks
180	! This also implies that a disrupting 0x78 trap will follow a 0x32 precise trap
181	sllx %l6, DRAM_ES_MEU, %l5
182	or %l7, %l5, %l7
183
184	! Not checking syndrome because it varies with environment timing (e.g. different in cmp and ciop)
185	set 0xffff, %l1
186	andn %l0, %l1, %l0
187
188	verify:
189	cmp %l0, %l7
190	bne %xcc, test_fail
191	nop
192
193	compute_expected_L2_ESR:
194	! Compute expected value of L2 error status register
195	mov 0x1, %l1
196	sllx %l1, L2ES_DSU, %l0
197
198	check_l2_ESR:
199	ldx [%g6], %l4
200
201	cmp %l4, %l0
202	bne %xcc, test_fail
203	nop
204
205	clr_DRAM_ESR:
206	! Clear DRAM Error status register
207	stx %g4, [%g5]
208
209	check_err_corrected:
210	! Check if error is corrected
211	ldx [%g2], %l0
212	cmp %l0, %g3
213	bne %xcc, test_fail
214	nop
215
216	check_DRAM_ESR_again:
217	! Check DRAM ES again - should be zero
218	ldx [%g5], %l0
219	brnz %l0, test_fail
220	nop
221
222	check_sw_err_trap:
223	! Check if a Software Recoverable Error Trap happened
224	set EXECUTED, %l0
225	cmp %o0, %l0
226	bne test_fail
227	nop
228	mov TT_SW_Error, %l0
229	cmp %o1, %l0
230	bne test_fail
231	nop
232
233
234	My_Recoverable_Sw_error_trap:
235	! Signal trap taken
236	setx EXECUTED, %l0, %o0
237	! save trap type value
238	rdpr %tt, %o1
239	retry
240	nop
241
242
243
244	/*******************************************************
245	* Exit code
246	*******************************************************/
247
248	test_pass:
249	ta T_GOOD_TRAP
250
251	test_fail:
252	ta T_BAD_TRAP
253
254