Commit | Line | Data |
---|---|---|
86530b38 AT |
1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: n2_err_dram_afe_NoMemOp.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap | |
39 | #define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap | |
40 | ||
41 | #define MAIN_PAGE_NUCLEUS_ALSO | |
42 | #define MAIN_PAGE_HV_ALSO | |
43 | ||
44 | ||
45 | #include "hboot.s" | |
46 | #include "asi_s.h" | |
47 | ||
48 | #define L20 0x0020134000 | |
49 | #define L21 0x0000134040 | |
50 | ||
51 | #define L22 0x0000134080 | |
52 | #define L23 0x00001340c0 | |
53 | ||
54 | #define L24 0x0000134100 | |
55 | #define L25 0x0000134140 | |
56 | ||
57 | #define L26 0x0000134180 | |
58 | #define L27 0x00001341c0 | |
59 | ||
60 | #define MCU_CNT 31 | |
61 | #define ERR_TYPE 0x1 | |
62 | ||
63 | ||
64 | #ifdef MCU0 | |
65 | #define DRAM_FBR_CNT_REG_PA DRAM_FBR_CNT_REG_PA_0 | |
66 | #define DRAM_ERR_CNT_REG_PA DRAM_ERR_CNT_REG_PA_0 | |
67 | ||
68 | #define DRAM_FBD_ERR_SYND_REG_PA DRAM_FBD_ERR_SYND_REG_PA_0 | |
69 | #define DRAM_FBD_INJ_ERR_SRC_REG_PA DRAM_FBD_INJ_ERR_SRC_REG_PA_0 | |
70 | ||
71 | #define DRAM_ERR_INJ_REG 0x8400000290 | |
72 | #define DRAM_ERR_STAT_REG 0x8400000280 | |
73 | #define L2_ERR_STAT_REG 0xAB00000000 | |
74 | #define L2_ERR_ADDR_REG 0xAC00000000 | |
75 | #endif | |
76 | ||
77 | #ifdef MCU1 | |
78 | #define DRAM_FBR_CNT_REG_PA DRAM_FBR_CNT_REG_PA_1 | |
79 | #define DRAM_ERR_CNT_REG_PA DRAM_ERR_CNT_REG_PA_1 | |
80 | ||
81 | #define DRAM_FBD_ERR_SYND_REG_PA DRAM_FBD_ERR_SYND_REG_PA_1 | |
82 | #define DRAM_FBD_INJ_ERR_SRC_REG_PA DRAM_FBD_INJ_ERR_SRC_REG_PA_1 | |
83 | ||
84 | #define DRAM_ERR_INJ_REG 0x8400001290 | |
85 | #define DRAM_ERR_STAT_REG 0x8400001280 | |
86 | #define L2_ERR_STAT_REG 0xAB00000080 | |
87 | #define L2_ERR_ADDR_REG 0xAC00000080 | |
88 | #endif | |
89 | ||
90 | #ifdef MCU2 | |
91 | #define DRAM_FBR_CNT_REG_PA DRAM_FBR_CNT_REG_PA_2 | |
92 | #define DRAM_ERR_CNT_REG_PA DRAM_ERR_CNT_REG_PA_2 | |
93 | ||
94 | #define DRAM_FBD_ERR_SYND_REG_PA DRAM_FBD_ERR_SYND_REG_PA_2 | |
95 | #define DRAM_FBD_INJ_ERR_SRC_REG_PA DRAM_FBD_INJ_ERR_SRC_REG_PA_2 | |
96 | ||
97 | #define DRAM_ERR_INJ_REG 0x8400002290 | |
98 | #define DRAM_ERR_STAT_REG 0x8400002280 | |
99 | #define L2_ERR_STAT_REG 0xAB00000100 | |
100 | #define L2_ERR_ADDR_REG 0xAC00000100 | |
101 | #endif | |
102 | ||
103 | #ifdef MCU3 | |
104 | #define DRAM_FBR_CNT_REG_PA DRAM_FBR_CNT_REG_PA_3 | |
105 | #define DRAM_ERR_CNT_REG_PA DRAM_ERR_CNT_REG_PA_3 | |
106 | ||
107 | #define DRAM_FBD_ERR_SYND_REG_PA DRAM_FBD_ERR_SYND_REG_PA_3 | |
108 | #define DRAM_FBD_INJ_ERR_SRC_REG_PA DRAM_FBD_INJ_ERR_SRC_REG_PA_3 | |
109 | ||
110 | ||
111 | #define DRAM_ERR_INJ_REG 0x8400003290 | |
112 | #define DRAM_ERR_STAT_REG 0x8400003280 | |
113 | #define L2_ERR_STAT_REG 0xAB00000180 | |
114 | #define L2_ERR_ADDR_REG 0xAC00000180 | |
115 | #endif | |
116 | ||
117 | #define CMP_ECC_CNT 0x1 | |
118 | ||
119 | #ifdef L2_OFF | |
120 | #define L2_ON_OFF_DM 0x1 | |
121 | #else | |
122 | #define L2_ON_OFF_DM 0x0 | |
123 | #endif | |
124 | ||
125 | #define TT 0x63 | |
126 | ||
127 | .text | |
128 | .global main | |
129 | .global My_Corrected_ECC_error_trap | |
130 | .global My_Recoverable_Sw_error_trap | |
131 | ||
132 | ||
133 | main: | |
134 | ta T_CHANGE_HPRIV | |
135 | clr %i6 | |
136 | clr %i7 | |
137 | clr %i2 | |
138 | clr %i0 | |
139 | enable_err_reporting: | |
140 | setx L2EE_PA0, %l0, %l1 | |
141 | ||
142 | ldx [%l1], %l2 | |
143 | mov 0x3, %l0 | |
144 | or %l2, %l0, %l2 | |
145 | ! stx %l2, [%l1] | |
146 | ||
147 | ||
148 | write_mcu_fbr_count_reg: | |
149 | set 0x10000, %g6 !<16>=countone=1 | |
150 | setx DRAM_FBR_CNT_REG_PA, %l7, %o2 | |
151 | stx %g6, [%o2] | |
152 | ldx [%o2], %i1 | |
153 | ||
154 | set_error_count_reg: | |
155 | set 0x1, %g6 !<16>=countone=1 | |
156 | setx DRAM_ERR_CNT_REG_PA, %l7, %o2 | |
157 | stx %g6, [%o2] | |
158 | ||
159 | clear_soc_esr: | |
160 | setx SOC_ESR_REG, %l7, %g5 | |
161 | stx %g0, [%g5] | |
162 | ||
163 | clear_soc_per: | |
164 | setx SOC_PER_REG, %l7, %g5 | |
165 | stx %g0, [%g5] | |
166 | ||
167 | clear_mcu_esr: | |
168 | setx DRAM_ERR_STAT_REG, %l7, %g5 | |
169 | stx %g0, [%g5] | |
170 | ||
171 | clear_l2_esr: | |
172 | setx L2_ERR_STAT_REG, %l7, %g5 | |
173 | stx %g0, [%g5] | |
174 | ||
175 | clear_l2_ear: | |
176 | setx L2_ERR_ADDR_REG, %l7, %g5 | |
177 | stx %g0, [%g5] | |
178 | ||
179 | set_inj_err_src_reg: | |
180 | set ERR_TYPE, %g1 | |
181 | setx DRAM_FBD_INJ_ERR_SRC_REG_PA, %l7, %g3 | |
182 | stx %g1, [%g3] | |
183 | membar 0x40 | |
184 | ||
185 | set_ejr: | |
186 | set 0x1, %g1 | |
187 | sllx %g1, MCU_CNT, %g2 | |
188 | setx SOC_EJR_REG, %l7, %g3 | |
189 | stx %g2, [%g3] | |
190 | membar 0x40 | |
191 | ||
192 | set_eie: | |
193 | setx SOC_EIE_REG, %l7, %g3 | |
194 | stx %g2, [%g3] | |
195 | membar 0x40 | |
196 | ||
197 | set 0xff,%g4 | |
198 | clr %g2 | |
199 | delay_loop: | |
200 | inc %g2 | |
201 | cmp %g2,%g4 | |
202 | bne delay_loop | |
203 | nop | |
204 | ||
205 | check_error_trap: | |
206 | setx EXECUTED, %l1, %l0 | |
207 | cmp %i2, %l0 | |
208 | bne test_fail | |
209 | nop | |
210 | ||
211 | mov TT, %l0 | |
212 | cmp %i0, %l0 | |
213 | bne test_fail | |
214 | nop | |
215 | ||
216 | /****************************************************** | |
217 | * Exit code | |
218 | *******************************************************/ | |
219 | ||
220 | test_pass: | |
221 | EXIT_GOOD | |
222 | ||
223 | test_fail: | |
224 | EXIT_BAD | |
225 | ||
226 | ||
227 | ||
228 | ||
229 | /************************************************************************ | |
230 | Trap Handlers | |
231 | ************************************************************************/ | |
232 | My_Recoverable_Sw_error_trap: | |
233 | nop | |
234 | ba test_fail | |
235 | nop | |
236 | ||
237 | !PER not cleared at the end of the TRAP Handler to avoid further Trap | |
238 | My_Corrected_ECC_error_trap: | |
239 | ! Signal trap taken | |
240 | setx EXECUTED, %l0, %i2 | |
241 | ! save trap type value | |
242 | rdpr %tt, %i0 | |
243 | ||
244 | inc %i7 | |
245 | ||
246 | clear_ejr_tt63: | |
247 | setx SOC_EJR_REG, %l7, %l0 | |
248 | stx %g0, [%l0] | |
249 | nop | |
250 | ||
251 | check_desr_tt63: | |
252 | ldxa [%g0]0x4c, %g2 | |
253 | nop | |
254 | setx 0x8b00000000000000, %l0, %g3 | |
255 | subcc %g2, %g3, %g4 | |
256 | brnz %g4, test_fail | |
257 | nop | |
258 | ||
259 | check_per_tt63: | |
260 | setx SOC_PER_REG, %l7, %g5 | |
261 | ldx [%g5], %i1 | |
262 | nop | |
263 | setx 0x8000000000000000, %l7, %g7 !valid bit | |
264 | set 0x1, %g1 | |
265 | sllx %g1, ERR_FIELD, %g2 | |
266 | or %g7, %g2, %i3 | |
267 | subcc %i1, %i3, %i4 | |
268 | brnz %i4, test_fail | |
269 | nop | |
270 | ||
271 | check_mcu_ESR_tt63: | |
272 | mov 0x1, %l1 | |
273 | sllx %l1, DRAM_ES_FBR, %l6 | |
274 | ||
275 | setx DRAM_ERR_STAT_REG, %l3, %g5 | |
276 | ldx [%g5], %l1 | |
277 | ||
278 | setx 0xbfffffffffff0000, %l3, %l0 ! MEC bit not checked | |
279 | andcc %l0, %l1, %l5 | |
280 | ||
281 | sub %l5, %l6, %i4 | |
282 | brnz %i4, test_fail | |
283 | nop | |
284 | ||
285 | ||
286 | check_mcu_EAR_tt63: | |
287 | setx DRAM_ERR_ADDR_REG_PA_0, %l3, %g5 | |
288 | ldx [%g5], %l1 | |
289 | ||
290 | ||
291 | /* | |
292 | ! Setting DSC and/ or DSU does not cause any logging of the error | |
293 | ! address or syndrome in the L2 Error Address register. | |
294 | ! It also does not update the VEC/VEU/MEC/MEU bits */ | |
295 | check_L2_ESR_tt63: | |
296 | setx L2_ERR_STAT_REG, %l3, %g5 | |
297 | ldx [%g5], %l6 | |
298 | ||
299 | setx 0xbffffffff0000000, %l3, %l0 | |
300 | andcc %l0, %l6, %l5 ! Donot check L2ESR SYND bits and MEC | |
301 | ||
302 | mov 0x1, %l1 | |
303 | sllx %l1, L2ES_DSC, %l0 | |
304 | ||
305 | cmp %l5, %l0 | |
306 | bne %xcc, test_fail | |
307 | nop | |
308 | ||
309 | check_fbr_cnt_reg_tt63: | |
310 | setx DRAM_FBR_CNT_REG_PA, %l7, %o2 | |
311 | ldx [%o2], %g1 | |
312 | set 0x10000, %g6 !<16>=countone=1 | |
313 | sub %g1, %g6, %i4 | |
314 | brnz %i4, test_fail | |
315 | nop | |
316 | ||
317 | read_err_cnt_reg_tt63: | |
318 | setx DRAM_ERR_CNT_REG_PA, %l7, %o2 | |
319 | ldx [%o2], %g1 | |
320 | set CMP_ECC_CNT, %i1 | |
321 | sub %g1, %i1, %i4 | |
322 | brnz %i4, test_fail | |
323 | nop | |
324 | ||
325 | read_fbd_err_synd_reg_tt63: | |
326 | setx DRAM_FBD_ERR_SYND_REG_PA, %l7, %o2 | |
327 | ldx [%o2], %g1 | |
328 | ||
329 | setx 0x8000000000000000, %l7, %o3 | |
330 | set 0x1, %o4 | |
331 | sll %o4, FBSYND, %o5 | |
332 | or %o3, %o5, %g2 | |
333 | ||
334 | and %g1, %g2, %g3 | |
335 | subcc %g2, %g3, %g4 | |
336 | brnz %g4, test_fail | |
337 | nop | |
338 | ||
339 | clear_per_tt63: | |
340 | setx SOC_PER_REG, %l7, %l0 | |
341 | stx %g0, [%l0] | |
342 | nop | |
343 | ||
344 | clear_esr_tt63: | |
345 | setx SOC_ESR_REG, %l7, %l0 | |
346 | stx %g0, [%l0] | |
347 | nop | |
348 | ||
349 | done | |
350 | nop | |
351 | ||
352 | ||
353 | ||
354 | ||
355 |