[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / mcu / n2_err_dram_dac_dau_fbr_fbu.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: n2_err_dram_dac_dau_fbr_fbu.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO

#define CMP_FBD_SYND 0x0

#include "hboot.s"
#include "asi_s.h"

#ifdef MCU0
#define L2_BANK_ADDR			0x00
#define	DRAM_FBR_CNT_REG_PA		DRAM_FBR_CNT_REG_PA_0
#define DRAM_ERR_CNT_REG_PA     	DRAM_ERR_CNT_REG_PA_0

#define DRAM_FBD_ERR_SYND_REG_PA        DRAM_FBD_ERR_SYND_REG_PA_0
#define DRAM_FBD_INJ_ERR_SRC_REG_PA     DRAM_FBD_INJ_ERR_SRC_REG_PA_0

#define  DRAM_ERR_INJ_REG   		0x8400000290
#define  DRAM_ERR_STAT_REG  		0x8400000280
#define  L2_ERR_STAT_REG    		0xAB00000000
#define  L2_ERR_ADDR_REG    		0xAC00000000
#define FBR_ERR 31

#endif

#ifdef MCU1
#define FBR_ERR 34
#define L2_BANK_ADDR			0x80
#define DRAM_FBR_CNT_REG_PA     	DRAM_FBR_CNT_REG_PA_1
#define DRAM_ERR_CNT_REG_PA     	DRAM_ERR_CNT_REG_PA_1

#define DRAM_FBD_ERR_SYND_REG_PA        DRAM_FBD_ERR_SYND_REG_PA_1
#define DRAM_FBD_INJ_ERR_SRC_REG_PA     DRAM_FBD_INJ_ERR_SRC_REG_PA_1

#define  DRAM_ERR_INJ_REG   		0x8400001290
#define  DRAM_ERR_STAT_REG  		0x8400001280
#define  L2_ERR_STAT_REG    		0xAB00000080
#define  L2_ERR_ADDR_REG    		0xAC00000080
#endif

#ifdef MCU2
#define FBR_ERR 37
#define L2_BANK_ADDR			0x100
#define DRAM_FBR_CNT_REG_PA     	DRAM_FBR_CNT_REG_PA_2
#define DRAM_ERR_CNT_REG_PA     	DRAM_ERR_CNT_REG_PA_2

#define DRAM_FBD_ERR_SYND_REG_PA        DRAM_FBD_ERR_SYND_REG_PA_2
#define DRAM_FBD_INJ_ERR_SRC_REG_PA     DRAM_FBD_INJ_ERR_SRC_REG_PA_2

#define  DRAM_ERR_INJ_REG   		0x8400002290
#define  DRAM_ERR_STAT_REG  		0x8400002280
#define  L2_ERR_STAT_REG    		0xAB00000100
#define  L2_ERR_ADDR_REG    		0xAC00000100
#endif

#ifdef MCU3
#define FBR_ERR 40

#define L2_BANK_ADDR			0x180
#define DRAM_FBR_CNT_REG_PA     	DRAM_FBR_CNT_REG_PA_3
#define	DRAM_ERR_CNT_REG_PA		DRAM_ERR_CNT_REG_PA_3

#define DRAM_FBD_ERR_SYND_REG_PA	DRAM_FBD_ERR_SYND_REG_PA_3
#define DRAM_FBD_INJ_ERR_SRC_REG_PA 	DRAM_FBD_INJ_ERR_SRC_REG_PA_3


#define  DRAM_ERR_INJ_REG   		0x8400003290
#define  DRAM_ERR_STAT_REG  		0x8400003280
#define  L2_ERR_STAT_REG    		0xAB00000180
#define  L2_ERR_ADDR_REG    		0xAC00000180
#endif

/********************************************************************
			Test Code Start
********************************************************************/
 
.text
.global	 main

main:
  ta	  T_CHANGE_HPRIV

disable_l1:
  ldxa  [%g0] ASI_LSU_CONTROL, %l0
  ! Remove the lower 2 bits (I-Cache and D-Cache enables)
  andn  %l0, 0x3, %l0
  stxa  %l0, [%g0] ASI_LSU_CONTROL


set_L2_Direct_Mapped_Mode:
  setx  L2CS_PA0, %l6, %g1
  add %g1,L2_BANK_ADDR,%g1
  mov   0x2, %l0
  stx   %l0, [%g1]

no_err_reporting:
  setx L2EE_PA0, %l0, %l1
  add   %l1, L2_BANK_ADDR, %l1
  mov  0x0, %l2
  stx  %l2, [%l1]

set_DRAM_error_inject_ch0:
  mov   0x2, %l1                ! ECC Mask (1-bit error)
  mov   0x1, %l2
  sllx  %l2, DRAM_EI_SSHOT, %l3
  or    %l1, %l3, %l1           ! Set single shot ;
  mov   0x1, %l2
  sllx  %l2, DRAM_EI_ENB, %l3
  or    %l1, %l3, %l1           ! Enable error injection for the next write
  setx  DRAM_ERR_INJ_REG, %l3, %g6
  stx   %l1, [%g6]
  membar 0x40


store_to_L2_way0:
  setx  0x555555555, %l0, %g5
  setx  0x22000000, %l0, %g7  ! bits [21:18] select way
  add   %g7,L2_BANK_ADDR,%g7
  stx %g5, [%g7]
  membar #Sync

! Storing to same L2 way0 but different tag,this will write to mcu
write_mcu_channel_0:
  setx  0x31000000, %l0, %g3 ! bits [21:18] select way
  add   %g3,L2_BANK_ADDR,%g3
  stx %g5, [%g3]
  membar #Sync

read_error_address_ch0:
 ldx   [%g7], %l3
  membar #Sync

set_DRAM_error_inject_ch0_dau:
  mov   0x606, %l1                ! ECC Mask (1-bit error)
  mov   0x1, %l2
  sllx  %l2, DRAM_EI_SSHOT, %l3
  or    %l1, %l3, %l1           ! Set single shot ;
  mov   0x1, %l2
  sllx  %l2, DRAM_EI_ENB, %l3
  or    %l1, %l3, %l1           ! Enable error injection for the next write
  setx  DRAM_ERR_INJ_REG, %l3, %g6
  stx   %l1, [%g6]
  membar 0x40
store_to_L2_way0_dau:
  setx  0x555555555, %l0, %g5
  setx  0x11000000, %l0, %g7  ! bits [21:18] select way
  add   %g7,L2_BANK_ADDR,%g7
  stx %g5, [%g7]
  membar #Sync

! Storing to same L2 way0 but different tag,this will write to mcu
write_mcu_channel_dau:
  setx  0x32000000, %l0, %g3 ! bits [21:18] select way
  add   %g3,L2_BANK_ADDR,%g3
  stx %g5, [%g3]
  membar #Sync

read_error_address_ch0_dau:
 ldx   [%g7], %l3
  membar #Sync

write_mcu_fbr_count_reg_fbr:
        set     0x10000, %g6            !<16>=countone=1
        setx    DRAM_FBR_CNT_REG_PA, %l7, %o2
        stx     %g6, [%o2]
        ldx     [%o2], %i1

set_error_count_reg_fbr:
        set     0x1, %g6            !<16>=countone=1
        setx    DRAM_ERR_CNT_REG_PA, %l7, %o2
        stx     %g6, [%o2]

set_inj_err_src_reg_fbr:
        set     0x3, %g1
        setx    DRAM_FBD_INJ_ERR_SRC_REG_PA, %l7, %g3
        stx     %g1, [%g3]
        membar 0x40

set_ejr_fbr:
        set     0x1, %g1
        sllx    %g1, FBR_ERR, %g2
        setx    SOC_EJR_REG, %l7, %g3
        stx     %g2, [%g3]
        membar 0x40

read_error_address_ch0_FBR:
  setx  0x31100000, %l0, %g7  ! bits [21:18] select way
  add   %g7,L2_BANK_ADDR,%g7
 ldx   [%g7], %l3
  membar #Sync
cyc_nop_0:
 setx    0x1111111111111110, %g7, %o0
        setx    0x2222222222222220, %g7, %o1
        setx    0x3333333333333330, %g7, %o2
        setx    0x4444444444444440, %g7, %o3
        setx    0x5555555555555550, %g7, %o4
        setx    0x6666666666666660, %g7, %o5
        setx    0x8888888888888880, %g7, %o6
        setx    0x9999999999999990, %g7, %o7

	clr %o1
	clr %o2
	clr %o3
	clr %o4
	clr %o5
	clr %o5
	clr %o6
	clr %o7


set_error_count_reg_fbu:
        set     0x1, %g6            !<16>=countone=1
        setx    DRAM_ERR_CNT_REG_PA, %l7, %o2
        stx     %g6, [%o2]

set_inj_err_src_reg_fbu:
        set     INJ_ERR_SRC, %g1
        setx    DRAM_FBD_INJ_ERR_SRC_REG_PA, %l7, %g3
        stx     %g1, [%g3]
        membar 0x40

set_ejr_fbu:
        set     0x1, %g1
        sllx    %g1, ERR_FIELD, %g2
        setx    SOC_EJR_REG, %l7, %g3
        stx     %g2, [%g3]
        membar 0x40

L2_Init:
        setx	0x1111111111111110, %g7, %o0
	setx	0x2222222222222220, %g7, %o1
	setx	0x3333333333333330, %g7, %o2
	setx	0x4444444444444440, %g7, %o3
	setx	0x5555555555555550, %g7, %o4
	setx	0x6666666666666660, %g7, %o5
	setx	0x8888888888888880, %g7, %o6
	setx	0x9999999999999990, %g7, %o7

	set	0x41000000, %l0
        add     %l0,L2_BANK_ADDR,%l0

        set     0x41000000, %l1
        add     %l1,L2_BANK_ADDR,%l1


L2_0:
     	stx	%o0, [%l0]
L2_1:
     	stx	%o1, [%l1]

L2_0_again:
	ldx	[%l0], %g1
	membar 0x40

L2_1_again:
	ldx	[%l1], %g2
	membar 0x40

	mov     0x1,%l5
	sllx    %l5, 18, %l6
	mov     0x10,%l7
	clr     %l4
line_flush:
        stx     %o3, [%l0]
	add     %l0,%l6,%l0
	inc     %l4
	cmp     %l4,%l7
	bne     line_flush
	nop


check_mcu_esr:
        mov     0x1, %l1
        sllx    %l1, DRAM_ES_FBU, %l4
        sllx    %l1, DRAM_ES_FBR, %l2
        or      %l2,%l4,%l6
        sllx    %l1, DRAM_ES_DAU, %l3
        sllx    %l1, DRAM_ES_DAC, %l2
        or      %l3,%l2,%l4
        or      %l4,%l6,%l6
        sllx    %l1, DRAM_ES_MEU, %l5
        sllx    %l1, DRAM_ES_MEC, %l3
        or      %l3,%l5,%l4
        or      %l4,%l6,%l6

        setx    DRAM_ERR_STAT_REG, %l3, %g5
        ldx     [%g5], %l1

        setx    0xffffffffffff0000, %l3, %l0
        andcc   %l0, %l1, %l5                   ! Donot check SYND bits

        subcc   %l5, %l6, %i4
        brnz    %i4, test_fail
        nop

read_fbd_err_synd_reg:
        setx    DRAM_FBD_ERR_SYND_REG_PA, %l7, %o2
        ldx     [%o2], %g1

        setx    0x8000000000000000, %l7, %o3
        set     0x1, %o4
        sll     %o4, FBSYND, %o5
        or      %o3, %o5, %g2

        and     %g1, %g2, %g3
        subcc   %g2, %g3, %g4
        brnz    %g4, test_fail
        nop

check_L2_ESR_0:
        setx    L2_ERR_STAT_REG, %l3, %g5
        ldx     [%g5], %l6

        setx    0xfffffffff0000000, %l3, %l0
        andcc   %l0, %l6, %l5                   ! Donot check L2ESR SYND bits

        mov     0x1, %l1
        sllx    %l1, L2ES_DAU, %l0
        sllx    %l1, L2ES_DAC, %l2
        or      %l0, %l2, %l2
        sllx    %l1, L2ES_VEU, %l3
        sllx    %l1, L2ES_VEC, %l4
        or      %l3, %l4, %l4
        or      %l2, %l4, %l4
        sllx    %l1, L2ES_MEU, %l7
        sllx    %l1, L2ES_MEC, %l6
        or      %l7, %l6, %l2
        or      %l4, %l2, %l2
        sllx    %l1, L2ES_DSC, %l0
        or      %l0, %l2, %i5

        subcc   %l5, %i5, %o5
        brnz    %o5, test_fail
        nop


ba test_pass
nop

/******************************************************
 * Exit code
 *******************************************************/

test_pass:
ta  T_GOOD_TRAP


test_fail:
ta  T_BAD_TRAP
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: n2_err_dram_dac_dau_fbr_fbu.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define MAIN_PAGE_NUCLEUS_ALSO
	39	#define MAIN_PAGE_HV_ALSO
	40
	41	#define CMP_FBD_SYND 0x0
	42
	43	#include "hboot.s"
	44	#include "asi_s.h"
	45
	46	#ifdef MCU0
	47	#define L2_BANK_ADDR 0x00
	48	#define DRAM_FBR_CNT_REG_PA DRAM_FBR_CNT_REG_PA_0
	49	#define DRAM_ERR_CNT_REG_PA DRAM_ERR_CNT_REG_PA_0
	50
	51	#define DRAM_FBD_ERR_SYND_REG_PA DRAM_FBD_ERR_SYND_REG_PA_0
	52	#define DRAM_FBD_INJ_ERR_SRC_REG_PA DRAM_FBD_INJ_ERR_SRC_REG_PA_0
	53
	54	#define DRAM_ERR_INJ_REG 0x8400000290
	55	#define DRAM_ERR_STAT_REG 0x8400000280
	56	#define L2_ERR_STAT_REG 0xAB00000000
	57	#define L2_ERR_ADDR_REG 0xAC00000000
	58	#define FBR_ERR 31
	59
	60	#endif
	61
	62	#ifdef MCU1
	63	#define FBR_ERR 34
	64	#define L2_BANK_ADDR 0x80
65	#define DRAM_FBR_CNT_REG_PA DRAM_FBR_CNT_REG_PA_1
66	#define DRAM_ERR_CNT_REG_PA DRAM_ERR_CNT_REG_PA_1
67
68	#define DRAM_FBD_ERR_SYND_REG_PA DRAM_FBD_ERR_SYND_REG_PA_1
69	#define DRAM_FBD_INJ_ERR_SRC_REG_PA DRAM_FBD_INJ_ERR_SRC_REG_PA_1
70
71	#define DRAM_ERR_INJ_REG 0x8400001290
72	#define DRAM_ERR_STAT_REG 0x8400001280
73	#define L2_ERR_STAT_REG 0xAB00000080
74	#define L2_ERR_ADDR_REG 0xAC00000080
75	#endif
76
77	#ifdef MCU2
78	#define FBR_ERR 37
79	#define L2_BANK_ADDR 0x100
80	#define DRAM_FBR_CNT_REG_PA DRAM_FBR_CNT_REG_PA_2
81	#define DRAM_ERR_CNT_REG_PA DRAM_ERR_CNT_REG_PA_2
82
83	#define DRAM_FBD_ERR_SYND_REG_PA DRAM_FBD_ERR_SYND_REG_PA_2
84	#define DRAM_FBD_INJ_ERR_SRC_REG_PA DRAM_FBD_INJ_ERR_SRC_REG_PA_2
85
86	#define DRAM_ERR_INJ_REG 0x8400002290
87	#define DRAM_ERR_STAT_REG 0x8400002280
88	#define L2_ERR_STAT_REG 0xAB00000100
89	#define L2_ERR_ADDR_REG 0xAC00000100
90	#endif
91
92	#ifdef MCU3
93	#define FBR_ERR 40
94
95	#define L2_BANK_ADDR 0x180
96	#define DRAM_FBR_CNT_REG_PA DRAM_FBR_CNT_REG_PA_3
97	#define DRAM_ERR_CNT_REG_PA DRAM_ERR_CNT_REG_PA_3
98
99	#define DRAM_FBD_ERR_SYND_REG_PA DRAM_FBD_ERR_SYND_REG_PA_3
100	#define DRAM_FBD_INJ_ERR_SRC_REG_PA DRAM_FBD_INJ_ERR_SRC_REG_PA_3
101
102
103	#define DRAM_ERR_INJ_REG 0x8400003290
104	#define DRAM_ERR_STAT_REG 0x8400003280
105	#define L2_ERR_STAT_REG 0xAB00000180
106	#define L2_ERR_ADDR_REG 0xAC00000180
107	#endif
108
109	/********************************************************************
110	Test Code Start
111	********************************************************************/
112
113	.text
114	.global main
115
116	main:
117	ta T_CHANGE_HPRIV
118
119	disable_l1:
120	ldxa [%g0] ASI_LSU_CONTROL, %l0
121	! Remove the lower 2 bits (I-Cache and D-Cache enables)
122	andn %l0, 0x3, %l0
123	stxa %l0, [%g0] ASI_LSU_CONTROL
124
125
126	set_L2_Direct_Mapped_Mode:
127	setx L2CS_PA0, %l6, %g1
128	add %g1,L2_BANK_ADDR,%g1
129	mov 0x2, %l0
130	stx %l0, [%g1]
131
132	no_err_reporting:
133	setx L2EE_PA0, %l0, %l1
134	add %l1, L2_BANK_ADDR, %l1
135	mov 0x0, %l2
136	stx %l2, [%l1]
137
138	set_DRAM_error_inject_ch0:
139	mov 0x2, %l1 ! ECC Mask (1-bit error)
140	mov 0x1, %l2
141	sllx %l2, DRAM_EI_SSHOT, %l3
142	or %l1, %l3, %l1 ! Set single shot ;
143	mov 0x1, %l2
144	sllx %l2, DRAM_EI_ENB, %l3
145	or %l1, %l3, %l1 ! Enable error injection for the next write
146	setx DRAM_ERR_INJ_REG, %l3, %g6
147	stx %l1, [%g6]
148	membar 0x40
149
150
151	store_to_L2_way0:
152	setx 0x555555555, %l0, %g5
153	setx 0x22000000, %l0, %g7 ! bits [21:18] select way
154	add %g7,L2_BANK_ADDR,%g7
155	stx %g5, [%g7]
156	membar #Sync
157
158	! Storing to same L2 way0 but different tag,this will write to mcu
159	write_mcu_channel_0:
160	setx 0x31000000, %l0, %g3 ! bits [21:18] select way
161	add %g3,L2_BANK_ADDR,%g3
162	stx %g5, [%g3]
163	membar #Sync
164
165	read_error_address_ch0:
166	ldx [%g7], %l3
167	membar #Sync
168
169	set_DRAM_error_inject_ch0_dau:
170	mov 0x606, %l1 ! ECC Mask (1-bit error)
171	mov 0x1, %l2
172	sllx %l2, DRAM_EI_SSHOT, %l3
173	or %l1, %l3, %l1 ! Set single shot ;
174	mov 0x1, %l2
175	sllx %l2, DRAM_EI_ENB, %l3
176	or %l1, %l3, %l1 ! Enable error injection for the next write
177	setx DRAM_ERR_INJ_REG, %l3, %g6
178	stx %l1, [%g6]
179	membar 0x40
180	store_to_L2_way0_dau:
181	setx 0x555555555, %l0, %g5
182	setx 0x11000000, %l0, %g7 ! bits [21:18] select way
183	add %g7,L2_BANK_ADDR,%g7
184	stx %g5, [%g7]
185	membar #Sync
186
187	! Storing to same L2 way0 but different tag,this will write to mcu
188	write_mcu_channel_dau:
189	setx 0x32000000, %l0, %g3 ! bits [21:18] select way
190	add %g3,L2_BANK_ADDR,%g3
191	stx %g5, [%g3]
192	membar #Sync
193
194	read_error_address_ch0_dau:
195	ldx [%g7], %l3
196	membar #Sync
197
198	write_mcu_fbr_count_reg_fbr:
199	set 0x10000, %g6 !<16>=countone=1
200	setx DRAM_FBR_CNT_REG_PA, %l7, %o2
201	stx %g6, [%o2]
202	ldx [%o2], %i1
203
204	set_error_count_reg_fbr:
205	set 0x1, %g6 !<16>=countone=1
206	setx DRAM_ERR_CNT_REG_PA, %l7, %o2
207	stx %g6, [%o2]
208
209	set_inj_err_src_reg_fbr:
210	set 0x3, %g1
211	setx DRAM_FBD_INJ_ERR_SRC_REG_PA, %l7, %g3
212	stx %g1, [%g3]
213	membar 0x40
214
215	set_ejr_fbr:
216	set 0x1, %g1
217	sllx %g1, FBR_ERR, %g2
218	setx SOC_EJR_REG, %l7, %g3
219	stx %g2, [%g3]
220	membar 0x40
221
222	read_error_address_ch0_FBR:
223	setx 0x31100000, %l0, %g7 ! bits [21:18] select way
224	add %g7,L2_BANK_ADDR,%g7
225	ldx [%g7], %l3
226	membar #Sync
227	cyc_nop_0:
228	setx 0x1111111111111110, %g7, %o0
229	setx 0x2222222222222220, %g7, %o1
230	setx 0x3333333333333330, %g7, %o2
231	setx 0x4444444444444440, %g7, %o3
232	setx 0x5555555555555550, %g7, %o4
233	setx 0x6666666666666660, %g7, %o5
234	setx 0x8888888888888880, %g7, %o6
235	setx 0x9999999999999990, %g7, %o7
236
237	clr %o1
238	clr %o2
239	clr %o3
240	clr %o4
241	clr %o5
242	clr %o5
243	clr %o6
244	clr %o7
245
246
247	set_error_count_reg_fbu:
248	set 0x1, %g6 !<16>=countone=1
249	setx DRAM_ERR_CNT_REG_PA, %l7, %o2
250	stx %g6, [%o2]
251
252	set_inj_err_src_reg_fbu:
253	set INJ_ERR_SRC, %g1
254	setx DRAM_FBD_INJ_ERR_SRC_REG_PA, %l7, %g3
255	stx %g1, [%g3]
256	membar 0x40
257
258	set_ejr_fbu:
259	set 0x1, %g1
260	sllx %g1, ERR_FIELD, %g2
261	setx SOC_EJR_REG, %l7, %g3
262	stx %g2, [%g3]
263	membar 0x40
264
265	L2_Init:
266	setx 0x1111111111111110, %g7, %o0
267	setx 0x2222222222222220, %g7, %o1
268	setx 0x3333333333333330, %g7, %o2
269	setx 0x4444444444444440, %g7, %o3
270	setx 0x5555555555555550, %g7, %o4
271	setx 0x6666666666666660, %g7, %o5
272	setx 0x8888888888888880, %g7, %o6
273	setx 0x9999999999999990, %g7, %o7
274
275	set 0x41000000, %l0
276	add %l0,L2_BANK_ADDR,%l0
277
278	set 0x41000000, %l1
279	add %l1,L2_BANK_ADDR,%l1
280
281
282
283	L2_0:
284	stx %o0, [%l0]
285	L2_1:
286	stx %o1, [%l1]
287
288	L2_0_again:
289	ldx [%l0], %g1
290	membar 0x40
291
292	L2_1_again:
293	ldx [%l1], %g2
294	membar 0x40
295
296	mov 0x1,%l5
297	sllx %l5, 18, %l6
298	mov 0x10,%l7
299	clr %l4
300	line_flush:
301	stx %o3, [%l0]
302	add %l0,%l6,%l0
303	inc %l4
304	cmp %l4,%l7
305	bne line_flush
306	nop
307
308
309	check_mcu_esr:
310	mov 0x1, %l1
311	sllx %l1, DRAM_ES_FBU, %l4
312	sllx %l1, DRAM_ES_FBR, %l2
313	or %l2,%l4,%l6
314	sllx %l1, DRAM_ES_DAU, %l3
315	sllx %l1, DRAM_ES_DAC, %l2
316	or %l3,%l2,%l4
317	or %l4,%l6,%l6
318	sllx %l1, DRAM_ES_MEU, %l5
319	sllx %l1, DRAM_ES_MEC, %l3
320	or %l3,%l5,%l4
321	or %l4,%l6,%l6
322
323	setx DRAM_ERR_STAT_REG, %l3, %g5
324	ldx [%g5], %l1
325
326	setx 0xffffffffffff0000, %l3, %l0
327	andcc %l0, %l1, %l5 ! Donot check SYND bits
328
329	subcc %l5, %l6, %i4
330	brnz %i4, test_fail
331	nop
332
333	read_fbd_err_synd_reg:
334	setx DRAM_FBD_ERR_SYND_REG_PA, %l7, %o2
335	ldx [%o2], %g1
336
337	setx 0x8000000000000000, %l7, %o3
338	set 0x1, %o4
339	sll %o4, FBSYND, %o5
340	or %o3, %o5, %g2
341
342	and %g1, %g2, %g3
343	subcc %g2, %g3, %g4
344	brnz %g4, test_fail
345	nop
346
347	check_L2_ESR_0:
348	setx L2_ERR_STAT_REG, %l3, %g5
349	ldx [%g5], %l6
350
351	setx 0xfffffffff0000000, %l3, %l0
352	andcc %l0, %l6, %l5 ! Donot check L2ESR SYND bits
353
354	mov 0x1, %l1
355	sllx %l1, L2ES_DAU, %l0
356	sllx %l1, L2ES_DAC, %l2
357	or %l0, %l2, %l2
358	sllx %l1, L2ES_VEU, %l3
359	sllx %l1, L2ES_VEC, %l4
360	or %l3, %l4, %l4
361	or %l2, %l4, %l4
362	sllx %l1, L2ES_MEU, %l7
363	sllx %l1, L2ES_MEC, %l6
364	or %l7, %l6, %l2
365	or %l4, %l2, %l2
366	sllx %l1, L2ES_DSC, %l0
367	or %l0, %l2, %i5
368
369	subcc %l5, %i5, %o5
370	brnz %o5, test_fail
371	nop
372
373
374
375
376	ba test_pass
377	nop
378
379	/******************************************************
380	* Exit code
381	*******************************************************/
382
383	test_pass:
384	ta T_GOOD_TRAP
385
386
387	test_fail:
388	ta T_BAD_TRAP
389
390
391
392
393