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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: n2_err_dram_dau_fbr.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap | |
39 | #define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap | |
40 | #define H_HT0_Data_access_error_0x32 Soc_data_access_error_trap | |
41 | !#define H_HT0_Data_access_error_0x32 Soc_Precise_data_access_error_trap | |
42 | ||
43 | ||
44 | #define MAIN_PAGE_NUCLEUS_ALSO | |
45 | #define MAIN_PAGE_HV_ALSO | |
46 | ||
47 | ||
48 | #include "hboot.s" | |
49 | #include "asi_s.h" | |
50 | ||
51 | #define L20 0x0020134000 | |
52 | #define L21 0x0000134040 | |
53 | ||
54 | #define L22 0x0000134080 | |
55 | #define L23 0x00001340c0 | |
56 | ||
57 | #define L24 0x0000134100 | |
58 | #define L25 0x0000134140 | |
59 | ||
60 | #define L26 0x0000134180 | |
61 | #define L27 0x00001341c0 | |
62 | #define DRAM_ERR_INJ_REG 0x8400000290 | |
63 | ||
64 | ||
65 | #define ERR_TYPE 0x3 | |
66 | ||
67 | ||
68 | #ifdef MCU0 | |
69 | #define DRAM_FBR_CNT_REG_PA DRAM_FBR_CNT_REG_PA_0 | |
70 | #define DRAM_ERR_CNT_REG_PA DRAM_ERR_CNT_REG_PA_0 | |
71 | ||
72 | #define DRAM_FBD_ERR_SYND_REG_PA DRAM_FBD_ERR_SYND_REG_PA_0 | |
73 | #define DRAM_FBD_INJ_ERR_SRC_REG_PA DRAM_FBD_INJ_ERR_SRC_REG_PA_0 | |
74 | ||
75 | #define DRAM_ERR_INJ_REG 0x8400000290 | |
76 | #define DRAM_ERR_STAT_REG 0x8400000280 | |
77 | #define L2_ERR_STAT_REG 0xAB00000000 | |
78 | #define L2_ERR_ADDR_REG 0xAC00000000 | |
79 | #define L2_BANK_ADDR 0x0 | |
80 | #endif | |
81 | ||
82 | #ifdef MCU1 | |
83 | #define DRAM_FBR_CNT_REG_PA DRAM_FBR_CNT_REG_PA_1 | |
84 | #define DRAM_ERR_CNT_REG_PA DRAM_ERR_CNT_REG_PA_1 | |
85 | ||
86 | #define DRAM_FBD_ERR_SYND_REG_PA DRAM_FBD_ERR_SYND_REG_PA_1 | |
87 | #define DRAM_FBD_INJ_ERR_SRC_REG_PA DRAM_FBD_INJ_ERR_SRC_REG_PA_1 | |
88 | ||
89 | #define DRAM_ERR_INJ_REG 0x8400001290 | |
90 | #define DRAM_ERR_STAT_REG 0x8400001280 | |
91 | #define L2_ERR_STAT_REG 0xAB00000080 | |
92 | #define L2_ERR_ADDR_REG 0xAC00000080 | |
93 | #define L2_BANK_ADDR 0x80 | |
94 | #endif | |
95 | ||
96 | #ifdef MCU2 | |
97 | #define DRAM_FBR_CNT_REG_PA DRAM_FBR_CNT_REG_PA_2 | |
98 | #define DRAM_ERR_CNT_REG_PA DRAM_ERR_CNT_REG_PA_2 | |
99 | ||
100 | #define DRAM_FBD_ERR_SYND_REG_PA DRAM_FBD_ERR_SYND_REG_PA_2 | |
101 | #define DRAM_FBD_INJ_ERR_SRC_REG_PA DRAM_FBD_INJ_ERR_SRC_REG_PA_2 | |
102 | ||
103 | #define DRAM_ERR_INJ_REG 0x8400002290 | |
104 | #define DRAM_ERR_STAT_REG 0x8400002280 | |
105 | #define L2_ERR_STAT_REG 0xAB00000100 | |
106 | #define L2_ERR_ADDR_REG 0xAC00000100 | |
107 | #define L2_BANK_ADDR 0x100 | |
108 | #endif | |
109 | ||
110 | #ifdef MCU3 | |
111 | #define DRAM_FBR_CNT_REG_PA DRAM_FBR_CNT_REG_PA_3 | |
112 | #define DRAM_ERR_CNT_REG_PA DRAM_ERR_CNT_REG_PA_3 | |
113 | ||
114 | #define DRAM_FBD_ERR_SYND_REG_PA DRAM_FBD_ERR_SYND_REG_PA_3 | |
115 | #define DRAM_FBD_INJ_ERR_SRC_REG_PA DRAM_FBD_INJ_ERR_SRC_REG_PA_3 | |
116 | ||
117 | ||
118 | #define DRAM_ERR_INJ_REG 0x8400003290 | |
119 | #define DRAM_ERR_STAT_REG 0x8400003280 | |
120 | #define L2_ERR_STAT_REG 0xAB00000180 | |
121 | #define L2_ERR_ADDR_REG 0xAC00000180 | |
122 | #define L2_BANK_ADDR 0x180 | |
123 | ||
124 | #endif | |
125 | ||
126 | #define CMP_ECC_CNT 0x1 | |
127 | ||
128 | #ifdef L2_OFF | |
129 | #define L2_ON_OFF_DM 0x1 | |
130 | #else | |
131 | #define L2_ON_OFF_DM 0x0 | |
132 | #endif | |
133 | ||
134 | #define TT 0x63 | |
135 | ||
136 | .text | |
137 | .global main | |
138 | .global My_Corrected_ECC_error_trap | |
139 | .global My_Recoverable_Sw_error_trap | |
140 | .global Soc_data_access_error_trap | |
141 | ||
142 | ||
143 | main: | |
144 | ta T_CHANGE_HPRIV | |
145 | clr %i6 | |
146 | clr %i7 | |
147 | clr %i2 | |
148 | clr %i0 | |
149 | ! Now access L2 control and status registers | |
150 | disable_l1: | |
151 | ldxa [%g0] ASI_LSU_CONTROL, %l0 | |
152 | ! Remove the lower 2 bits (I-Cache and D-Cache enables) | |
153 | andn %l0, 0x3, %l0 | |
154 | stxa %l0, [%g0] ASI_LSU_CONTROL | |
155 | ||
156 | ||
157 | set_L2_Direct_Mapped_Mode: | |
158 | setx L2CS_PA0, %l6, %g1 | |
159 | add %g1,L2_BANK_ADDR,%g1 | |
160 | mov 0x2, %l0 | |
161 | stx %l0, [%g1] | |
162 | ||
163 | ||
164 | enable_err_reporting: | |
165 | setx L2EE_PA0, %l0, %l1 | |
166 | ||
167 | ldx [%l1], %l2 | |
168 | mov 0x3, %l0 | |
169 | or %l2, %l0, %l2 | |
170 | ! stx %l2, [%l1] | |
171 | ||
172 | set_DRAM_error_inject_ch0: | |
173 | mov 0x606, %l1 ! ECC Mask (1-bit error) | |
174 | mov 0x1, %l2 | |
175 | sllx %l2, DRAM_EI_SSHOT, %l3 | |
176 | or %l1, %l3, %l1 ! Set single shot ; | |
177 | mov 0x1, %l2 | |
178 | sllx %l2, DRAM_EI_ENB, %l3 | |
179 | or %l1, %l3, %l1 ! Enable error injection for the next write | |
180 | setx DRAM_ERR_INJ_REG, %l3, %g6 | |
181 | ! add %g6, MCU_BANK_ADDR, %g6 | |
182 | stx %l1, [%g6] | |
183 | membar 0x40 | |
184 | ||
185 | ||
186 | store_to_L2_way0: | |
187 | setx 0x555555555, %l0, %g5 | |
188 | setx 0x22000000, %l0, %g7 ! bits [21:18] select way | |
189 | add %g7, L2_BANK_ADDR, %g7 | |
190 | stx %g5, [%g7] | |
191 | membar #Sync | |
192 | ||
193 | ! Storing to same L2 way0 but different tag,this will write to mcu | |
194 | write_mcu_channel_0: | |
195 | setx 0x31000000, %l0, %g3 ! bits [21:18] select way | |
196 | add %g3, L2_BANK_ADDR, %g3 | |
197 | stx %g5, [%g3] | |
198 | membar #Sync | |
199 | ||
200 | read_error_address_ch0: | |
201 | ldx [%g7], %l3 | |
202 | membar #Sync | |
203 | ||
204 | write_mcu_fbr_count_reg: | |
205 | set 0x10000, %g6 !<16>=countone=1 | |
206 | setx DRAM_FBR_CNT_REG_PA, %l7, %o2 | |
207 | stx %g6, [%o2] | |
208 | ldx [%o2], %i1 | |
209 | ||
210 | set_error_count_reg: | |
211 | set 0x1, %g6 !<16>=countone=1 | |
212 | setx DRAM_ERR_CNT_REG_PA, %l7, %o2 | |
213 | stx %g6, [%o2] | |
214 | ||
215 | clear_soc_esr: | |
216 | setx SOC_ESR_REG, %l7, %g5 | |
217 | stx %g0, [%g5] | |
218 | ||
219 | clear_soc_per: | |
220 | setx SOC_PER_REG, %l7, %g5 | |
221 | stx %g0, [%g5] | |
222 | ||
223 | clear_mcu_esr: | |
224 | setx DRAM_ERR_STAT_REG, %l7, %g5 | |
225 | stx %g0, [%g5] | |
226 | ||
227 | clear_l2_esr: | |
228 | setx L2_ERR_STAT_REG, %l7, %g5 | |
229 | stx %g0, [%g5] | |
230 | ||
231 | clear_l2_ear: | |
232 | setx L2_ERR_ADDR_REG, %l7, %g5 | |
233 | stx %g0, [%g5] | |
234 | ||
235 | set_inj_err_src_reg: | |
236 | set ERR_TYPE, %g1 | |
237 | setx DRAM_FBD_INJ_ERR_SRC_REG_PA, %l7, %g3 | |
238 | stx %g1, [%g3] | |
239 | membar 0x40 | |
240 | ||
241 | set_ejr: | |
242 | set 0x1, %g1 | |
243 | sllx %g1, ERR_FIELD, %g2 | |
244 | setx SOC_EJR_REG, %l7, %g3 | |
245 | stx %g2, [%g3] | |
246 | membar 0x40 | |
247 | ||
248 | set_eie: | |
249 | setx SOC_EIE_REG, %l7, %g3 | |
250 | stx %g2, [%g3] | |
251 | membar 0x40 | |
252 | ||
253 | read_error_address_ch0_FBR: | |
254 | ldx [%g7], %l3 | |
255 | membar #Sync | |
256 | ||
257 | idle_cycles: | |
258 | setx 0xfffffffffff,%l0,%l1 | |
259 | setx 0x12345678910,%l0,%l1 | |
260 | setx 0x55555555555,%l0,%l1 | |
261 | setx 0x66666666666,%l0,%l1 | |
262 | setx 0x77777777777,%l0,%l1 | |
263 | setx 0x88888888888,%l0,%l1 | |
264 | setx 0xfffffffffff,%l0,%l1 | |
265 | setx 0x12345678910,%l0,%l1 | |
266 | setx 0x55555555555,%l0,%l1 | |
267 | setx 0x66666666666,%l0,%l1 | |
268 | ||
269 | ||
270 | ||
271 | ||
272 | check_error_trap: | |
273 | setx EXECUTED, %l1, %l0 | |
274 | cmp %i2, %l0 | |
275 | bne test_fail | |
276 | nop | |
277 | ||
278 | mov TT, %l0 | |
279 | cmp %i0, %l0 | |
280 | bne test_fail | |
281 | nop | |
282 | ||
283 | /****************************************************** | |
284 | * Exit code | |
285 | *******************************************************/ | |
286 | ||
287 | test_pass: | |
288 | EXIT_GOOD | |
289 | ||
290 | test_fail: | |
291 | EXIT_BAD | |
292 | ||
293 | ||
294 | ||
295 | ||
296 | /************************************************************************ | |
297 | Trap Handlers | |
298 | ************************************************************************/ | |
299 | My_Recoverable_Sw_error_trap: | |
300 | nop | |
301 | ba test_fail | |
302 | nop | |
303 | ||
304 | !PER not cleared at the end of the TRAP Handler to avoid further Trap | |
305 | My_Corrected_ECC_error_trap: | |
306 | ! Signal trap taken | |
307 | setx EXECUTED, %l0, %i2 | |
308 | ! save trap type value | |
309 | rdpr %tt, %i0 | |
310 | ||
311 | inc %i7 | |
312 | ||
313 | clear_ejr_tt63: | |
314 | setx SOC_EJR_REG, %l7, %l0 | |
315 | stx %g0, [%l0] | |
316 | nop | |
317 | ||
318 | check_desr_tt63: | |
319 | ldxa [%g0]0x4c, %g2 | |
320 | nop | |
321 | setx 0x8b00000000000000, %l0, %g3 | |
322 | subcc %g2, %g3, %g4 | |
323 | brnz %g4, test_fail | |
324 | nop | |
325 | ||
326 | check_per_tt63: | |
327 | setx SOC_PER_REG, %l7, %g5 | |
328 | ldx [%g5], %i1 | |
329 | nop | |
330 | setx 0x8000000000000000, %l7, %g7 !valid bit | |
331 | set 0x1, %g1 | |
332 | sllx %g1, ERR_FIELD, %g2 | |
333 | or %g7, %g2, %i3 | |
334 | subcc %i1, %i3, %i4 | |
335 | brnz %i4, test_fail | |
336 | nop | |
337 | ||
338 | check_mcu_ESR_tt63: | |
339 | mov 0x1, %l1 | |
340 | sllx %l1, DRAM_ES_FBR, %l6 | |
341 | sllx %l1, DRAM_ES_DAU, %l3 | |
342 | or %l6,%l3,%l6 | |
343 | ||
344 | setx DRAM_ERR_STAT_REG, %l3, %g5 | |
345 | ldx [%g5], %l1 | |
346 | ||
347 | setx 0x3fffffffffff0000, %l3, %l0 ! MEC bit not checked | |
348 | andcc %l0, %l1, %l5 | |
349 | ||
350 | sub %l5, %l6, %i4 | |
351 | brnz %i4, test_fail | |
352 | nop | |
353 | ||
354 | ||
355 | check_mcu_EAR_tt63: | |
356 | setx DRAM_ERR_ADDR_REG_PA_0, %l3, %g5 | |
357 | ldx [%g5], %l1 | |
358 | ||
359 | ||
360 | /* | |
361 | ! Setting DSC and/ or DSU does not cause any logging of the error | |
362 | ! address or syndrome in the L2 Error Address register. | |
363 | ! It also does not update the VEC/VEU/MEC/MEU bits */ | |
364 | check_L2_ESR_tt63: | |
365 | setx L2_ERR_STAT_REG, %l3, %g5 | |
366 | ldx [%g5], %l6 | |
367 | ||
368 | setx 0x3ffffffff0000000, %l3, %l0 | |
369 | andcc %l0, %l6, %l5 ! Donot check L2ESR SYND bits and MEC | |
370 | ||
371 | mov 0x1, %l1 | |
372 | sllx %l1, L2ES_DSC, %l0 | |
373 | sllx %l1, L2ES_DAU, %l3 | |
374 | or %l0,%l3,%l0 | |
375 | sllx %l1, L2ES_VEU, %l3 | |
376 | or %l0,%l3,%l0 | |
377 | ||
378 | cmp %l5, %l0 | |
379 | bne %xcc, test_fail | |
380 | nop | |
381 | ||
382 | check_fbr_cnt_reg_tt63: | |
383 | setx DRAM_FBR_CNT_REG_PA, %l7, %o2 | |
384 | ldx [%o2], %g1 | |
385 | set 0x10000, %g6 !<16>=countone=1 | |
386 | sub %g1, %g6, %i4 | |
387 | brnz %i4, test_fail | |
388 | nop | |
389 | ||
390 | read_err_cnt_reg_tt63: | |
391 | setx DRAM_ERR_CNT_REG_PA, %l7, %o2 | |
392 | ldx [%o2], %g1 | |
393 | set CMP_ECC_CNT, %i1 | |
394 | sub %g1, %i1, %i4 | |
395 | brnz %i4, test_fail | |
396 | nop | |
397 | ||
398 | read_fbd_err_synd_reg_tt63: | |
399 | setx DRAM_FBD_ERR_SYND_REG_PA, %l7, %o2 | |
400 | ldx [%o2], %g1 | |
401 | ||
402 | setx 0x8000000000000000, %l7, %o3 | |
403 | set 0x1, %o4 | |
404 | sll %o4, FBSYND, %o5 | |
405 | or %o3, %o5, %g2 | |
406 | ||
407 | and %g1, %g2, %g3 | |
408 | subcc %g2, %g3, %g4 | |
409 | brnz %g4, test_fail | |
410 | nop | |
411 | ||
412 | clear_per_tt63: | |
413 | setx SOC_PER_REG, %l7, %l0 | |
414 | stx %g0, [%l0] | |
415 | nop | |
416 | ||
417 | clear_esr_tt63: | |
418 | setx SOC_ESR_REG, %l7, %l0 | |
419 | stx %g0, [%l0] | |
420 | nop | |
421 | ||
422 | done | |
423 | nop | |
424 | ||
425 | ||
426 | Soc_data_access_error_trap: | |
427 | #define L2_ES_W1C_VALUE 0xc03ffff800000000 | |
428 | read_trap_type_Da: | |
429 | setx EXECUTED, %l0, %o0 | |
430 | ! save trap type value | |
431 | rdpr %tt, %o1 | |
432 | nop | |
433 | mov 0x32, %i7 | |
434 | cmp %o1, %i7 | |
435 | tne %xcc, T_BAD_TRAP | |
436 | ||
437 | setx 0x000000000000000f, %l0, %i5 | |
438 | mov 0x1,%l7 | |
439 | check_clear_dsfsr_Da: | |
440 | add %g0, SFSR_VA, %i7 | |
441 | ldxa [%i7]ASI_DSFSR, %i6 | |
442 | ! setx 0x0000000000000002, %l0, %i5 | |
443 | mov 0x2,%g7 | |
444 | cmp %i6,%g7 | |
445 | tne %xcc, T_BAD_TRAP | |
446 | stxa %g0, [%i7]ASI_DSFSR | |
447 | nop | |
448 | done | |
449 | nop | |
450 | ||
451 | !! END Of SOC Error Handlers !! | |
452 | ||
453 | ||
454 | ||
455 |