[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / mcu / n2_err_dram_ecc_crc_idt.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: n2_err_dram_ecc_crc_idt.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO

#define CMP_FBD_SYND 0x0

#include "hboot.s"
#include "asi_s.h"

#ifdef MCU0
#define L2_BANK_ADDR			0x00
#define	DRAM_FBR_CNT_REG_PA		DRAM_FBR_CNT_REG_PA_0
#define DRAM_ERR_CNT_REG_PA     	DRAM_ERR_CNT_REG_PA_0

#define DRAM_FBD_ERR_SYND_REG_PA        DRAM_FBD_ERR_SYND_REG_PA_0
#define DRAM_FBD_INJ_ERR_SRC_REG_PA     DRAM_FBD_INJ_ERR_SRC_REG_PA_0

#define  DRAM_ERR_INJ_REG   		0x8400000290
#define  DRAM_ERR_STAT_REG  		0x8400000280
#define  L2_ERR_STAT_REG    		0xAB00000000
#define  L2_ERR_ADDR_REG    		0xAC00000000
#define FBR_ERR 31

#endif

#ifdef MCU1
#define FBR_ERR 34
#define L2_BANK_ADDR			0x80
#define DRAM_FBR_CNT_REG_PA     	DRAM_FBR_CNT_REG_PA_1
#define DRAM_ERR_CNT_REG_PA     	DRAM_ERR_CNT_REG_PA_1

#define DRAM_FBD_ERR_SYND_REG_PA        DRAM_FBD_ERR_SYND_REG_PA_1
#define DRAM_FBD_INJ_ERR_SRC_REG_PA     DRAM_FBD_INJ_ERR_SRC_REG_PA_1

#define  DRAM_ERR_INJ_REG   		0x8400001290
#define  DRAM_ERR_STAT_REG  		0x8400001280
#define  L2_ERR_STAT_REG    		0xAB00000080
#define  L2_ERR_ADDR_REG    		0xAC00000080
#endif

#ifdef MCU2
#define FBR_ERR 37
#define L2_BANK_ADDR			0x100
#define DRAM_FBR_CNT_REG_PA     	DRAM_FBR_CNT_REG_PA_2
#define DRAM_ERR_CNT_REG_PA     	DRAM_ERR_CNT_REG_PA_2

#define DRAM_FBD_ERR_SYND_REG_PA        DRAM_FBD_ERR_SYND_REG_PA_2
#define DRAM_FBD_INJ_ERR_SRC_REG_PA     DRAM_FBD_INJ_ERR_SRC_REG_PA_2

#define  DRAM_ERR_INJ_REG   		0x8400002290
#define  DRAM_ERR_STAT_REG  		0x8400002280
#define  L2_ERR_STAT_REG    		0xAB00000100
#define  L2_ERR_ADDR_REG    		0xAC00000100
#endif

#ifdef MCU3
#define FBR_ERR 40

#define L2_BANK_ADDR			0x180
#define DRAM_FBR_CNT_REG_PA     	DRAM_FBR_CNT_REG_PA_3
#define	DRAM_ERR_CNT_REG_PA		DRAM_ERR_CNT_REG_PA_3

#define DRAM_FBD_ERR_SYND_REG_PA	DRAM_FBD_ERR_SYND_REG_PA_3
#define DRAM_FBD_INJ_ERR_SRC_REG_PA 	DRAM_FBD_INJ_ERR_SRC_REG_PA_3


#define  DRAM_ERR_INJ_REG   		0x8400003290
#define  DRAM_ERR_STAT_REG  		0x8400003280
#define  L2_ERR_STAT_REG    		0xAB00000180
#define  L2_ERR_ADDR_REG    		0xAC00000180
#endif

/********************************************************************
			Test Code Start
********************************************************************/
 
.text
.global	 main

main:
  ta	  T_CHANGE_HPRIV

disable_l1:
  ldxa  [%g0] ASI_LSU_CONTROL, %l0
  ! Remove the lower 2 bits (I-Cache and D-Cache enables)
  andn  %l0, 0x3, %l0
  stxa  %l0, [%g0] ASI_LSU_CONTROL


set_L2_Direct_Mapped_Mode:
  setx  L2CS_PA0, %l6, %g1
  add %g1,L2_BANK_ADDR,%g1
  mov   0x2, %l0
  stx   %l0, [%g1]

no_err_reporting:
  setx L2EE_PA0, %l0, %l1
  mov  0x0, %l2
  stx  %l2, [%l1+0x0]
  stx  %l2, [%l1+0x40]
  stx  %l2, [%l1+0x80]
  stx  %l2, [%l1+0xc0]
  stx  %l2, [%l1+0x100]
  stx  %l2, [%l1+0x140]
  stx  %l2, [%l1+0x180]
  stx  %l2, [%l1+0x1c0]

set_error_count_reg_fbu:
        set     0x1, %g6            !<16>=countone=1
        setx    DRAM_ERR_CNT_REG_PA, %l7, %o2
        stx     %g6, [%o2]

set_inj_err_src_reg_fbu:
        set     INJ_ERR_SRC, %g1
        setx    DRAM_FBD_INJ_ERR_SRC_REG_PA, %l7, %g3
        stx     %g1, [%g3]
        membar 0x40

set_ejr_fbu:
        set     0x1, %g1
        sllx    %g1, ERR_FIELD, %g2
        setx    SOC_EJR_REG, %l7, %g3
        stx     %g2, [%g3]
        membar 0x40

L2_Init:
        set     0x11111111, %o0
        set     0x41000000, %l0
        add     %l0,L2_BANK_ADDR,%l0

        set     0x41000000, %l1
        add     %l1,L2_BANK_ADDR,%l1
L2_0:
        stx     %o0, [%l0]
	membar #Sync
L2_1:
        stx     %o0, [%l1]
	membar #Sync

clear_fbu:
        setx    SOC_EJR_REG, %l7, %g3
        stx     %g0, [%g3]
        membar #Sync


        mov     0x1,%l5
        sllx    %l5, 18, %l6
        mov     0x10,%l7
        clr     %l4
line_flush:
        stx     %o3, [%l0]
        add     %l0,%l6,%l0
        inc     %l4
        cmp     %l4,%l7
        bne     line_flush
        nop

set_DRAM_error_inject_ch0:
  mov   0x2, %l1                ! ECC Mask (1-bit error)
  mov   0x1, %l2
  sllx  %l2, DRAM_EI_SSHOT, %l3
  or    %l1, %l3, %l1           ! Set single shot ;
  mov   0x1, %l2
  sllx  %l2, DRAM_EI_ENB, %l3
  or    %l1, %l3, %l1           ! Enable error injection for the next write
  setx  DRAM_ERR_INJ_REG, %l3, %g6
  stx   %l1, [%g6]
  membar 0x40


store_to_L2_way0:
  setx  0x555555555, %l0, %g5
  setx  0x22000000, %l0, %g7  ! bits [21:18] select way
  add   %g7,L2_BANK_ADDR,%g7
  stx %g5, [%g7]
  membar #Sync

! Storing to same L2 way0 but different tag,this will write to mcu
write_mcu_channel_0:
  setx  0x31000000, %l0, %g3 ! bits [21:18] select way
  add   %g3,L2_BANK_ADDR,%g3
  stx %g5, [%g3]
  membar #Sync

read_error_address_ch0:
 ldx   [%g7], %l3
  membar #Sync

set_DRAM_error_inject_ch0_dau:
  mov   0x606, %l1                ! ECC Mask (1-bit error)
  mov   0x1, %l2
  sllx  %l2, DRAM_EI_SSHOT, %l3
  or    %l1, %l3, %l1           ! Set single shot ;
  mov   0x1, %l2
  sllx  %l2, DRAM_EI_ENB, %l3
  or    %l1, %l3, %l1           ! Enable error injection for the next write
  setx  DRAM_ERR_INJ_REG, %l3, %g6
  stx   %l1, [%g6]
  membar 0x40
store_to_L2_way0_dau:
  setx  0x555555555, %l0, %g5
  setx  0x11000000, %l0, %g7  ! bits [21:18] select way
  add   %g7,L2_BANK_ADDR,%g7
  stx %g5, [%g7]
  membar #Sync

! Storing to same L2 way0 but different tag,this will write to mcu
write_mcu_channel_dau:
  setx  0x32000000, %l0, %g3 ! bits [21:18] select way
  add   %g3,L2_BANK_ADDR,%g3
  stx %g5, [%g3]
  membar #Sync

read_error_address_ch0_dau:
 ldx   [%g7], %l3
  membar #Sync

write_mcu_fbr_count_reg_fbr:
        set     0x10000, %g6            !<16>=countone=1
        setx    DRAM_FBR_CNT_REG_PA, %l7, %o2
        stx     %g6, [%o2]
        ldx     [%o2], %i1

set_error_count_reg_fbr:
        set     0x1, %g6            !<16>=countone=1
        setx    DRAM_ERR_CNT_REG_PA, %l7, %o2
        stx     %g6, [%o2]

set_inj_err_src_reg_fbr:
        set     0x3, %g1
        setx    DRAM_FBD_INJ_ERR_SRC_REG_PA, %l7, %g3
        stx     %g1, [%g3]
        membar 0x40

set_ejr_fbr:
        set     0x1, %g1
        sllx    %g1, FBR_ERR, %g2
        setx    SOC_EJR_REG, %l7, %g3
        stx     %g2, [%g3]
        membar 0x40

read_error_address_ch0_FBR:
  setx  0x31100000, %l0, %g7  ! bits [21:18] select way
  add   %g7,L2_BANK_ADDR,%g7
 ldx   [%g7], %l3
  membar #Sync
cyc_nop_0:
 setx    0x1111111111111110, %g7, %o0
        setx    0x2222222222222220, %g7, %o1
        setx    0x3333333333333330, %g7, %o2
        setx    0x4444444444444440, %g7, %o3
        setx    0x5555555555555550, %g7, %o4
        setx    0x6666666666666660, %g7, %o5
        setx    0x8888888888888880, %g7, %o6
        setx    0x9999999999999990, %g7, %o7

	clr %o1
	clr %o2
	clr %o3
	clr %o4
	clr %o5
	clr %o5
	clr %o6
	clr %o7


clear_dac_mec:
        setx    DRAM_ERR_STAT_REG, %l0, %g5
        setx    0x6000000000000000, %l0, %l1
        stx     %l1, [%g5]
        setx    L2_ERR_STAT_REG, %l0, %g5
        setx    0x4000041000000000, %l0, %l1
        stx     %l1, [%g5]


check_mcu_esr:
        mov     0x1, %l1
        sllx    %l1, DRAM_ES_FBU, %l4
        sllx    %l1, DRAM_ES_DAU, %l2
        or      %l2,%l4,%l3
        sllx    %l1, DRAM_ES_MEU, %l5
        or      %l5,%l3,%l6
	

        setx    DRAM_ERR_STAT_REG, %l3, %g5
        ldx     [%g5], %l1

        subcc   %l1, %l6, %i4
        brnz    %i4, test_fail
        nop

read_fbd_err_synd_reg:
        setx    DRAM_FBD_ERR_SYND_REG_PA, %l7, %o2
        ldx     [%o2], %g1

        setx    0x8000000000000000, %l7, %o3
        set     0x1, %o4
        sll     %o4, FBSYND, %o5
        or      %o3, %o5, %g2

        and     %g1, %g2, %g3
        subcc   %g2, %g3, %g4
        brnz    %g4, test_fail
        nop

check_L2_ESR_0:
        setx    L2_ERR_STAT_REG, %l3, %g5
        ldx     [%g5], %l6

        setx    0xfffffffff0000000, %l3, %l0
        andcc   %l0, %l6, %l5                   ! Donot check L2ESR SYND bits

        mov     0x1, %l1
        sllx    %l1, L2ES_DAU, %l0
        sllx    %l1, L2ES_VEU, %l3
        or      %l0, %l3, %l4
        sllx    %l1, L2ES_MEU, %l7
        or      %l4, %l7, %l2

        subcc   %l5, %l2, %o5
        brnz    %o5, test_fail
        nop


ba test_pass
nop

/******************************************************
 * Exit code
 *******************************************************/

test_pass:
ta  T_GOOD_TRAP


test_fail:
ta  T_BAD_TRAP
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: n2_err_dram_ecc_crc_idt.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define MAIN_PAGE_NUCLEUS_ALSO
	39	#define MAIN_PAGE_HV_ALSO
	40
	41	#define CMP_FBD_SYND 0x0
	42
	43	#include "hboot.s"
	44	#include "asi_s.h"
	45
	46	#ifdef MCU0
	47	#define L2_BANK_ADDR 0x00
	48	#define DRAM_FBR_CNT_REG_PA DRAM_FBR_CNT_REG_PA_0
	49	#define DRAM_ERR_CNT_REG_PA DRAM_ERR_CNT_REG_PA_0
	50
	51	#define DRAM_FBD_ERR_SYND_REG_PA DRAM_FBD_ERR_SYND_REG_PA_0
	52	#define DRAM_FBD_INJ_ERR_SRC_REG_PA DRAM_FBD_INJ_ERR_SRC_REG_PA_0
	53
	54	#define DRAM_ERR_INJ_REG 0x8400000290
	55	#define DRAM_ERR_STAT_REG 0x8400000280
	56	#define L2_ERR_STAT_REG 0xAB00000000
	57	#define L2_ERR_ADDR_REG 0xAC00000000
	58	#define FBR_ERR 31
	59
	60	#endif
	61
	62	#ifdef MCU1
	63	#define FBR_ERR 34
	64	#define L2_BANK_ADDR 0x80
65	#define DRAM_FBR_CNT_REG_PA DRAM_FBR_CNT_REG_PA_1
66	#define DRAM_ERR_CNT_REG_PA DRAM_ERR_CNT_REG_PA_1
67
68	#define DRAM_FBD_ERR_SYND_REG_PA DRAM_FBD_ERR_SYND_REG_PA_1
69	#define DRAM_FBD_INJ_ERR_SRC_REG_PA DRAM_FBD_INJ_ERR_SRC_REG_PA_1
70
71	#define DRAM_ERR_INJ_REG 0x8400001290
72	#define DRAM_ERR_STAT_REG 0x8400001280
73	#define L2_ERR_STAT_REG 0xAB00000080
74	#define L2_ERR_ADDR_REG 0xAC00000080
75	#endif
76
77	#ifdef MCU2
78	#define FBR_ERR 37
79	#define L2_BANK_ADDR 0x100
80	#define DRAM_FBR_CNT_REG_PA DRAM_FBR_CNT_REG_PA_2
81	#define DRAM_ERR_CNT_REG_PA DRAM_ERR_CNT_REG_PA_2
82
83	#define DRAM_FBD_ERR_SYND_REG_PA DRAM_FBD_ERR_SYND_REG_PA_2
84	#define DRAM_FBD_INJ_ERR_SRC_REG_PA DRAM_FBD_INJ_ERR_SRC_REG_PA_2
85
86	#define DRAM_ERR_INJ_REG 0x8400002290
87	#define DRAM_ERR_STAT_REG 0x8400002280
88	#define L2_ERR_STAT_REG 0xAB00000100
89	#define L2_ERR_ADDR_REG 0xAC00000100
90	#endif
91
92	#ifdef MCU3
93	#define FBR_ERR 40
94
95	#define L2_BANK_ADDR 0x180
96	#define DRAM_FBR_CNT_REG_PA DRAM_FBR_CNT_REG_PA_3
97	#define DRAM_ERR_CNT_REG_PA DRAM_ERR_CNT_REG_PA_3
98
99	#define DRAM_FBD_ERR_SYND_REG_PA DRAM_FBD_ERR_SYND_REG_PA_3
100	#define DRAM_FBD_INJ_ERR_SRC_REG_PA DRAM_FBD_INJ_ERR_SRC_REG_PA_3
101
102
103	#define DRAM_ERR_INJ_REG 0x8400003290
104	#define DRAM_ERR_STAT_REG 0x8400003280
105	#define L2_ERR_STAT_REG 0xAB00000180
106	#define L2_ERR_ADDR_REG 0xAC00000180
107	#endif
108
109	/********************************************************************
110	Test Code Start
111	********************************************************************/
112
113	.text
114	.global main
115
116	main:
117	ta T_CHANGE_HPRIV
118
119	disable_l1:
120	ldxa [%g0] ASI_LSU_CONTROL, %l0
121	! Remove the lower 2 bits (I-Cache and D-Cache enables)
122	andn %l0, 0x3, %l0
123	stxa %l0, [%g0] ASI_LSU_CONTROL
124
125
126	set_L2_Direct_Mapped_Mode:
127	setx L2CS_PA0, %l6, %g1
128	add %g1,L2_BANK_ADDR,%g1
129	mov 0x2, %l0
130	stx %l0, [%g1]
131
132	no_err_reporting:
133	setx L2EE_PA0, %l0, %l1
134	mov 0x0, %l2
135	stx %l2, [%l1+0x0]
136	stx %l2, [%l1+0x40]
137	stx %l2, [%l1+0x80]
138	stx %l2, [%l1+0xc0]
139	stx %l2, [%l1+0x100]
140	stx %l2, [%l1+0x140]
141	stx %l2, [%l1+0x180]
142	stx %l2, [%l1+0x1c0]
143
144	set_error_count_reg_fbu:
145	set 0x1, %g6 !<16>=countone=1
146	setx DRAM_ERR_CNT_REG_PA, %l7, %o2
147	stx %g6, [%o2]
148
149	set_inj_err_src_reg_fbu:
150	set INJ_ERR_SRC, %g1
151	setx DRAM_FBD_INJ_ERR_SRC_REG_PA, %l7, %g3
152	stx %g1, [%g3]
153	membar 0x40
154
155	set_ejr_fbu:
156	set 0x1, %g1
157	sllx %g1, ERR_FIELD, %g2
158	setx SOC_EJR_REG, %l7, %g3
159	stx %g2, [%g3]
160	membar 0x40
161
162	L2_Init:
163	set 0x11111111, %o0
164	set 0x41000000, %l0
165	add %l0,L2_BANK_ADDR,%l0
166
167	set 0x41000000, %l1
168	add %l1,L2_BANK_ADDR,%l1
169	L2_0:
170	stx %o0, [%l0]
171	membar #Sync
172	L2_1:
173	stx %o0, [%l1]
174	membar #Sync
175
176	clear_fbu:
177	setx SOC_EJR_REG, %l7, %g3
178	stx %g0, [%g3]
179	membar #Sync
180
181
182	mov 0x1,%l5
183	sllx %l5, 18, %l6
184	mov 0x10,%l7
185	clr %l4
186	line_flush:
187	stx %o3, [%l0]
188	add %l0,%l6,%l0
189	inc %l4
190	cmp %l4,%l7
191	bne line_flush
192	nop
193
194	set_DRAM_error_inject_ch0:
195	mov 0x2, %l1 ! ECC Mask (1-bit error)
196	mov 0x1, %l2
197	sllx %l2, DRAM_EI_SSHOT, %l3
198	or %l1, %l3, %l1 ! Set single shot ;
199	mov 0x1, %l2
200	sllx %l2, DRAM_EI_ENB, %l3
201	or %l1, %l3, %l1 ! Enable error injection for the next write
202	setx DRAM_ERR_INJ_REG, %l3, %g6
203	stx %l1, [%g6]
204	membar 0x40
205
206
207	store_to_L2_way0:
208	setx 0x555555555, %l0, %g5
209	setx 0x22000000, %l0, %g7 ! bits [21:18] select way
210	add %g7,L2_BANK_ADDR,%g7
211	stx %g5, [%g7]
212	membar #Sync
213
214	! Storing to same L2 way0 but different tag,this will write to mcu
215	write_mcu_channel_0:
216	setx 0x31000000, %l0, %g3 ! bits [21:18] select way
217	add %g3,L2_BANK_ADDR,%g3
218	stx %g5, [%g3]
219	membar #Sync
220
221	read_error_address_ch0:
222	ldx [%g7], %l3
223	membar #Sync
224
225	set_DRAM_error_inject_ch0_dau:
226	mov 0x606, %l1 ! ECC Mask (1-bit error)
227	mov 0x1, %l2
228	sllx %l2, DRAM_EI_SSHOT, %l3
229	or %l1, %l3, %l1 ! Set single shot ;
230	mov 0x1, %l2
231	sllx %l2, DRAM_EI_ENB, %l3
232	or %l1, %l3, %l1 ! Enable error injection for the next write
233	setx DRAM_ERR_INJ_REG, %l3, %g6
234	stx %l1, [%g6]
235	membar 0x40
236	store_to_L2_way0_dau:
237	setx 0x555555555, %l0, %g5
238	setx 0x11000000, %l0, %g7 ! bits [21:18] select way
239	add %g7,L2_BANK_ADDR,%g7
240	stx %g5, [%g7]
241	membar #Sync
242
243	! Storing to same L2 way0 but different tag,this will write to mcu
244	write_mcu_channel_dau:
245	setx 0x32000000, %l0, %g3 ! bits [21:18] select way
246	add %g3,L2_BANK_ADDR,%g3
247	stx %g5, [%g3]
248	membar #Sync
249
250	read_error_address_ch0_dau:
251	ldx [%g7], %l3
252	membar #Sync
253
254	write_mcu_fbr_count_reg_fbr:
255	set 0x10000, %g6 !<16>=countone=1
256	setx DRAM_FBR_CNT_REG_PA, %l7, %o2
257	stx %g6, [%o2]
258	ldx [%o2], %i1
259
260	set_error_count_reg_fbr:
261	set 0x1, %g6 !<16>=countone=1
262	setx DRAM_ERR_CNT_REG_PA, %l7, %o2
263	stx %g6, [%o2]
264
265	set_inj_err_src_reg_fbr:
266	set 0x3, %g1
267	setx DRAM_FBD_INJ_ERR_SRC_REG_PA, %l7, %g3
268	stx %g1, [%g3]
269	membar 0x40
270
271	set_ejr_fbr:
272	set 0x1, %g1
273	sllx %g1, FBR_ERR, %g2
274	setx SOC_EJR_REG, %l7, %g3
275	stx %g2, [%g3]
276	membar 0x40
277
278	read_error_address_ch0_FBR:
279	setx 0x31100000, %l0, %g7 ! bits [21:18] select way
280	add %g7,L2_BANK_ADDR,%g7
281	ldx [%g7], %l3
282	membar #Sync
283	cyc_nop_0:
284	setx 0x1111111111111110, %g7, %o0
285	setx 0x2222222222222220, %g7, %o1
286	setx 0x3333333333333330, %g7, %o2
287	setx 0x4444444444444440, %g7, %o3
288	setx 0x5555555555555550, %g7, %o4
289	setx 0x6666666666666660, %g7, %o5
290	setx 0x8888888888888880, %g7, %o6
291	setx 0x9999999999999990, %g7, %o7
292
293	clr %o1
294	clr %o2
295	clr %o3
296	clr %o4
297	clr %o5
298	clr %o5
299	clr %o6
300	clr %o7
301
302
303	clear_dac_mec:
304	setx DRAM_ERR_STAT_REG, %l0, %g5
305	setx 0x6000000000000000, %l0, %l1
306	stx %l1, [%g5]
307	setx L2_ERR_STAT_REG, %l0, %g5
308	setx 0x4000041000000000, %l0, %l1
309	stx %l1, [%g5]
310
311
312	check_mcu_esr:
313	mov 0x1, %l1
314	sllx %l1, DRAM_ES_FBU, %l4
315	sllx %l1, DRAM_ES_DAU, %l2
316	or %l2,%l4,%l3
317	sllx %l1, DRAM_ES_MEU, %l5
318	or %l5,%l3,%l6
319
320
321	setx DRAM_ERR_STAT_REG, %l3, %g5
322	ldx [%g5], %l1
323
324	subcc %l1, %l6, %i4
325	brnz %i4, test_fail
326	nop
327
328	read_fbd_err_synd_reg:
329	setx DRAM_FBD_ERR_SYND_REG_PA, %l7, %o2
330	ldx [%o2], %g1
331
332	setx 0x8000000000000000, %l7, %o3
333	set 0x1, %o4
334	sll %o4, FBSYND, %o5
335	or %o3, %o5, %g2
336
337	and %g1, %g2, %g3
338	subcc %g2, %g3, %g4
339	brnz %g4, test_fail
340	nop
341
342	check_L2_ESR_0:
343	setx L2_ERR_STAT_REG, %l3, %g5
344	ldx [%g5], %l6
345
346	setx 0xfffffffff0000000, %l3, %l0
347	andcc %l0, %l6, %l5 ! Donot check L2ESR SYND bits
348
349	mov 0x1, %l1
350	sllx %l1, L2ES_DAU, %l0
351	sllx %l1, L2ES_VEU, %l3
352	or %l0, %l3, %l4
353	sllx %l1, L2ES_MEU, %l7
354	or %l4, %l7, %l2
355
356	subcc %l5, %l2, %o5
357	brnz %o5, test_fail
358	nop
359
360
361
362
363	ba test_pass
364	nop
365
366	/******************************************************
367	* Exit code
368	*******************************************************/
369
370	test_pass:
371	ta T_GOOD_TRAP
372
373
374	test_fail:
375	ta T_BAD_TRAP
376
377
378
379
380
381
382
383