projects / OpenSPARC-T2-DV / blame
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|---|---|---|
| 86530b38 AT |
1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== | |
| 3 | * | |
| 4 | * OpenSPARC T2 Processor File: n2_err_mcu_csrs.s | |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 7 | * | |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 9 | * | |
| 10 | * This program is free software; you can redistribute it and/or modify | |
| 11 | * it under the terms of the GNU General Public License as published by | |
| 12 | * the Free Software Foundation; version 2 of the License. | |
| 13 | * | |
| 14 | * This program is distributed in the hope that it will be useful, | |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 17 | * GNU General Public License for more details. | |
| 18 | * | |
| 19 | * You should have received a copy of the GNU General Public License | |
| 20 | * along with this program; if not, write to the Free Software | |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 22 | * | |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license | |
| 24 | * choice is available it will apply instead, Sun elects to use only | |
| 25 | * the General Public License version 2 (GPLv2) at this time for any | |
| 26 | * software where a choice of GPL license versions is made | |
| 27 | * available with the language indicating that GPLv2 or any later version | |
| 28 | * may be used, or where a choice of which version of the GPL is applied is | |
| 29 | * otherwise unspecified. | |
| 30 | * | |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
| 33 | * have any questions. | |
| 34 | * | |
| 35 | * | |
| 36 | * ========== Copyright Header End ============================================ | |
| 37 | */ | |
| 38 | #define MAIN_PAGE_NUCLEUS_ALSO | |
| 39 | #define MAIN_PAGE_HV_ALSO | |
| 40 | ||
| 41 | ||
| 42 | #define DRAM_ERR_STAT_REG0 0x8400000280 | |
| 43 | #define DRAM_ERR_ADDR_REG0 0x8400000288 | |
| 44 | #define DRAM_ERR_INJ_REG0 0x8400000290 | |
| 45 | #define DRAM_ERR_CNT_REG0 0x8400000298 | |
| 46 | /** | |
| 47 | !#define DRAM_ERR_FBD_REG0 0x84000002a8 | |
| 48 | !changed in PRM v 0.9 | |
| 49 | **/ | |
| 50 | ||
| 51 | #define DRAM_ERR_FBD_REG0 0x8400000c00 | |
| 52 | #define DRAM_ERR_LOC_REG0 0x84000002a0 | |
| 53 | ||
| 54 | ||
| 55 | ||
| 56 | #include "hboot.s" | |
| 57 | #include "asi_s.h" | |
| 58 | #include "err_defines.h" | |
| 59 | ||
| 60 | ||
| 61 | .text | |
| 62 | .global main | |
| 63 | ||
| 64 | ||
| 65 | main: | |
| 66 | ta T_CHANGE_HPRIV | |
| 67 | ||
| 68 | DRAM_stat_0: | |
| 69 | setx 0xffffffffffffffff, %l0, %g7 | |
| 70 | setx DRAM_ERR_STAT_REG0, %l3, %g5 | |
| 71 | ||
| 72 | stx %g7, [%g5] | |
| 73 | ldx [%g5], %i0 | |
| 74 | ||
| 75 | setx 0xffff, %12, %o0 ! <15:0> = Address -> (RW) | |
| 76 | cmp %i0, %o0 | |
| 77 | bne %xcc, test_fail | |
| 78 | nop | |
| 79 | ||
| 80 | ||
| 81 | ||
| 82 | DRAM_err_addr_reg_0: | |
| 83 | setx DRAM_ERR_ADDR_REG0, %l3, %g5 | |
| 84 | ||
| 85 | ldx [%g5], %i1 | |
| 86 | ||
| 87 | stx %g7, [%g5] | |
| 88 | ldx [%g5], %i2 | |
| 89 | ||
| 90 | stx %i1, [%g5] ! store back original value | |
| 91 | ||
| 92 | setx 0xfffffffff0, %l3, %o2 ! <39:4> = Address -> (RW) | |
| 93 | cmp %i2, %o2 | |
| 94 | bne %xcc, test_fail | |
| 95 | nop | |
| 96 | ||
| 97 | ||
| 98 | DRAM_inj_0: | |
| 99 | setx DRAM_ERR_INJ_REG0, %l3, %g5 | |
| 100 | ||
| 101 | ldx [%g5], %i1 | |
| 102 | ||
| 103 | stx %g7, [%g5] | |
| 104 | ldx [%g5], %i3 | |
| 105 | ||
| 106 | stx %i1, [%g5] ! store back original value | |
| 107 | ||
| 108 | setx 0xc000ffff, %13, %o3 ! <15:0> , <31:30> = Address -> (RW) | |
| 109 | cmp %i3, %o3 | |
| 110 | bne %xcc, test_fail | |
| 111 | nop | |
| 112 | ||
| 113 | ||
| 114 | DRAM_fbd_0: | |
| 115 | setx DRAM_ERR_FBD_REG0, %l3, %g5 | |
| 116 | ||
| 117 | ldx [%g5], %i1 | |
| 118 | ||
| 119 | stx %g7, [%g5] | |
| 120 | ldx [%g5], %i4 | |
| 121 | ||
| 122 | stx %i1, [%g5] ! store back original value | |
| 123 | ||
| 124 | setx 0x800000003fffffff, %13, %o4 ! <2:0> , [63] = Address -> (RW) | |
| 125 | cmp %i4, %o4 | |
| 126 | bne %xcc, test_fail | |
| 127 | nop | |
| 128 | ||
| 129 | ||
| 130 | DRAM_cnt_0: | |
| 131 | setx DRAM_ERR_CNT_REG0, %l3, %g5 | |
| 132 | ||
| 133 | ldx [%g5], %i1 | |
| 134 | ||
| 135 | stx %g7, [%g5] | |
| 136 | ldx [%g5], %i5 | |
| 137 | ||
| 138 | stx %i1, [%g5] ! store back original value | |
| 139 | ||
| 140 | setx 0xffff, %13, %o5 ! <15:0> = Address -> (RW) | |
| 141 | cmp %i5, %o5 | |
| 142 | bne %xcc, test_fail | |
| 143 | nop | |
| 144 | ||
| 145 | DRAM_loc_0: | |
| 146 | setx DRAM_ERR_LOC_REG0, %l3, %g5 | |
| 147 | ||
| 148 | ldx [%g5], %i1 | |
| 149 | ||
| 150 | stx %g7, [%g5] | |
| 151 | ldx [%g5], %i6 | |
| 152 | ||
| 153 | stx %i1, [%g5] ! store back original value | |
| 154 | ||
| 155 | setx 0xfffffffff, %13, %o6 ! <35:0> = Address -> (RW) | |
| 156 | cmp %i6, %o6 | |
| 157 | bne %xcc, test_fail | |
| 158 | nop | |
| 159 | ||
| 160 | ba test_pass | |
| 161 | nop | |
| 162 | ||
| 163 | ||
| 164 | /****************************************************** | |
| 165 | * Exit code | |
| 166 | *******************************************************/ | |
| 167 | ||
| 168 | test_pass: | |
| 169 | ta T_GOOD_TRAP | |
| 170 | ||
| 171 | ||
| 172 | test_fail: | |
| 173 | ta T_BAD_TRAP | |
| 174 | ||
| 175 |