[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / mcu / n2_err_mcu_int.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: n2_err_mcu_int.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO

#define CMP_FBD_SYND 0x0

#include "hboot.s"
#include "asi_s.h"

#define L20 0x0000134000
#define L21 0x0000134040

#define L22 0x0000134080
#define L23 0x00001340c0

#define L24 0x0000134100
#define L25 0x0000134140

#define L26 0x0000134180
#define L27 0x00001341c0

#ifdef MCU0
#define	DRAM_FBR_CNT_REG_PA		DRAM_FBR_CNT_REG_PA_0
#define DRAM_ERR_CNT_REG_PA     	DRAM_ERR_CNT_REG_PA_0

#define DRAM_FBD_ERR_SYND_REG_PA        DRAM_FBD_ERR_SYND_REG_PA_0
#define DRAM_FBD_INJ_ERR_SRC_REG_PA     DRAM_FBD_INJ_ERR_SRC_REG_PA_0

#define  DRAM_ERR_INJ_REG   		0x8400000290
#define  DRAM_ERR_STAT_REG  		0x8400000280
#define  L2_ERR_STAT_REG    		0xAB00000000
#define  L2_ERR_ADDR_REG    		0xAC00000000
#endif

#ifdef MCU1
#define DRAM_FBR_CNT_REG_PA     	DRAM_FBR_CNT_REG_PA_1
#define DRAM_ERR_CNT_REG_PA     	DRAM_ERR_CNT_REG_PA_1

#define DRAM_FBD_ERR_SYND_REG_PA        DRAM_FBD_ERR_SYND_REG_PA_1
#define DRAM_FBD_INJ_ERR_SRC_REG_PA     DRAM_FBD_INJ_ERR_SRC_REG_PA_1

#define  DRAM_ERR_INJ_REG   		0x8400001290
#define  DRAM_ERR_STAT_REG  		0x8400001280
#define  L2_ERR_STAT_REG    		0xAB00000080
#define  L2_ERR_ADDR_REG    		0xAC00000080
#endif

#ifdef MCU2
#define DRAM_FBR_CNT_REG_PA     	DRAM_FBR_CNT_REG_PA_2
#define DRAM_ERR_CNT_REG_PA     	DRAM_ERR_CNT_REG_PA_2

#define DRAM_FBD_ERR_SYND_REG_PA        DRAM_FBD_ERR_SYND_REG_PA_2
#define DRAM_FBD_INJ_ERR_SRC_REG_PA     DRAM_FBD_INJ_ERR_SRC_REG_PA_2

#define  DRAM_ERR_INJ_REG   		0x8400002290
#define  DRAM_ERR_STAT_REG  		0x8400002280
#define  L2_ERR_STAT_REG    		0xAB00000100
#define  L2_ERR_ADDR_REG    		0xAC00000100
#endif

#ifdef MCU3
#define DRAM_FBR_CNT_REG_PA     	DRAM_FBR_CNT_REG_PA_3
#define	DRAM_ERR_CNT_REG_PA		DRAM_ERR_CNT_REG_PA_3

#define DRAM_FBD_ERR_SYND_REG_PA	DRAM_FBD_ERR_SYND_REG_PA_3
#define DRAM_FBD_INJ_ERR_SRC_REG_PA 	DRAM_FBD_INJ_ERR_SRC_REG_PA_3


#define  DRAM_ERR_INJ_REG   		0x8400003290
#define  DRAM_ERR_STAT_REG  		0x8400003280
#define  L2_ERR_STAT_REG    		0xAB00000180
#define  L2_ERR_ADDR_REG    		0xAC00000180
#endif

#ifdef ECC 
#define CMP_ECC_CNT	0x0
#else
#define CMP_ECC_CNT     0x1
#endif

#ifdef L2_OFF
#define L2_ON_OFF_DM	0x1
#else
#define L2_ON_OFF_DM    0x0
#endif
 
.text
.global	 main

main:
  ta	  T_CHANGE_HPRIV


L2_on_off_dm:
        setx  L2CS_PA0, %l6, %g1
	ldx   [%g1], %o1

	setx  0xfffffffffffffffc, %l6, %i1	! <1:0>=00
	and   %i1, %o1, %o2
	
        mov   L2_ON_OFF_DM, %l0
	or    %o2, %l0, %l1

        stx   %l1, [%g1]

	nop
	membar #Sync

write_mcu_fbr_count_reg:
	set	0x10000, %g6		!<16>=countone=1
	setx	DRAM_FBR_CNT_REG_PA, %l7, %o2
	stx     %g6, [%o2]
	ldx     [%o2], %i1


set_error_count_reg:
        set     0x1, %g6            !<16>=countone=1
        setx    DRAM_ERR_CNT_REG_PA, %l7, %o2
        stx     %g6, [%o2]

clear_soc_esr:
        setx    SOC_ESR_REG, %l7, %g5
        stx     %g0, [%g5]

clear_l2_esr:
        setx    L2_ERR_STAT_REG, %l7, %g5
        stx     %g0, [%g5]

clear_mcu_esr:
        setx    DRAM_ERR_STAT_REG, %l7, %g5
        stx     %g0, [%g5]

clear_l2_ear_0:
        setx    L2_ERR_ADDR_REG, %l7, %g5
        stx     %g0, [%g5]

clear_fbd_err_synd:
        setx    DRAM_FBD_ERR_SYND_REG_PA, %l7, %g5
        stx     %g0, [%g5]


#ifdef FBR
set_inj_err_src_reg:
	set	INJ_ERR_SRC, %g1
	setx	DRAM_FBD_INJ_ERR_SRC_REG_PA, %l7, %g3
	stx	%g1, [%g3]
	nop; nop; nop; nop
        nop; nop; nop; nop
	nop; nop; nop; nop
	nop; nop; nop; nop
	nop; nop; nop; nop
	nop; nop; nop; nop
	nop; nop; nop; nop
	nop; nop; nop; nop
	nop; nop; nop; nop
	ldx	[%g3], %g7
	nop; nop; nop; nop
        nop; nop; nop; nop
        nop; nop; nop; nop
        nop; nop; nop; nop
        nop; nop; nop; nop
        nop; nop; nop; nop
        nop; nop; nop; nop
        nop; nop; nop; nop
        nop; nop; nop; nop
        nop; nop; nop; nop
        nop; nop; nop; nop
        nop; nop; nop; nop
        nop; nop; nop; nop
	membar 0x40
#endif

set_ejr:
        set     0x1, %g1
        sllx    %g1, ERR_FIELD, %g2
        setx    SOC_EJR_REG, %l7, %g3
        stx     %g2, [%g3]
        membar 0x40

L2_Init:
        setx	0x1111111111111110, %g7, %o0
	setx	0x2222222222222220, %g7, %o1
	setx	0x3333333333333330, %g7, %o2
	setx	0x4444444444444440, %g7, %o3
	setx	0x5555555555555550, %g7, %o4
	setx	0x6666666666666660, %g7, %o5
	setx	0x8888888888888880, %g7, %o6
	setx	0x9999999999999990, %g7, %o7

	setx	L20, %g7, %l0
	setx	L21, %g7, %l1

	setx	L22, %g7, %l2
	setx	L23, %g7, %l3

	setx	L24, %g7, %l4
	setx	L25, %g7, %l5

	setx	L26, %g7, %l6
	setx	L27, %g7, %l7

L2_0:
     	stx	%o0, [%l0]
	ldx	[%l0], %g1

L2_1:
     	stx	%o1, [%l1]
	ldx	[%l1], %g1

L2_2:
     	stx	%o2, [%l2]
	ldx	[%l2], %g1

L2_3:
     	stx	%o3, [%l3]
	ldx	[%l3], %g1

L2_4:
     	stx	%o4, [%l4]
	ldx	[%l4], %g1

L2_5:
     	stx	%o5, [%l5]
	ldx	[%l5], %g1

L2_6:
     	stx	%o6, [%l6]
	ldx	[%l6], %g1

L2_7:
     	stx	%o7, [%l7]
	ldx	[%l7], %g1

	membar 0x40

next_line:
	add	%l0, 0x40, %l0
        add     %l1, 0x40, %l1
        add     %l2, 0x40, %l2
        add     %l3, 0x40, %l3
        add     %l4, 0x40, %l4
        add     %l5, 0x40, %l5
        add     %l6, 0x40, %l6
        add     %l7, 0x40, %l7

L2_4_again:
                stx     %o4, [%l4]
        ldx     [%l4], %g1

L2_5_again:
                stx     %o5, [%l5]
        ldx     [%l5], %g1

L2_6_again:
                stx     %o6, [%l6]
        ldx     [%l6], %g1

L2_7_again:
        stx     %o7, [%l7]
        ldx     [%l7], %g1

L2_0_again:
     	stx	%o0, [%l0]
	ldx	[%l0], %g1

L2_1_again:
        stx	%o1, [%l1]
	ldx	[%l1], %g1

L2_2_again:
     	stx	%o2, [%l2]
	ldx	[%l2], %g1

L2_3_again:
	stx	%o3, [%l3]
	ldx	[%l3], %g1


	membar 0x40

read_ncu_esr:
        setx    SOC_ESR_REG, %l7, %g5
        ldx     [%g5], %i1
	nop
        setx    0x8000000000000000, %l7, %g7    !valid bit
        set     0x1, %g1
        sllx    %g1, ERR_FIELD, %g2     
        or      %g7, %g2, %i3      
        sub     %i1, %i3, %i4
        brnz    %i4, test_fail
        nop

#ifdef ECC 
check_mcu_esr:
	mov   	0x1, %l1
	sllx  	%l1, DRAM_ES_DAC, %g2

/*
	mov	0x1, %l1
	sllx	%l1, DRAM_ES_MEC, %l2

	or	%l0, %l2, %l6
*/	
!	set   	0x2000, %l3      ! 16-bit Syndrome - for SECC, it's the mask nibble-reversed
!	or    	%l0, %l3, %l0            ! %l0 has expected value

	setx  	DRAM_ERR_STAT_REG, %l3, %g5  
	ldx   	[%g5], %l1

        setx  	0xbfffffffffff0000, %l3, %l0
        andcc 	%l0, %l1, %l5                   ! Donot check L2ESR SYND bits and MEC

        subcc	%l5, %g2, %i4
        brnz    %i4, test_fail
        nop

check_L2_ESR_0:
	setx  	L2_ERR_STAT_REG, %l3, %g5  
	ldx   	[%g5], %l6

	setx  	0xbffffffff0000000, %l3, %l0
	andcc 	%l0, %l6, %l5                   ! Donot check L2ESR SYND and MEC bits

	mov   	0x1, %l1
	sllx  	%l1, L2ES_DAC, %l0

	mov   	0x1, %l1
	sllx  	%l1, L2ES_VEC, %l2

        or    	%l0, %l2, %i4

/*
        mov   	0x1, %l1
        sllx  	%l1, L2ES_MEC, %i3

	or    	%i3, %i4, %i5
*/
	subcc	%l5, %i4, %o5
	brnz	%o5, test_fail
	nop


ch_L2_addr:
	setx  	L2_ERR_ADDR_REG, %l3, %g5  
	ldx   	[%g5], %l1
	membar 	0x40

#endif

#ifdef FBR 
check_mcu_esr:
        mov     0x1, %l1
        sllx    %l1, DRAM_ES_FBR, %l6

        setx    DRAM_ERR_STAT_REG, %l3, %g5  
        ldx     [%g5], %l1

        setx    0xbfffffffffff0000, %l3, %l0
        andcc   %l0, %l1, %l5                   ! Donot check SYND bits and MEC

        subcc   %l5, %l6, %i4
        brnz    %i4, test_fail
        nop

read_fbd_err_synd_reg:
        setx    DRAM_FBD_ERR_SYND_REG_PA, %l7, %o2
        ldx     [%o2], %g1

        setx    0x8000000000000000, %l7, %o3
        set     0x1, %o4
        sll     %o4, FBSYND, %o5
        or      %o3, %o5, %g2

        and     %g1, %g2, %g3
        subcc   %g2, %g3, %g4
        brnz    %g4, test_fail
        nop

#endif


check_fbr_cnt_reg:
        setx    DRAM_FBR_CNT_REG_PA, %l7, %o2
	ldx	[%o2], %g1
        set     0x10000, %g6            !<16>=countone=1
	subcc   %g1, %g6, %i4
        brnz    %i4, test_fail
        nop


check_err_cnt_reg:
        setx    DRAM_ERR_CNT_REG_PA, %l7, %o2
        ldx     [%o2], %g1
	set	CMP_ECC_CNT, %i1
        subcc   %g1, %i1, %i4
        brnz    %i4, test_fail
        nop


	nop

/******************************************************
 * Exit code
 *******************************************************/

test_pass:
ta  T_GOOD_TRAP


test_fail:
ta  T_BAD_TRAP
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: n2_err_mcu_int.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define MAIN_PAGE_NUCLEUS_ALSO
	39	#define MAIN_PAGE_HV_ALSO
	40
	41	#define CMP_FBD_SYND 0x0
	42
	43	#include "hboot.s"
	44	#include "asi_s.h"
	45
	46	#define L20 0x0000134000
	47	#define L21 0x0000134040
	48
	49	#define L22 0x0000134080
	50	#define L23 0x00001340c0
	51
	52	#define L24 0x0000134100
	53	#define L25 0x0000134140
	54
	55	#define L26 0x0000134180
	56	#define L27 0x00001341c0
	57
	58	#ifdef MCU0
	59	#define DRAM_FBR_CNT_REG_PA DRAM_FBR_CNT_REG_PA_0
	60	#define DRAM_ERR_CNT_REG_PA DRAM_ERR_CNT_REG_PA_0
	61
	62	#define DRAM_FBD_ERR_SYND_REG_PA DRAM_FBD_ERR_SYND_REG_PA_0
	63	#define DRAM_FBD_INJ_ERR_SRC_REG_PA DRAM_FBD_INJ_ERR_SRC_REG_PA_0
	64
65	#define DRAM_ERR_INJ_REG 0x8400000290
66	#define DRAM_ERR_STAT_REG 0x8400000280
67	#define L2_ERR_STAT_REG 0xAB00000000
68	#define L2_ERR_ADDR_REG 0xAC00000000
69	#endif
70
71	#ifdef MCU1
72	#define DRAM_FBR_CNT_REG_PA DRAM_FBR_CNT_REG_PA_1
73	#define DRAM_ERR_CNT_REG_PA DRAM_ERR_CNT_REG_PA_1
74
75	#define DRAM_FBD_ERR_SYND_REG_PA DRAM_FBD_ERR_SYND_REG_PA_1
76	#define DRAM_FBD_INJ_ERR_SRC_REG_PA DRAM_FBD_INJ_ERR_SRC_REG_PA_1
77
78	#define DRAM_ERR_INJ_REG 0x8400001290
79	#define DRAM_ERR_STAT_REG 0x8400001280
80	#define L2_ERR_STAT_REG 0xAB00000080
81	#define L2_ERR_ADDR_REG 0xAC00000080
82	#endif
83
84	#ifdef MCU2
85	#define DRAM_FBR_CNT_REG_PA DRAM_FBR_CNT_REG_PA_2
86	#define DRAM_ERR_CNT_REG_PA DRAM_ERR_CNT_REG_PA_2
87
88	#define DRAM_FBD_ERR_SYND_REG_PA DRAM_FBD_ERR_SYND_REG_PA_2
89	#define DRAM_FBD_INJ_ERR_SRC_REG_PA DRAM_FBD_INJ_ERR_SRC_REG_PA_2
90
91	#define DRAM_ERR_INJ_REG 0x8400002290
92	#define DRAM_ERR_STAT_REG 0x8400002280
93	#define L2_ERR_STAT_REG 0xAB00000100
94	#define L2_ERR_ADDR_REG 0xAC00000100
95	#endif
96
97	#ifdef MCU3
98	#define DRAM_FBR_CNT_REG_PA DRAM_FBR_CNT_REG_PA_3
99	#define DRAM_ERR_CNT_REG_PA DRAM_ERR_CNT_REG_PA_3
100
101	#define DRAM_FBD_ERR_SYND_REG_PA DRAM_FBD_ERR_SYND_REG_PA_3
102	#define DRAM_FBD_INJ_ERR_SRC_REG_PA DRAM_FBD_INJ_ERR_SRC_REG_PA_3
103
104
105	#define DRAM_ERR_INJ_REG 0x8400003290
106	#define DRAM_ERR_STAT_REG 0x8400003280
107	#define L2_ERR_STAT_REG 0xAB00000180
108	#define L2_ERR_ADDR_REG 0xAC00000180
109	#endif
110
111	#ifdef ECC
112	#define CMP_ECC_CNT 0x0
113	#else
114	#define CMP_ECC_CNT 0x1
115	#endif
116
117	#ifdef L2_OFF
118	#define L2_ON_OFF_DM 0x1
119	#else
120	#define L2_ON_OFF_DM 0x0
121	#endif
122
123	.text
124	.global main
125
126	main:
127	ta T_CHANGE_HPRIV
128
129
130	L2_on_off_dm:
131	setx L2CS_PA0, %l6, %g1
132	ldx [%g1], %o1
133
134	setx 0xfffffffffffffffc, %l6, %i1 ! <1:0>=00
135	and %i1, %o1, %o2
136
137	mov L2_ON_OFF_DM, %l0
138	or %o2, %l0, %l1
139
140	stx %l1, [%g1]
141
142	nop
143	membar #Sync
144
145	write_mcu_fbr_count_reg:
146	set 0x10000, %g6 !<16>=countone=1
147	setx DRAM_FBR_CNT_REG_PA, %l7, %o2
148	stx %g6, [%o2]
149	ldx [%o2], %i1
150
151
152	set_error_count_reg:
153	set 0x1, %g6 !<16>=countone=1
154	setx DRAM_ERR_CNT_REG_PA, %l7, %o2
155	stx %g6, [%o2]
156
157	clear_soc_esr:
158	setx SOC_ESR_REG, %l7, %g5
159	stx %g0, [%g5]
160
161	clear_l2_esr:
162	setx L2_ERR_STAT_REG, %l7, %g5
163	stx %g0, [%g5]
164
165	clear_mcu_esr:
166	setx DRAM_ERR_STAT_REG, %l7, %g5
167	stx %g0, [%g5]
168
169	clear_l2_ear_0:
170	setx L2_ERR_ADDR_REG, %l7, %g5
171	stx %g0, [%g5]
172
173	clear_fbd_err_synd:
174	setx DRAM_FBD_ERR_SYND_REG_PA, %l7, %g5
175	stx %g0, [%g5]
176
177
178	#ifdef FBR
179	set_inj_err_src_reg:
180	set INJ_ERR_SRC, %g1
181	setx DRAM_FBD_INJ_ERR_SRC_REG_PA, %l7, %g3
182	stx %g1, [%g3]
183	nop; nop; nop; nop
184	nop; nop; nop; nop
185	nop; nop; nop; nop
186	nop; nop; nop; nop
187	nop; nop; nop; nop
188	nop; nop; nop; nop
189	nop; nop; nop; nop
190	nop; nop; nop; nop
191	nop; nop; nop; nop
192	ldx [%g3], %g7
193	nop; nop; nop; nop
194	nop; nop; nop; nop
195	nop; nop; nop; nop
196	nop; nop; nop; nop
197	nop; nop; nop; nop
198	nop; nop; nop; nop
199	nop; nop; nop; nop
200	nop; nop; nop; nop
201	nop; nop; nop; nop
202	nop; nop; nop; nop
203	nop; nop; nop; nop
204	nop; nop; nop; nop
205	nop; nop; nop; nop
206	membar 0x40
207	#endif
208
209	set_ejr:
210	set 0x1, %g1
211	sllx %g1, ERR_FIELD, %g2
212	setx SOC_EJR_REG, %l7, %g3
213	stx %g2, [%g3]
214	membar 0x40
215
216	L2_Init:
217	setx 0x1111111111111110, %g7, %o0
218	setx 0x2222222222222220, %g7, %o1
219	setx 0x3333333333333330, %g7, %o2
220	setx 0x4444444444444440, %g7, %o3
221	setx 0x5555555555555550, %g7, %o4
222	setx 0x6666666666666660, %g7, %o5
223	setx 0x8888888888888880, %g7, %o6
224	setx 0x9999999999999990, %g7, %o7
225
226	setx L20, %g7, %l0
227	setx L21, %g7, %l1
228
229	setx L22, %g7, %l2
230	setx L23, %g7, %l3
231
232	setx L24, %g7, %l4
233	setx L25, %g7, %l5
234
235	setx L26, %g7, %l6
236	setx L27, %g7, %l7
237
238	L2_0:
239	stx %o0, [%l0]
240	ldx [%l0], %g1
241
242	L2_1:
243	stx %o1, [%l1]
244	ldx [%l1], %g1
245
246	L2_2:
247	stx %o2, [%l2]
248	ldx [%l2], %g1
249
250	L2_3:
251	stx %o3, [%l3]
252	ldx [%l3], %g1
253
254	L2_4:
255	stx %o4, [%l4]
256	ldx [%l4], %g1
257
258	L2_5:
259	stx %o5, [%l5]
260	ldx [%l5], %g1
261
262	L2_6:
263	stx %o6, [%l6]
264	ldx [%l6], %g1
265
266	L2_7:
267	stx %o7, [%l7]
268	ldx [%l7], %g1
269
270	membar 0x40
271
272	next_line:
273	add %l0, 0x40, %l0
274	add %l1, 0x40, %l1
275	add %l2, 0x40, %l2
276	add %l3, 0x40, %l3
277	add %l4, 0x40, %l4
278	add %l5, 0x40, %l5
279	add %l6, 0x40, %l6
280	add %l7, 0x40, %l7
281
282	L2_4_again:
283	stx %o4, [%l4]
284	ldx [%l4], %g1
285
286	L2_5_again:
287	stx %o5, [%l5]
288	ldx [%l5], %g1
289
290	L2_6_again:
291	stx %o6, [%l6]
292	ldx [%l6], %g1
293
294	L2_7_again:
295	stx %o7, [%l7]
296	ldx [%l7], %g1
297
298	L2_0_again:
299	stx %o0, [%l0]
300	ldx [%l0], %g1
301
302	L2_1_again:
303	stx %o1, [%l1]
304	ldx [%l1], %g1
305
306	L2_2_again:
307	stx %o2, [%l2]
308	ldx [%l2], %g1
309
310	L2_3_again:
311	stx %o3, [%l3]
312	ldx [%l3], %g1
313
314
315	membar 0x40
316
317	read_ncu_esr:
318	setx SOC_ESR_REG, %l7, %g5
319	ldx [%g5], %i1
320	nop
321	setx 0x8000000000000000, %l7, %g7 !valid bit
322	set 0x1, %g1
323	sllx %g1, ERR_FIELD, %g2
324	or %g7, %g2, %i3
325	sub %i1, %i3, %i4
326	brnz %i4, test_fail
327	nop
328
329	#ifdef ECC
330	check_mcu_esr:
331	mov 0x1, %l1
332	sllx %l1, DRAM_ES_DAC, %g2
333
334	/*
335	mov 0x1, %l1
336	sllx %l1, DRAM_ES_MEC, %l2
337
338	or %l0, %l2, %l6
339	*/
340	! set 0x2000, %l3 ! 16-bit Syndrome - for SECC, it's the mask nibble-reversed
341	! or %l0, %l3, %l0 ! %l0 has expected value
342
343	setx DRAM_ERR_STAT_REG, %l3, %g5
344	ldx [%g5], %l1
345
346	setx 0xbfffffffffff0000, %l3, %l0
347	andcc %l0, %l1, %l5 ! Donot check L2ESR SYND bits and MEC
348
349	subcc %l5, %g2, %i4
350	brnz %i4, test_fail
351	nop
352
353	check_L2_ESR_0:
354	setx L2_ERR_STAT_REG, %l3, %g5
355	ldx [%g5], %l6
356
357	setx 0xbffffffff0000000, %l3, %l0
358	andcc %l0, %l6, %l5 ! Donot check L2ESR SYND and MEC bits
359
360	mov 0x1, %l1
361	sllx %l1, L2ES_DAC, %l0
362
363	mov 0x1, %l1
364	sllx %l1, L2ES_VEC, %l2
365
366	or %l0, %l2, %i4
367
368	/*
369	mov 0x1, %l1
370	sllx %l1, L2ES_MEC, %i3
371
372	or %i3, %i4, %i5
373	*/
374	subcc %l5, %i4, %o5
375	brnz %o5, test_fail
376	nop
377
378
379	ch_L2_addr:
380	setx L2_ERR_ADDR_REG, %l3, %g5
381	ldx [%g5], %l1
382	membar 0x40
383
384	#endif
385
386	#ifdef FBR
387	check_mcu_esr:
388	mov 0x1, %l1
389	sllx %l1, DRAM_ES_FBR, %l6
390
391	setx DRAM_ERR_STAT_REG, %l3, %g5
392	ldx [%g5], %l1
393
394	setx 0xbfffffffffff0000, %l3, %l0
395	andcc %l0, %l1, %l5 ! Donot check SYND bits and MEC
396
397	subcc %l5, %l6, %i4
398	brnz %i4, test_fail
399	nop
400
401	read_fbd_err_synd_reg:
402	setx DRAM_FBD_ERR_SYND_REG_PA, %l7, %o2
403	ldx [%o2], %g1
404
405	setx 0x8000000000000000, %l7, %o3
406	set 0x1, %o4
407	sll %o4, FBSYND, %o5
408	or %o3, %o5, %g2
409
410	and %g1, %g2, %g3
411	subcc %g2, %g3, %g4
412	brnz %g4, test_fail
413	nop
414
415	#endif
416
417
418	check_fbr_cnt_reg:
419	setx DRAM_FBR_CNT_REG_PA, %l7, %o2
420	ldx [%o2], %g1
421	set 0x10000, %g6 !<16>=countone=1
422	subcc %g1, %g6, %i4
423	brnz %i4, test_fail
424	nop
425
426
427	check_err_cnt_reg:
428	setx DRAM_ERR_CNT_REG_PA, %l7, %o2
429	ldx [%o2], %g1
430	set CMP_ECC_CNT, %i1
431	subcc %g1, %i1, %i4
432	brnz %i4, test_fail
433	nop
434
435
436
437	nop
438
439	/******************************************************
440	* Exit code
441	*******************************************************/
442
443	test_pass:
444	ta T_GOOD_TRAP
445
446
447	test_fail:
448	ta T_BAD_TRAP
449
450
451