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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: n2_err_mcu_int_fbu.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define MAIN_PAGE_NUCLEUS_ALSO | |
39 | #define MAIN_PAGE_HV_ALSO | |
40 | ||
41 | #define CMP_FBD_SYND 0x0 | |
42 | ||
43 | #include "hboot.s" | |
44 | #include "asi_s.h" | |
45 | ||
46 | #define L20 0x0004100000 | |
47 | #define L21 0x0004100040 | |
48 | ||
49 | #define L22 0x0004100080 | |
50 | #define L23 0x00041000c0 | |
51 | ||
52 | #define L24 0x0000134100 | |
53 | #define L25 0x0000134140 | |
54 | ||
55 | #define L26 0x0000134180 | |
56 | #define L27 0x00001341c0 | |
57 | ||
58 | #ifdef MCU0 | |
59 | #define DRAM_FBR_CNT_REG_PA DRAM_FBR_CNT_REG_PA_0 | |
60 | #define DRAM_ERR_CNT_REG_PA DRAM_ERR_CNT_REG_PA_0 | |
61 | ||
62 | #define DRAM_FBD_ERR_SYND_REG_PA DRAM_FBD_ERR_SYND_REG_PA_0 | |
63 | #define DRAM_FBD_INJ_ERR_SRC_REG_PA DRAM_FBD_INJ_ERR_SRC_REG_PA_0 | |
64 | ||
65 | #define DRAM_ERR_INJ_REG 0x8400000290 | |
66 | #define DRAM_ERR_STAT_REG 0x8400000280 | |
67 | #define L2_ERR_STAT_REG 0xAB00000000 | |
68 | #define L2_ERR_ADDR_REG 0xAC00000000 | |
69 | #endif | |
70 | ||
71 | #ifdef MCU1 | |
72 | #define DRAM_FBR_CNT_REG_PA DRAM_FBR_CNT_REG_PA_1 | |
73 | #define DRAM_ERR_CNT_REG_PA DRAM_ERR_CNT_REG_PA_1 | |
74 | ||
75 | #define DRAM_FBD_ERR_SYND_REG_PA DRAM_FBD_ERR_SYND_REG_PA_1 | |
76 | #define DRAM_FBD_INJ_ERR_SRC_REG_PA DRAM_FBD_INJ_ERR_SRC_REG_PA_1 | |
77 | ||
78 | #define DRAM_ERR_INJ_REG 0x8400001290 | |
79 | #define DRAM_ERR_STAT_REG 0x8400001280 | |
80 | #define L2_ERR_STAT_REG 0xAB00000080 | |
81 | #define L2_ERR_ADDR_REG 0xAC00000080 | |
82 | #endif | |
83 | ||
84 | #ifdef MCU2 | |
85 | #define DRAM_FBR_CNT_REG_PA DRAM_FBR_CNT_REG_PA_2 | |
86 | #define DRAM_ERR_CNT_REG_PA DRAM_ERR_CNT_REG_PA_2 | |
87 | ||
88 | #define DRAM_FBD_ERR_SYND_REG_PA DRAM_FBD_ERR_SYND_REG_PA_2 | |
89 | #define DRAM_FBD_INJ_ERR_SRC_REG_PA DRAM_FBD_INJ_ERR_SRC_REG_PA_2 | |
90 | ||
91 | #define DRAM_ERR_INJ_REG 0x8400002290 | |
92 | #define DRAM_ERR_STAT_REG 0x8400002280 | |
93 | #define L2_ERR_STAT_REG 0xAB00000100 | |
94 | #define L2_ERR_ADDR_REG 0xAC00000100 | |
95 | #endif | |
96 | ||
97 | #ifdef MCU3 | |
98 | #define DRAM_FBR_CNT_REG_PA DRAM_FBR_CNT_REG_PA_3 | |
99 | #define DRAM_ERR_CNT_REG_PA DRAM_ERR_CNT_REG_PA_3 | |
100 | ||
101 | #define DRAM_FBD_ERR_SYND_REG_PA DRAM_FBD_ERR_SYND_REG_PA_3 | |
102 | #define DRAM_FBD_INJ_ERR_SRC_REG_PA DRAM_FBD_INJ_ERR_SRC_REG_PA_3 | |
103 | ||
104 | ||
105 | #define DRAM_ERR_INJ_REG 0x8400003290 | |
106 | #define DRAM_ERR_STAT_REG 0x8400003280 | |
107 | #define L2_ERR_STAT_REG 0xAB00000180 | |
108 | #define L2_ERR_ADDR_REG 0xAC00000180 | |
109 | #endif | |
110 | ||
111 | #ifdef ECC | |
112 | #define CMP_ECC_CNT 0x0 | |
113 | #else | |
114 | #define CMP_ECC_CNT 0x1 | |
115 | #endif | |
116 | ||
117 | #ifdef L2_OFF | |
118 | #define L2_ON_OFF_DM 0x1 | |
119 | #else | |
120 | #define L2_ON_OFF_DM 0x0 | |
121 | #endif | |
122 | ||
123 | .text | |
124 | .global main | |
125 | ||
126 | main: | |
127 | ta T_CHANGE_HPRIV | |
128 | ||
129 | ||
130 | L2_on_off_dm: | |
131 | setx L2CS_PA0, %l6, %g1 | |
132 | ldx [%g1], %o1 | |
133 | ||
134 | setx 0xfffffffffffffffc, %l6, %i1 ! <1:0>=00 | |
135 | and %i1, %o1, %o2 | |
136 | ||
137 | mov L2_ON_OFF_DM, %l0 | |
138 | or %o2, %l0, %l1 | |
139 | ||
140 | stx %l1, [%g1] | |
141 | ||
142 | nop | |
143 | membar #Sync | |
144 | ||
145 | ||
146 | set_error_count_reg: | |
147 | set 0x1, %g6 !<16>=countone=1 | |
148 | setx DRAM_ERR_CNT_REG_PA, %l7, %o2 | |
149 | stx %g6, [%o2] | |
150 | ||
151 | clear_soc_esr: | |
152 | setx SOC_ESR_REG, %l7, %g5 | |
153 | stx %g0, [%g5] | |
154 | ||
155 | clear_l2_esr: | |
156 | setx L2_ERR_STAT_REG, %l7, %g5 | |
157 | stx %g0, [%g5] | |
158 | ||
159 | clear_mcu_esr: | |
160 | setx DRAM_ERR_STAT_REG, %l7, %g5 | |
161 | stx %g0, [%g5] | |
162 | ||
163 | clear_l2_ear_0: | |
164 | setx L2_ERR_ADDR_REG, %l7, %g5 | |
165 | stx %g0, [%g5] | |
166 | ||
167 | clear_fbd_err_synd: | |
168 | setx DRAM_FBD_ERR_SYND_REG_PA, %l7, %g5 | |
169 | stx %g0, [%g5] | |
170 | ||
171 | set_inj_err_src_reg: | |
172 | set INJ_ERR_SRC, %g1 | |
173 | setx DRAM_FBD_INJ_ERR_SRC_REG_PA, %l7, %g3 | |
174 | stx %g1, [%g3] | |
175 | membar 0x40 | |
176 | ||
177 | set_ejr: | |
178 | set 0x1, %g1 | |
179 | sllx %g1, ERR_FIELD, %g2 | |
180 | setx SOC_EJR_REG, %l7, %g3 | |
181 | stx %g2, [%g3] | |
182 | membar 0x40 | |
183 | ||
184 | setx 0x40, %l1, %g4 | |
185 | delay_loop: | |
186 | nop | |
187 | nop | |
188 | nop | |
189 | nop | |
190 | dec %g4 | |
191 | brnz %g4, delay_loop | |
192 | nop | |
193 | ||
194 | ||
195 | ||
196 | check_mcu_esr: | |
197 | mov 0x1, %l1 | |
198 | sllx %l1, DRAM_ES_FBU, %l6 | |
199 | ||
200 | setx DRAM_ERR_STAT_REG, %l3, %g5 | |
201 | ldx [%g5], %l1 | |
202 | ||
203 | setx 0xffffffffffff0000, %l3, %l0 | |
204 | andcc %l0, %l1, %l5 ! Donot check SYND bits | |
205 | ||
206 | ! subcc %l5, %l6, %i4 | |
207 | ! brnz %i4, test_fail | |
208 | nop | |
209 | ||
210 | L2_Init: | |
211 | setx 0x1111111111111110, %g7, %o0 | |
212 | setx 0x2222222222222220, %g7, %o1 | |
213 | setx 0x3333333333333330, %g7, %o2 | |
214 | setx 0x4444444444444440, %g7, %o3 | |
215 | setx 0x5555555555555550, %g7, %o4 | |
216 | setx 0x6666666666666660, %g7, %o5 | |
217 | setx 0x8888888888888880, %g7, %o6 | |
218 | setx 0x9999999999999990, %g7, %o7 | |
219 | ||
220 | setx L20, %g7, %l0 | |
221 | setx L21, %g7, %l1 | |
222 | ||
223 | dec %g1 | |
224 | cmp %g1, %g0 | |
225 | ||
226 | ||
227 | L2_0: | |
228 | stx %o0, [%l0] | |
229 | ldx [%l0], %g1 | |
230 | ||
231 | L2_1: | |
232 | stx %o1, [%l1] | |
233 | ldx [%l1], %g1 | |
234 | membar 0x40 | |
235 | ||
236 | next_line: | |
237 | add %l0, 0x40, %l0 | |
238 | add %l1, 0x40, %l1 | |
239 | ||
240 | L2_0_again: | |
241 | stx %o0, [%l0] | |
242 | ldx [%l0], %g1 | |
243 | ||
244 | L2_1_again: | |
245 | stx %o1, [%l1] | |
246 | ldx [%l1], %g1 | |
247 | membar 0x40 | |
248 | ||
249 | ||
250 | check_mcu_esr_again: | |
251 | mov 0x1, %l1 | |
252 | sllx %l1, DRAM_ES_FBU, %l6 | |
253 | ||
254 | setx DRAM_ERR_STAT_REG, %l3, %g5 | |
255 | ldx [%g5], %l1 | |
256 | ||
257 | setx 0xffffffffffff0000, %l3, %l0 | |
258 | andcc %l0, %l1, %l5 ! Donot check SYND bits | |
259 | ||
260 | ! subcc %l5, %l6, %i4 | |
261 | ! brnz %i4, test_fail | |
262 | nop | |
263 | ||
264 | read_fbd_err_synd_reg: | |
265 | setx DRAM_FBD_ERR_SYND_REG_PA, %l7, %o2 | |
266 | ldx [%o2], %g1 | |
267 | ||
268 | setx 0x8000000000000000, %l7, %o3 | |
269 | set 0x1, %o4 | |
270 | sll %o4, FBSYND, %o5 | |
271 | or %o3, %o5, %g2 | |
272 | ||
273 | and %g1, %g2, %g3 | |
274 | ! subcc %g2, %g3, %g4 | |
275 | ! brnz %g4, test_fail | |
276 | nop | |
277 | ||
278 | ||
279 | check_L2_ESR_0: | |
280 | setx L2_ERR_STAT_REG, %l3, %g5 | |
281 | ldx [%g5], %l6 | |
282 | ||
283 | setx 0xfffffffff0000000, %l3, %l0 | |
284 | andcc %l0, %l6, %l5 ! Donot check L2ESR SYND bits | |
285 | ||
286 | mov 0x1, %l1 | |
287 | sllx %l1, L2ES_DSC, %l0 | |
288 | ||
289 | mov 0x1, %l1 | |
290 | sllx %l1, L2ES_VEC, %l2 | |
291 | ||
292 | or %l0, %l2, %i4 | |
293 | ||
294 | mov 0x1, %l1 | |
295 | sllx %l1, L2ES_MEC, %i3 | |
296 | ||
297 | or %i3, %i4, %i5 | |
298 | ||
299 | ! subcc %l5, %i5, %o5 | |
300 | ! brnz %o5, test_fail | |
301 | nop | |
302 | ||
303 | /*** | |
304 | ||
305 | ||
306 | set_inj_err_src_reg_2: | |
307 | setx DRAM_FBD_INJ_ERR_SRC_REG_PA, %l7, %g3 | |
308 | stx %g0, [%g3] | |
309 | membar 0x40 | |
310 | ||
311 | setx 0x1111111111111110, %g7, %o0 | |
312 | setx 0x2222222222222220, %g7, %o1 | |
313 | ||
314 | setx L20, %g7, %l0 | |
315 | setx L21, %g7, %l1 | |
316 | ||
317 | stx %o0, [%l0+0x80] | |
318 | ldx [%l0+0x40], %g1 | |
319 | ||
320 | ||
321 | setx DRAM_ERR_STAT_REG, %l3, %g5 | |
322 | ldx [%g5], %l1 | |
323 | ||
324 | ****/ | |
325 | ||
326 | ba test_pass | |
327 | nop | |
328 | ||
329 | /****************************************************** | |
330 | * Exit code | |
331 | *******************************************************/ | |
332 | ||
333 | test_pass: | |
334 | ta T_GOOD_TRAP | |
335 | ||
336 | ||
337 | test_fail: | |
338 | ta T_BAD_TRAP | |
339 | ||
340 | ||
341 |