[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / mcu / n2_err_mcu_int_fbu_AA.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: n2_err_mcu_int_fbu_AA.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO

#define CMP_FBD_SYND 0x0

#include "hboot.s"
#include "asi_s.h"

#define L22 0x0004100080
#define L23 0x00041000c0

#define L24 0x0000134100
#define L25 0x0000134140

#define L26 0x0000134180
#define L27 0x00001341c0

#ifdef MCU0
#define	DRAM_FBR_CNT_REG_PA		DRAM_FBR_CNT_REG_PA_0
#define DRAM_ERR_CNT_REG_PA     	DRAM_ERR_CNT_REG_PA_0

#define DRAM_FBD_ERR_SYND_REG_PA        DRAM_FBD_ERR_SYND_REG_PA_0
#define DRAM_FBD_INJ_ERR_SRC_REG_PA     DRAM_FBD_INJ_ERR_SRC_REG_PA_0

#define  DRAM_ERR_INJ_REG   		0x8400000290
#define  DRAM_ERR_STAT_REG  		0x8400000280
#define  L2_ERR_STAT_REG    		0xAB00000000
#define  L2_ERR_ADDR_REG    		0xAC00000000

#define L20 				0x0004100000
#define L21 				0x0008100000
#endif

#ifdef MCU1
#define DRAM_FBR_CNT_REG_PA     	DRAM_FBR_CNT_REG_PA_1
#define DRAM_ERR_CNT_REG_PA     	DRAM_ERR_CNT_REG_PA_1

#define DRAM_FBD_ERR_SYND_REG_PA        DRAM_FBD_ERR_SYND_REG_PA_1
#define DRAM_FBD_INJ_ERR_SRC_REG_PA     DRAM_FBD_INJ_ERR_SRC_REG_PA_1

#define  DRAM_ERR_INJ_REG   		0x8400001290
#define  DRAM_ERR_STAT_REG  		0x8400001280
#define  L2_ERR_STAT_REG    		0xAB00000080
#define  L2_ERR_ADDR_REG    		0xAC00000080

#define L20    				0x0004100080
#define L21				0x0008100080
#endif

#ifdef MCU2
#define DRAM_FBR_CNT_REG_PA     	DRAM_FBR_CNT_REG_PA_2
#define DRAM_ERR_CNT_REG_PA     	DRAM_ERR_CNT_REG_PA_2

#define DRAM_FBD_ERR_SYND_REG_PA        DRAM_FBD_ERR_SYND_REG_PA_2
#define DRAM_FBD_INJ_ERR_SRC_REG_PA     DRAM_FBD_INJ_ERR_SRC_REG_PA_2

#define  DRAM_ERR_INJ_REG   		0x8400002290
#define  DRAM_ERR_STAT_REG  		0x8400002280
#define  L2_ERR_STAT_REG    		0xAB00000100
#define  L2_ERR_ADDR_REG    		0xAC00000100

#define L20                             0x0004100100
#define L21                             0x0008100100
#endif

#ifdef MCU3
#define DRAM_FBR_CNT_REG_PA     	DRAM_FBR_CNT_REG_PA_3
#define	DRAM_ERR_CNT_REG_PA		DRAM_ERR_CNT_REG_PA_3

#define DRAM_FBD_ERR_SYND_REG_PA	DRAM_FBD_ERR_SYND_REG_PA_3
#define DRAM_FBD_INJ_ERR_SRC_REG_PA 	DRAM_FBD_INJ_ERR_SRC_REG_PA_3

#define  DRAM_ERR_INJ_REG   		0x8400003290
#define  DRAM_ERR_STAT_REG  		0x8400003280
#define  L2_ERR_STAT_REG    		0xAB00000180
#define  L2_ERR_ADDR_REG    		0xAC00000180

#define L20                             0x0004100180
#define L21                             0x0008100180
#endif

#ifdef ECC 
#define CMP_ECC_CNT	0x0
#else
#define CMP_ECC_CNT     0x1
#endif

#ifdef L2_OFF
#define L2_ON_OFF_DM	0x1
#else
#define L2_ON_OFF_DM    0x0
#endif
 
.text
.global	 main

main:
  ta	  T_CHANGE_HPRIV


L2_on_off_dm:
        setx  L2CS_PA0, %l6, %g1
	ldx   [%g1], %o1

	setx  0xfffffffffffffffc, %l6, %i1	! <1:0>=00
	and   %i1, %o1, %o2
	
        mov   L2_ON_OFF_DM, %l0
	or    %o2, %l0, %l1

        stx   %l1, [%g1]

	nop
	membar #Sync


set_error_count_reg:
        set     0x1, %g6            !<16>=countone=1
        setx    DRAM_ERR_CNT_REG_PA, %l7, %o2
        stx     %g6, [%o2]

clear_soc_esr:
        setx    SOC_ESR_REG, %l7, %g5
        stx     %g0, [%g5]

clear_l2_esr:
        setx    L2_ERR_STAT_REG, %l7, %g5
        stx     %g0, [%g5]

clear_mcu_esr:
        setx    DRAM_ERR_STAT_REG, %l7, %g5
        stx     %g0, [%g5]

clear_l2_ear_0:
        setx    L2_ERR_ADDR_REG, %l7, %g5
        stx     %g0, [%g5]

clear_fbd_err_synd:
        setx    DRAM_FBD_ERR_SYND_REG_PA, %l7, %g5
        stx     %g0, [%g5]

set_inj_err_src_reg:
        set     INJ_ERR_SRC, %g1
        setx    DRAM_FBD_INJ_ERR_SRC_REG_PA, %l7, %g3
        stx     %g1, [%g3]
        membar 0x40

set_ejr:
        set     0x1, %g1
        sllx    %g1, ERR_FIELD, %g2
        setx    SOC_EJR_REG, %l7, %g3
        stx     %g2, [%g3]
        membar 0x40

        setx    0x40, %l1, %g4
delay_loop:
        nop
        nop
        nop
        nop
        dec     %g4
        brnz    %g4, delay_loop
        nop


check_mcu_esr:
        mov     0x1, %l1
        sllx    %l1, DRAM_ES_FBR, %l6

        setx    DRAM_ERR_STAT_REG, %l3, %g5  
        ldx     [%g5], %l1

        setx    0xffffffffffff0000, %l3, %l0
        andcc   %l0, %l1, %l5                   ! Donot check SYND bits
/*
        subcc   %l5, %l6, %i4
        brnz    %i4, test_fail
        nop
*/

L2_Init:
        setx	0x1111111111111110, %g7, %o0
	setx	0x2222222222222220, %g7, %o1

	setx	L20, %g7, %l0
	setx	L21, %g7, %l1

	dec	%g1
	cmp	%g1, %g0


L2_0:
     	stx	%o0, [%l0]
	ldx	[%l0], %g1

L2_1:
     	stx	%o1, [%l1]
	ldx	[%l1], %g1
	membar 	0x40

next_line:
	add	%l0, 0x200, %l0
        add     %l1, 0x200, %l1

L2_0_again:
     	stx	%o0, [%l0]
	ldx	[%l0], %g1

L2_1_again:
        stx	%o1, [%l1]
	ldx	[%l1], %g1
	membar 	0x40

check_mcu_esr_again:
        mov     0x1, %l1
        sllx    %l1, DRAM_ES_FBR, %l6

        setx    DRAM_ERR_STAT_REG, %l3, %g5  
        ldx     [%g5], %l1

        setx    0xffffffffffff0000, %l3, %l0
        andcc   %l0, %l1, %l5                   ! Donot check SYND bits

        subcc   %l5, %l6, %i4
        brnz    %i4, test_fail
        nop

read_fbd_err_synd_reg:
        setx    DRAM_FBD_ERR_SYND_REG_PA, %l7, %o2
        ldx     [%o2], %g1

        setx    0x8000000000000000, %l7, %o3
        set     0x1, %o4
        sll     %o4, FBSYND, %o5
        or      %o3, %o5, %g2

        and     %g1, %g2, %g3
        subcc   %g2, %g3, %g4
        brnz    %g4, test_fail
        nop


check_L2_ESR_0:
        setx    L2_ERR_STAT_REG, %l3, %g5  
        ldx     [%g5], %l6

        setx    0xbffffffff0000000, %l3, %l0	!msa 01/08/07: no MEC check
        andcc   %l0, %l6, %l5                   ! Donot check L2ESR SYND bits

        mov     0x1, %l1
        sllx    %l1, L2ES_DSC, %i5

        subcc   %l5, %i5, %o5
        brnz    %o5, test_fail
        nop

ba test_pass
nop

/******************************************************
 * Exit code
 *******************************************************/

test_pass:
ta  T_GOOD_TRAP


test_fail:
ta  T_BAD_TRAP
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: n2_err_mcu_int_fbu_AA.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define MAIN_PAGE_NUCLEUS_ALSO
	39	#define MAIN_PAGE_HV_ALSO
	40
	41	#define CMP_FBD_SYND 0x0
	42
	43	#include "hboot.s"
	44	#include "asi_s.h"
	45
	46	#define L22 0x0004100080
	47	#define L23 0x00041000c0
	48
	49	#define L24 0x0000134100
	50	#define L25 0x0000134140
	51
	52	#define L26 0x0000134180
	53	#define L27 0x00001341c0
	54
	55	#ifdef MCU0
	56	#define DRAM_FBR_CNT_REG_PA DRAM_FBR_CNT_REG_PA_0
	57	#define DRAM_ERR_CNT_REG_PA DRAM_ERR_CNT_REG_PA_0
	58
	59	#define DRAM_FBD_ERR_SYND_REG_PA DRAM_FBD_ERR_SYND_REG_PA_0
	60	#define DRAM_FBD_INJ_ERR_SRC_REG_PA DRAM_FBD_INJ_ERR_SRC_REG_PA_0
	61
	62	#define DRAM_ERR_INJ_REG 0x8400000290
	63	#define DRAM_ERR_STAT_REG 0x8400000280
	64	#define L2_ERR_STAT_REG 0xAB00000000
65	#define L2_ERR_ADDR_REG 0xAC00000000
66
67	#define L20 0x0004100000
68	#define L21 0x0008100000
69	#endif
70
71	#ifdef MCU1
72	#define DRAM_FBR_CNT_REG_PA DRAM_FBR_CNT_REG_PA_1
73	#define DRAM_ERR_CNT_REG_PA DRAM_ERR_CNT_REG_PA_1
74
75	#define DRAM_FBD_ERR_SYND_REG_PA DRAM_FBD_ERR_SYND_REG_PA_1
76	#define DRAM_FBD_INJ_ERR_SRC_REG_PA DRAM_FBD_INJ_ERR_SRC_REG_PA_1
77
78	#define DRAM_ERR_INJ_REG 0x8400001290
79	#define DRAM_ERR_STAT_REG 0x8400001280
80	#define L2_ERR_STAT_REG 0xAB00000080
81	#define L2_ERR_ADDR_REG 0xAC00000080
82
83	#define L20 0x0004100080
84	#define L21 0x0008100080
85	#endif
86
87	#ifdef MCU2
88	#define DRAM_FBR_CNT_REG_PA DRAM_FBR_CNT_REG_PA_2
89	#define DRAM_ERR_CNT_REG_PA DRAM_ERR_CNT_REG_PA_2
90
91	#define DRAM_FBD_ERR_SYND_REG_PA DRAM_FBD_ERR_SYND_REG_PA_2
92	#define DRAM_FBD_INJ_ERR_SRC_REG_PA DRAM_FBD_INJ_ERR_SRC_REG_PA_2
93
94	#define DRAM_ERR_INJ_REG 0x8400002290
95	#define DRAM_ERR_STAT_REG 0x8400002280
96	#define L2_ERR_STAT_REG 0xAB00000100
97	#define L2_ERR_ADDR_REG 0xAC00000100
98
99	#define L20 0x0004100100
100	#define L21 0x0008100100
101	#endif
102
103	#ifdef MCU3
104	#define DRAM_FBR_CNT_REG_PA DRAM_FBR_CNT_REG_PA_3
105	#define DRAM_ERR_CNT_REG_PA DRAM_ERR_CNT_REG_PA_3
106
107	#define DRAM_FBD_ERR_SYND_REG_PA DRAM_FBD_ERR_SYND_REG_PA_3
108	#define DRAM_FBD_INJ_ERR_SRC_REG_PA DRAM_FBD_INJ_ERR_SRC_REG_PA_3
109
110	#define DRAM_ERR_INJ_REG 0x8400003290
111	#define DRAM_ERR_STAT_REG 0x8400003280
112	#define L2_ERR_STAT_REG 0xAB00000180
113	#define L2_ERR_ADDR_REG 0xAC00000180
114
115	#define L20 0x0004100180
116	#define L21 0x0008100180
117	#endif
118
119	#ifdef ECC
120	#define CMP_ECC_CNT 0x0
121	#else
122	#define CMP_ECC_CNT 0x1
123	#endif
124
125	#ifdef L2_OFF
126	#define L2_ON_OFF_DM 0x1
127	#else
128	#define L2_ON_OFF_DM 0x0
129	#endif
130
131	.text
132	.global main
133
134	main:
135	ta T_CHANGE_HPRIV
136
137
138	L2_on_off_dm:
139	setx L2CS_PA0, %l6, %g1
140	ldx [%g1], %o1
141
142	setx 0xfffffffffffffffc, %l6, %i1 ! <1:0>=00
143	and %i1, %o1, %o2
144
145	mov L2_ON_OFF_DM, %l0
146	or %o2, %l0, %l1
147
148	stx %l1, [%g1]
149
150	nop
151	membar #Sync
152
153
154	set_error_count_reg:
155	set 0x1, %g6 !<16>=countone=1
156	setx DRAM_ERR_CNT_REG_PA, %l7, %o2
157	stx %g6, [%o2]
158
159	clear_soc_esr:
160	setx SOC_ESR_REG, %l7, %g5
161	stx %g0, [%g5]
162
163	clear_l2_esr:
164	setx L2_ERR_STAT_REG, %l7, %g5
165	stx %g0, [%g5]
166
167	clear_mcu_esr:
168	setx DRAM_ERR_STAT_REG, %l7, %g5
169	stx %g0, [%g5]
170
171	clear_l2_ear_0:
172	setx L2_ERR_ADDR_REG, %l7, %g5
173	stx %g0, [%g5]
174
175	clear_fbd_err_synd:
176	setx DRAM_FBD_ERR_SYND_REG_PA, %l7, %g5
177	stx %g0, [%g5]
178
179	set_inj_err_src_reg:
180	set INJ_ERR_SRC, %g1
181	setx DRAM_FBD_INJ_ERR_SRC_REG_PA, %l7, %g3
182	stx %g1, [%g3]
183	membar 0x40
184
185	set_ejr:
186	set 0x1, %g1
187	sllx %g1, ERR_FIELD, %g2
188	setx SOC_EJR_REG, %l7, %g3
189	stx %g2, [%g3]
190	membar 0x40
191
192	setx 0x40, %l1, %g4
193	delay_loop:
194	nop
195	nop
196	nop
197	nop
198	dec %g4
199	brnz %g4, delay_loop
200	nop
201
202
203
204	check_mcu_esr:
205	mov 0x1, %l1
206	sllx %l1, DRAM_ES_FBR, %l6
207
208	setx DRAM_ERR_STAT_REG, %l3, %g5
209	ldx [%g5], %l1
210
211	setx 0xffffffffffff0000, %l3, %l0
212	andcc %l0, %l1, %l5 ! Donot check SYND bits
213	/*
214	subcc %l5, %l6, %i4
215	brnz %i4, test_fail
216	nop
217	*/
218
219	L2_Init:
220	setx 0x1111111111111110, %g7, %o0
221	setx 0x2222222222222220, %g7, %o1
222
223	setx L20, %g7, %l0
224	setx L21, %g7, %l1
225
226	dec %g1
227	cmp %g1, %g0
228
229
230	L2_0:
231	stx %o0, [%l0]
232	ldx [%l0], %g1
233
234	L2_1:
235	stx %o1, [%l1]
236	ldx [%l1], %g1
237	membar 0x40
238
239	next_line:
240	add %l0, 0x200, %l0
241	add %l1, 0x200, %l1
242
243	L2_0_again:
244	stx %o0, [%l0]
245	ldx [%l0], %g1
246
247	L2_1_again:
248	stx %o1, [%l1]
249	ldx [%l1], %g1
250	membar 0x40
251
252	check_mcu_esr_again:
253	mov 0x1, %l1
254	sllx %l1, DRAM_ES_FBR, %l6
255
256	setx DRAM_ERR_STAT_REG, %l3, %g5
257	ldx [%g5], %l1
258
259	setx 0xffffffffffff0000, %l3, %l0
260	andcc %l0, %l1, %l5 ! Donot check SYND bits
261
262	subcc %l5, %l6, %i4
263	brnz %i4, test_fail
264	nop
265
266	read_fbd_err_synd_reg:
267	setx DRAM_FBD_ERR_SYND_REG_PA, %l7, %o2
268	ldx [%o2], %g1
269
270	setx 0x8000000000000000, %l7, %o3
271	set 0x1, %o4
272	sll %o4, FBSYND, %o5
273	or %o3, %o5, %g2
274
275	and %g1, %g2, %g3
276	subcc %g2, %g3, %g4
277	brnz %g4, test_fail
278	nop
279
280
281	check_L2_ESR_0:
282	setx L2_ERR_STAT_REG, %l3, %g5
283	ldx [%g5], %l6
284
285	setx 0xbffffffff0000000, %l3, %l0 !msa 01/08/07: no MEC check
286	andcc %l0, %l6, %l5 ! Donot check L2ESR SYND bits
287
288	mov 0x1, %l1
289	sllx %l1, L2ES_DSC, %i5
290
291	subcc %l5, %i5, %o5
292	brnz %o5, test_fail
293	nop
294
295	ba test_pass
296	nop
297
298	/******************************************************
299	* Exit code
300	*******************************************************/
301
302	test_pass:
303	ta T_GOOD_TRAP
304
305
306	test_fail:
307	ta T_BAD_TRAP
308
309
310