[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / mcu / n2_err_mcu_ios_fbr_trap.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: n2_err_mcu_ios_fbr_trap.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
#define H_HT0_Sw_Recoverable_Error_0x40  My_Recoverable_Sw_error_trap

#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO


#include "hboot.s"
#include "asi_s.h"

#define L20 0x0020134000
#define L21 0x0000134040

#define L22 0x0000134080
#define L23 0x00001340c0

#define L24 0x0000134100
#define L25 0x0000134140

#define L26 0x0000134180
#define L27 0x00001341c0

#ifdef MCU0
#define DRAM_FBR_CNT_REG_PA             DRAM_FBR_CNT_REG_PA_0
#define DRAM_ERR_CNT_REG_PA             DRAM_ERR_CNT_REG_PA_0

#define DRAM_FBD_ERR_SYND_REG_PA        DRAM_FBD_ERR_SYND_REG_PA_0
#define DRAM_FBD_INJ_ERR_SRC_REG_PA     DRAM_FBD_INJ_ERR_SRC_REG_PA_0

#define  DRAM_ERR_INJ_REG               0x8400000290
#define  DRAM_ERR_STAT_REG              0x8400000280
#define  L2_ERR_STAT_REG                0xAB00000000
#define  L2_ERR_ADDR_REG                0xAC00000000
#endif

#ifdef MCU1
#define DRAM_FBR_CNT_REG_PA             DRAM_FBR_CNT_REG_PA_1
#define DRAM_ERR_CNT_REG_PA             DRAM_ERR_CNT_REG_PA_1

#define DRAM_FBD_ERR_SYND_REG_PA        DRAM_FBD_ERR_SYND_REG_PA_1
#define DRAM_FBD_INJ_ERR_SRC_REG_PA     DRAM_FBD_INJ_ERR_SRC_REG_PA_1

#define  DRAM_ERR_INJ_REG               0x8400001290
#define  DRAM_ERR_STAT_REG              0x8400001280
#define  L2_ERR_STAT_REG                0xAB00000080
#define  L2_ERR_ADDR_REG                0xAC00000080
#endif

#ifdef MCU2
#define DRAM_FBR_CNT_REG_PA             DRAM_FBR_CNT_REG_PA_2
#define DRAM_ERR_CNT_REG_PA             DRAM_ERR_CNT_REG_PA_2

#define DRAM_FBD_ERR_SYND_REG_PA        DRAM_FBD_ERR_SYND_REG_PA_2
#define DRAM_FBD_INJ_ERR_SRC_REG_PA     DRAM_FBD_INJ_ERR_SRC_REG_PA_2

#define  DRAM_ERR_INJ_REG               0x8400002290
#define  DRAM_ERR_STAT_REG              0x8400002280
#define  L2_ERR_STAT_REG                0xAB00000100
#define  L2_ERR_ADDR_REG                0xAC00000100
#endif

#ifdef MCU3
#define DRAM_FBR_CNT_REG_PA             DRAM_FBR_CNT_REG_PA_3
#define DRAM_ERR_CNT_REG_PA             DRAM_ERR_CNT_REG_PA_3

#define DRAM_FBD_ERR_SYND_REG_PA        DRAM_FBD_ERR_SYND_REG_PA_3
#define DRAM_FBD_INJ_ERR_SRC_REG_PA     DRAM_FBD_INJ_ERR_SRC_REG_PA_3


#define  DRAM_ERR_INJ_REG               0x8400003290
#define  DRAM_ERR_STAT_REG              0x8400003280
#define  L2_ERR_STAT_REG                0xAB00000180
#define  L2_ERR_ADDR_REG                0xAC00000180
#endif

#define CMP_ECC_CNT     0x1

#ifdef L2_OFF
#define L2_ON_OFF_DM	0x1
#else
#define L2_ON_OFF_DM    0x0
#endif
 
#define TT      0x63

.text
.global	 main
.global  My_Corrected_ECC_error_trap
.global  My_Recoverable_Sw_error_trap


main:
	ta	  T_CHANGE_HPRIV
	clr	%i6
	clr	%i7
	clr	%i2
	clr	%i0

write_mcu_fbr_count_reg:
	set	0x10000, %g6		!<16>=countone=1
	setx	DRAM_FBR_CNT_REG_PA, %l7, %o2
	stx     %g6, [%o2]
	ldx     [%o2], %i1

set_error_count_reg:
        set     0x1, %g6            !<16>=countone=1
        setx    DRAM_ERR_CNT_REG_PA, %l7, %o2
        stx     %g6, [%o2]

clear_soc_esr:
        setx   	SOC_ESR_REG, %l7, %g5
        stx     %g0, [%g5]

clear_soc_per:
        setx    SOC_PER_REG, %l7, %g5
        stx     %g0, [%g5]

clear_mcu_esr:
        setx    DRAM_ERR_STAT_REG, %l7, %g5
        stx     %g0, [%g5]

clear_l2_esr:
        setx    L2_ERR_STAT_REG, %l7, %g5
        stx     %g0, [%g5]

clear_l2_ear:
        setx    L2_ERR_ADDR_REG, %l7, %g5
        stx     %g0, [%g5]

set_inj_err_src_reg:
        set     INJ_ERR_SRC, %g1
        setx    DRAM_FBD_INJ_ERR_SRC_REG_PA, %l7, %g3
        stx     %g1, [%g3]
        membar 0x40

set_ejr:
        set     0x1, %g1
        sllx    %g1, ERR_FIELD, %g2 
        setx    SOC_EJR_REG, %l7, %g3
        stx     %g2, [%g3]
        membar 0x40

set_eie:
        setx    SOC_EIE_REG, %l7, %g3
        stx     %g2, [%g3]
        membar 0x40

L2_Init:
	setx	L20, %g7, %l0
	setx	L22, %g7, %l2
	setx	L24, %g7, %l4
	setx	L26, %g7, %l6

	! Each of the line should be a miss in L2 and Read from Memory

#ifdef MCU0
L2_0:
        ldx     [%l0], %g1
#endif

#ifdef MCU1
L2_2:
        ldx     [%l2], %g1
#endif

#ifdef MCU2
L2_4:
        ldx     [%l4], %g1
#endif

#ifdef MCU3
L2_6:
        ldx     [%l6], %g1
#endif

	membar 0x40


        !setx    0x100, %g1, %g4
        set    0x100,%g4
delay_loop:
        dec     %g4
       ! brz    %g4, test_fail 
        nop

        cmp   %i7, %g0
       ! bne   %xcc, check_error_trap 
        nop

!	ba	delay_loop
	nop

idle_cycles:
        setx    L20, %g7, %l0
        setx    L22, %g7, %l2
        setx    L26, %g7, %l6
        setx    L24, %g7, %l4
        setx    L26, %g7, %l6
        setx    L20, %g7, %l0
        setx    L26, %g7, %l6
        setx    L22, %g7, %l2
        setx    L26, %g7, %l6
        setx    L26, %g7, %l6
        setx    L24, %g7, %l4
        setx    L26, %g7, %l6
        setx    L26, %g7, %l6
        setx    L26, %g7, %l6
        setx    L26, %g7, %l6


check_error_trap:
        setx  EXECUTED, %l1, %l0
        cmp   %i2, %l0
        bne   test_fail
        nop

        mov   TT, %l0
        cmp   %i0, %l0
        bne   test_fail
        nop

/******************************************************
 * Exit code
 *******************************************************/

test_pass:
EXIT_GOOD

test_fail:
EXIT_BAD


/************************************************************************
   Trap Handlers
 ************************************************************************/
My_Recoverable_Sw_error_trap:
        nop
	ba	test_fail
	nop

	!PER not cleared at the end of the TRAP Handler to avoid further Trap
My_Corrected_ECC_error_trap:
        ! Signal trap taken
        setx  EXECUTED, %l0, %i2
        ! save trap type value
        rdpr  %tt, %i0

	inc	%i7

clear_ejr_tt63:
        setx    SOC_EJR_REG, %l7, %l0
        stx     %g0, [%l0]
        nop

check_desr_tt63:
        ldxa  [%g0]0x4c, %g2
        nop
        setx    0x8b00000000000000, %l0, %g3
        subcc   %g2, %g3, %g4
        brnz    %g4, test_fail
	nop

check_per_tt63:
        setx    SOC_PER_REG, %l7, %g5
        ldx     [%g5], %i1
        nop
        setx    0x8000000000000000, %l7, %g7    !valid bit
        set     0x1, %g1
        sllx    %g1, ERR_FIELD, %g2
        or      %g7, %g2, %i3
        subcc   %i1, %i3, %i4
        brnz    %i4, test_fail
        nop

check_mcu_ESR_tt63:
        mov     0x1, %l1
        sllx    %l1, DRAM_ES_FBR, %l6

        setx  DRAM_ERR_STAT_REG, %l3, %g5  
        ldx   [%g5], %l1

        setx  0xbfffffffffff0000, %l3, %l0	! MEC bit not checked
        andcc %l0, %l1, %l5

        sub     %l5, %l6, %i4
        brnz    %i4, test_fail
        nop


check_mcu_EAR_tt63:
        setx  DRAM_ERR_ADDR_REG_PA_0, %l3, %g5  
        ldx   [%g5], %l1


	/*
	! Setting DSC and/ or DSU does not cause any logging of the error 
        ! address or syndrome in the L2 Error Address register. 
        ! It also does not update the VEC/VEU/MEC/MEU bits */
check_L2_ESR_tt63:
        setx  L2_ERR_STAT_REG, %l3, %g5  
        ldx   [%g5], %l6

        setx  0xbffffffff0000000, %l3, %l0
        andcc %l0, %l6, %l5                   ! Donot check L2ESR SYND bits and MEC

        mov   0x1, %l1
        sllx  %l1, L2ES_DSC, %l0

        cmp   %l5, %l0
        bne   %xcc, test_fail
        nop

check_fbr_cnt_reg_tt63:
        setx    DRAM_FBR_CNT_REG_PA, %l7, %o2
        ldx     [%o2], %g1
        set     0x10000, %g6            !<16>=countone=1
        sub     %g1, %g6, %i4
        brnz    %i4, test_fail
        nop

read_err_cnt_reg_tt63:
        setx    DRAM_ERR_CNT_REG_PA, %l7, %o2
        ldx     [%o2], %g1
        set     CMP_ECC_CNT, %i1
        sub     %g1, %i1, %i4
        brnz    %i4, test_fail
        nop

read_fbd_err_synd_reg_tt63:
        setx    DRAM_FBD_ERR_SYND_REG_PA, %l7, %o2
        ldx     [%o2], %g1

        setx    0x8000000000000000, %l7, %o3
        set     0x1, %o4
        sll     %o4, FBSYND, %o5
        or      %o3, %o5, %g2

        and     %g1, %g2, %g3
        subcc   %g2, %g3, %g4
        brnz    %g4, test_fail
        nop

clear_per_tt63:
        setx    SOC_PER_REG, %l7, %l0
        stx     %g0, [%l0]
        nop

clear_esr_tt63:
        setx    SOC_ESR_REG, %l7, %l0
        stx     %g0, [%l0]
        nop

       	done 
        nop
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: n2_err_mcu_ios_fbr_trap.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
	39	#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
	40
	41	#define MAIN_PAGE_NUCLEUS_ALSO
	42	#define MAIN_PAGE_HV_ALSO
	43
	44
	45	#include "hboot.s"
	46	#include "asi_s.h"
	47
	48	#define L20 0x0020134000
	49	#define L21 0x0000134040
	50
	51	#define L22 0x0000134080
	52	#define L23 0x00001340c0
	53
	54	#define L24 0x0000134100
	55	#define L25 0x0000134140
	56
	57	#define L26 0x0000134180
	58	#define L27 0x00001341c0
	59
	60	#ifdef MCU0
	61	#define DRAM_FBR_CNT_REG_PA DRAM_FBR_CNT_REG_PA_0
	62	#define DRAM_ERR_CNT_REG_PA DRAM_ERR_CNT_REG_PA_0
	63
	64	#define DRAM_FBD_ERR_SYND_REG_PA DRAM_FBD_ERR_SYND_REG_PA_0
65	#define DRAM_FBD_INJ_ERR_SRC_REG_PA DRAM_FBD_INJ_ERR_SRC_REG_PA_0
66
67	#define DRAM_ERR_INJ_REG 0x8400000290
68	#define DRAM_ERR_STAT_REG 0x8400000280
69	#define L2_ERR_STAT_REG 0xAB00000000
70	#define L2_ERR_ADDR_REG 0xAC00000000
71	#endif
72
73	#ifdef MCU1
74	#define DRAM_FBR_CNT_REG_PA DRAM_FBR_CNT_REG_PA_1
75	#define DRAM_ERR_CNT_REG_PA DRAM_ERR_CNT_REG_PA_1
76
77	#define DRAM_FBD_ERR_SYND_REG_PA DRAM_FBD_ERR_SYND_REG_PA_1
78	#define DRAM_FBD_INJ_ERR_SRC_REG_PA DRAM_FBD_INJ_ERR_SRC_REG_PA_1
79
80	#define DRAM_ERR_INJ_REG 0x8400001290
81	#define DRAM_ERR_STAT_REG 0x8400001280
82	#define L2_ERR_STAT_REG 0xAB00000080
83	#define L2_ERR_ADDR_REG 0xAC00000080
84	#endif
85
86	#ifdef MCU2
87	#define DRAM_FBR_CNT_REG_PA DRAM_FBR_CNT_REG_PA_2
88	#define DRAM_ERR_CNT_REG_PA DRAM_ERR_CNT_REG_PA_2
89
90	#define DRAM_FBD_ERR_SYND_REG_PA DRAM_FBD_ERR_SYND_REG_PA_2
91	#define DRAM_FBD_INJ_ERR_SRC_REG_PA DRAM_FBD_INJ_ERR_SRC_REG_PA_2
92
93	#define DRAM_ERR_INJ_REG 0x8400002290
94	#define DRAM_ERR_STAT_REG 0x8400002280
95	#define L2_ERR_STAT_REG 0xAB00000100
96	#define L2_ERR_ADDR_REG 0xAC00000100
97	#endif
98
99	#ifdef MCU3
100	#define DRAM_FBR_CNT_REG_PA DRAM_FBR_CNT_REG_PA_3
101	#define DRAM_ERR_CNT_REG_PA DRAM_ERR_CNT_REG_PA_3
102
103	#define DRAM_FBD_ERR_SYND_REG_PA DRAM_FBD_ERR_SYND_REG_PA_3
104	#define DRAM_FBD_INJ_ERR_SRC_REG_PA DRAM_FBD_INJ_ERR_SRC_REG_PA_3
105
106
107	#define DRAM_ERR_INJ_REG 0x8400003290
108	#define DRAM_ERR_STAT_REG 0x8400003280
109	#define L2_ERR_STAT_REG 0xAB00000180
110	#define L2_ERR_ADDR_REG 0xAC00000180
111	#endif
112
113	#define CMP_ECC_CNT 0x1
114
115	#ifdef L2_OFF
116	#define L2_ON_OFF_DM 0x1
117	#else
118	#define L2_ON_OFF_DM 0x0
119	#endif
120
121	#define TT 0x63
122
123	.text
124	.global main
125	.global My_Corrected_ECC_error_trap
126	.global My_Recoverable_Sw_error_trap
127
128
129	main:
130	ta T_CHANGE_HPRIV
131	clr %i6
132	clr %i7
133	clr %i2
134	clr %i0
135
136	write_mcu_fbr_count_reg:
137	set 0x10000, %g6 !<16>=countone=1
138	setx DRAM_FBR_CNT_REG_PA, %l7, %o2
139	stx %g6, [%o2]
140	ldx [%o2], %i1
141
142	set_error_count_reg:
143	set 0x1, %g6 !<16>=countone=1
144	setx DRAM_ERR_CNT_REG_PA, %l7, %o2
145	stx %g6, [%o2]
146
147	clear_soc_esr:
148	setx SOC_ESR_REG, %l7, %g5
149	stx %g0, [%g5]
150
151	clear_soc_per:
152	setx SOC_PER_REG, %l7, %g5
153	stx %g0, [%g5]
154
155	clear_mcu_esr:
156	setx DRAM_ERR_STAT_REG, %l7, %g5
157	stx %g0, [%g5]
158
159	clear_l2_esr:
160	setx L2_ERR_STAT_REG, %l7, %g5
161	stx %g0, [%g5]
162
163	clear_l2_ear:
164	setx L2_ERR_ADDR_REG, %l7, %g5
165	stx %g0, [%g5]
166
167	set_inj_err_src_reg:
168	set INJ_ERR_SRC, %g1
169	setx DRAM_FBD_INJ_ERR_SRC_REG_PA, %l7, %g3
170	stx %g1, [%g3]
171	membar 0x40
172
173	set_ejr:
174	set 0x1, %g1
175	sllx %g1, ERR_FIELD, %g2
176	setx SOC_EJR_REG, %l7, %g3
177	stx %g2, [%g3]
178	membar 0x40
179
180	set_eie:
181	setx SOC_EIE_REG, %l7, %g3
182	stx %g2, [%g3]
183	membar 0x40
184
185	L2_Init:
186	setx L20, %g7, %l0
187	setx L22, %g7, %l2
188	setx L24, %g7, %l4
189	setx L26, %g7, %l6
190
191	! Each of the line should be a miss in L2 and Read from Memory
192
193	#ifdef MCU0
194	L2_0:
195	ldx [%l0], %g1
196	#endif
197
198	#ifdef MCU1
199	L2_2:
200	ldx [%l2], %g1
201	#endif
202
203	#ifdef MCU2
204	L2_4:
205	ldx [%l4], %g1
206	#endif
207
208	#ifdef MCU3
209	L2_6:
210	ldx [%l6], %g1
211	#endif
212
213	membar 0x40
214
215
216	!setx 0x100, %g1, %g4
217	set 0x100,%g4
218	delay_loop:
219	dec %g4
220	! brz %g4, test_fail
221	nop
222
223	cmp %i7, %g0
224	! bne %xcc, check_error_trap
225	nop
226
227	! ba delay_loop
228	nop
229
230	idle_cycles:
231	setx L20, %g7, %l0
232	setx L22, %g7, %l2
233	setx L26, %g7, %l6
234	setx L24, %g7, %l4
235	setx L26, %g7, %l6
236	setx L20, %g7, %l0
237	setx L26, %g7, %l6
238	setx L22, %g7, %l2
239	setx L26, %g7, %l6
240	setx L26, %g7, %l6
241	setx L24, %g7, %l4
242	setx L26, %g7, %l6
243	setx L26, %g7, %l6
244	setx L26, %g7, %l6
245	setx L26, %g7, %l6
246
247
248	check_error_trap:
249	setx EXECUTED, %l1, %l0
250	cmp %i2, %l0
251	bne test_fail
252	nop
253
254	mov TT, %l0
255	cmp %i0, %l0
256	bne test_fail
257	nop
258
259	/******************************************************
260	* Exit code
261	*******************************************************/
262
263	test_pass:
264	EXIT_GOOD
265
266	test_fail:
267	EXIT_BAD
268
269
270
271
272	/************************************************************************
273	Trap Handlers
274	************************************************************************/
275	My_Recoverable_Sw_error_trap:
276	nop
277	ba test_fail
278	nop
279
280	!PER not cleared at the end of the TRAP Handler to avoid further Trap
281	My_Corrected_ECC_error_trap:
282	! Signal trap taken
283	setx EXECUTED, %l0, %i2
284	! save trap type value
285	rdpr %tt, %i0
286
287	inc %i7
288
289	clear_ejr_tt63:
290	setx SOC_EJR_REG, %l7, %l0
291	stx %g0, [%l0]
292	nop
293
294	check_desr_tt63:
295	ldxa [%g0]0x4c, %g2
296	nop
297	setx 0x8b00000000000000, %l0, %g3
298	subcc %g2, %g3, %g4
299	brnz %g4, test_fail
300	nop
301
302	check_per_tt63:
303	setx SOC_PER_REG, %l7, %g5
304	ldx [%g5], %i1
305	nop
306	setx 0x8000000000000000, %l7, %g7 !valid bit
307	set 0x1, %g1
308	sllx %g1, ERR_FIELD, %g2
309	or %g7, %g2, %i3
310	subcc %i1, %i3, %i4
311	brnz %i4, test_fail
312	nop
313
314	check_mcu_ESR_tt63:
315	mov 0x1, %l1
316	sllx %l1, DRAM_ES_FBR, %l6
317
318	setx DRAM_ERR_STAT_REG, %l3, %g5
319	ldx [%g5], %l1
320
321	setx 0xbfffffffffff0000, %l3, %l0 ! MEC bit not checked
322	andcc %l0, %l1, %l5
323
324	sub %l5, %l6, %i4
325	brnz %i4, test_fail
326	nop
327
328
329	check_mcu_EAR_tt63:
330	setx DRAM_ERR_ADDR_REG_PA_0, %l3, %g5
331	ldx [%g5], %l1
332
333
334	/*
335	! Setting DSC and/ or DSU does not cause any logging of the error
336	! address or syndrome in the L2 Error Address register.
337	! It also does not update the VEC/VEU/MEC/MEU bits */
338	check_L2_ESR_tt63:
339	setx L2_ERR_STAT_REG, %l3, %g5
340	ldx [%g5], %l6
341
342	setx 0xbffffffff0000000, %l3, %l0
343	andcc %l0, %l6, %l5 ! Donot check L2ESR SYND bits and MEC
344
345	mov 0x1, %l1
346	sllx %l1, L2ES_DSC, %l0
347
348	cmp %l5, %l0
349	bne %xcc, test_fail
350	nop
351
352	check_fbr_cnt_reg_tt63:
353	setx DRAM_FBR_CNT_REG_PA, %l7, %o2
354	ldx [%o2], %g1
355	set 0x10000, %g6 !<16>=countone=1
356	sub %g1, %g6, %i4
357	brnz %i4, test_fail
358	nop
359
360	read_err_cnt_reg_tt63:
361	setx DRAM_ERR_CNT_REG_PA, %l7, %o2
362	ldx [%o2], %g1
363	set CMP_ECC_CNT, %i1
364	sub %g1, %i1, %i4
365	brnz %i4, test_fail
366	nop
367
368	read_fbd_err_synd_reg_tt63:
369	setx DRAM_FBD_ERR_SYND_REG_PA, %l7, %o2
370	ldx [%o2], %g1
371
372	setx 0x8000000000000000, %l7, %o3
373	set 0x1, %o4
374	sll %o4, FBSYND, %o5
375	or %o3, %o5, %g2
376
377	and %g1, %g2, %g3
378	subcc %g2, %g3, %g4
379	brnz %g4, test_fail
380	nop
381
382	clear_per_tt63:
383	setx SOC_PER_REG, %l7, %l0
384	stx %g0, [%l0]
385	nop
386
387	clear_esr_tt63:
388	setx SOC_ESR_REG, %l7, %l0
389	stx %g0, [%l0]
390	nop
391
392	done
393	nop
394