[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / mcu / n2_mcu_si_DSC.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: n2_mcu_si_DSC.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap

#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO

#define	 DRAM_SCRB_FREQ_REG   0x8400000018
#define	 DRAM_SCRB_ENB_REG    0x8400000040

#define  L2_ERR_STAT_REG    0xAB00000000
#define  L2_ERR_ADDR_REG    0xAC00000000

#define  TEST_DATA0         0x1000100081c3e008
#define  TEST_DATA1         0x2000200081c3e008
#define  TEST_DATA2         0x3000300081c3e008
#define  L2_ES_W1C_VALUE    0xc03ffff800000000
#define  DRAM_ES_W1C_VALUE  0xfe00000000000000

#ifdef MCU0
#define L2_BANK_ADDR        0x0       
#define MCU_BANK_ADDR       0x0
#define  DRAM_ERR_INJ_REG   0x8400000290
#define  DRAM_ERR_STAT_REG  0x8400000280
#define	 ERROR_ADDR	    0x20200000
#endif

#ifdef MCU1
#define L2_BANK_ADDR        0x80
#define MCU_BANK_ADDR       0x80
#define  DRAM_ERR_INJ_REG   0x8400001290
#define  DRAM_ERR_STAT_REG  0x8400001280


#endif

#ifdef MCU2
#define L2_BANK_ADDR        0x100
#define MCU_BANK_ADDR       0x100
#define  DRAM_ERR_INJ_REG   0x8400002290
#define  DRAM_ERR_STAT_REG  0x8400002280
#define  ERROR_ADDR         0x20200100

#endif

#ifdef MCU3
#define L2_BANK_ADDR        0x180
#define MCU_BANK_ADDR       0x180
#define  DRAM_ERR_INJ_REG   0x8400003290
#define  DRAM_ERR_STAT_REG  0x8400003280


#endif


#include "hboot.s"
#include "asi_s.h"
#include "err_defines.h"


.text
.global  main
.global	 My_Corrected_ECC_error_trap


main:
  ta T_CHANGE_HPRIV
  clr	%o0
  clr	%o1

disable_l1:
  ldxa  [%g0] ASI_LSU_CONTROL, %l0
  ! Remove the lower 2 bits (I-Cache and D-Cache enables)
  andn  %l0, 0x3, %l0
  stxa  %l0, [%g0] ASI_LSU_CONTROL

set_DRAM_scrub_frequency:
  setx	DRAM_SCRB_FREQ_REG, %l0, %l1
  mov	0x1, %l0
  stx	%l0, [%l1]
  membar #Sync


enable_err_reporting:
  setx L2EE_PA0, %l0, %l1
  ldx	[%l1], %l2
  mov	0x3, %l0
  or	%l2, %l0, %l2
  stx	%l2, [%l1]
  membar #Sync

set_DRAM_error_inject_ch0:
  set   0x9012, %l1                ! ECC Mask (1-bit error)
  mov   0x1, %l2 		
  sllx  %l2, DRAM_EI_SSHOT, %l3
  Or    %l1, %l3, %l1           ! Set single shot ; 
  mov   0x1, %l2
  sllx  %l2, DRAM_EI_ENB, %l3
  or    %l1, %l3, %l1           ! Enable error injection for the next write
  setx  DRAM_ERR_INJ_REG, %l3, %g6 
!  add   %g6, MCU_BANK_ADDR, %g6
  stx   %l1, [%g6]
  membar 0x40

store_to_L2:
  setx  TEST_DATA1, %l0, %g5

set_L2_Directly_Mapped_Mode:
  setx  L2CS_PA0, %l6, %g1
  add   %g1, L2_BANK_ADDR, %g1
  mov   0x2, %l0
  stx   %l0, [%g1]

store_to_L2_way0:
  setx  0x002000, %l0, %g2  ! bits [21:18] select way
  add   %g2, L2_BANK_ADDR, %g2
  stx %g5, [%g2]
  stx %g5, [%g2+8]
  membar #Sync

! Storing to same L2 way0 but different tag,this will write to mcu
write_mcu_channel_0:
  setx  0x21002000, %l0, %g3 ! bits [21:18] select way
  add   %g3, L2_BANK_ADDR, %g3
  stx %g5, [%g3]
!  stx %g5, [%g3+8]
  membar #Sync

enable_DRAM_scrub:
  setx	DRAM_SCRB_ENB_REG, %l0, %l1
  mov	0x1, %l0
  stx	%l0, [%l1]
  membar #Sync

        setx    0x22002000, %l0, %g3 ! bits [21:18] select way
	clr	%i5
Nops:
	cmp	%o0, %g0
	bne	%xcc, check_error_trap
	nop
 
	ldx	[%g3], %g1 ! cause  a fill 
        nop; nop; nop
        nop; nop; nop
        nop; nop; nop
        nop; nop; nop
        nop; nop; nop
        nop; nop; nop
        nop; nop; nop
        nop; nop; nop
        nop; nop; nop
        nop; nop; nop
        nop; nop; nop
        nop; nop; nop

	add	%g3, 0x200, %g3 
	inc	%i5
	cmp	%i5, 0x10
	bne	Nops
	nop

   
check_error_trap:
 setx	EXECUTED, %l1, %l0
  cmp	%o0, %l0
  bne	test_fail
  nop
  mov	TT_Corrected_ECC, %l0
  cmp	%o1, %l0
  bne	test_fail
  nop

  ba	test_pass
  nop


	/**************** Trap Handler *******************/
My_Corrected_ECC_error_trap:
  ! Signal trap taken
  setx	EXECUTED, %l0, %o0
  ! save trap type value
  rdpr	%tt, %o1

check_l2esr:
	setx  L2ES_PA0, %g7, %g1
	ldx   [%g1], %g2

	setx	0x4000000000, %g7, %g3
	cmp	%g2, %g3
	bne	%xcc, test_fail
	nop

check_mcuesr:
        setx 	DRAM_ERR_STAT_REG, %g7, %g1
        ldx   	[%g1], %g2

        setx    0x800000000009012, %g7, %g3	!SYND =0x2; DSC
        cmp     %g2, %g3
        bne     %xcc, test_fail
        nop

check_DESR:
	ldxa	[%g0] 0x4c, %g2
	setx	0x8900000000000000, %g7, %g3
	cmp	%g2, %g3
	bne	%xcc, test_fail
	nop

check_mcu_EAR:
	setx	0x8400000288, %l1, %g1
	ldx	[%g1], %g2
	setx	0x2000, %l1, %g3
!	cmp	%g2, %g3
!	bne	%xcc, test_fail
	nop

	retry
  	nop

  ba    test_pass
  nop

/*******************************************************
 * Exit code
 *******************************************************/

test_pass:
ta  T_GOOD_TRAP


test_fail:
ta  T_BAD_TRAP
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: n2_mcu_si_DSC.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
	39
	40	#define MAIN_PAGE_NUCLEUS_ALSO
	41	#define MAIN_PAGE_HV_ALSO
	42
	43	#define DRAM_SCRB_FREQ_REG 0x8400000018
	44	#define DRAM_SCRB_ENB_REG 0x8400000040
	45
	46	#define L2_ERR_STAT_REG 0xAB00000000
	47	#define L2_ERR_ADDR_REG 0xAC00000000
	48
	49	#define TEST_DATA0 0x1000100081c3e008
	50	#define TEST_DATA1 0x2000200081c3e008
	51	#define TEST_DATA2 0x3000300081c3e008
	52	#define L2_ES_W1C_VALUE 0xc03ffff800000000
	53	#define DRAM_ES_W1C_VALUE 0xfe00000000000000
	54
	55	#ifdef MCU0
	56	#define L2_BANK_ADDR 0x0
	57	#define MCU_BANK_ADDR 0x0
	58	#define DRAM_ERR_INJ_REG 0x8400000290
	59	#define DRAM_ERR_STAT_REG 0x8400000280
	60	#define ERROR_ADDR 0x20200000
	61	#endif
	62
	63	#ifdef MCU1
	64	#define L2_BANK_ADDR 0x80
65	#define MCU_BANK_ADDR 0x80
66	#define DRAM_ERR_INJ_REG 0x8400001290
67	#define DRAM_ERR_STAT_REG 0x8400001280
68
69
70	#endif
71
72	#ifdef MCU2
73	#define L2_BANK_ADDR 0x100
74	#define MCU_BANK_ADDR 0x100
75	#define DRAM_ERR_INJ_REG 0x8400002290
76	#define DRAM_ERR_STAT_REG 0x8400002280
77	#define ERROR_ADDR 0x20200100
78
79	#endif
80
81	#ifdef MCU3
82	#define L2_BANK_ADDR 0x180
83	#define MCU_BANK_ADDR 0x180
84	#define DRAM_ERR_INJ_REG 0x8400003290
85	#define DRAM_ERR_STAT_REG 0x8400003280
86
87
88	#endif
89
90
91	#include "hboot.s"
92	#include "asi_s.h"
93	#include "err_defines.h"
94
95
96	.text
97	.global main
98	.global My_Corrected_ECC_error_trap
99
100
101	main:
102	ta T_CHANGE_HPRIV
103	clr %o0
104	clr %o1
105
106	disable_l1:
107	ldxa [%g0] ASI_LSU_CONTROL, %l0
108	! Remove the lower 2 bits (I-Cache and D-Cache enables)
109	andn %l0, 0x3, %l0
110	stxa %l0, [%g0] ASI_LSU_CONTROL
111
112	set_DRAM_scrub_frequency:
113	setx DRAM_SCRB_FREQ_REG, %l0, %l1
114	mov 0x1, %l0
115	stx %l0, [%l1]
116	membar #Sync
117
118
119	enable_err_reporting:
120	setx L2EE_PA0, %l0, %l1
121	ldx [%l1], %l2
122	mov 0x3, %l0
123	or %l2, %l0, %l2
124	stx %l2, [%l1]
125	membar #Sync
126
127	set_DRAM_error_inject_ch0:
128	set 0x9012, %l1 ! ECC Mask (1-bit error)
129	mov 0x1, %l2
130	sllx %l2, DRAM_EI_SSHOT, %l3
131	Or %l1, %l3, %l1 ! Set single shot ;
132	mov 0x1, %l2
133	sllx %l2, DRAM_EI_ENB, %l3
134	or %l1, %l3, %l1 ! Enable error injection for the next write
135	setx DRAM_ERR_INJ_REG, %l3, %g6
136	! add %g6, MCU_BANK_ADDR, %g6
137	stx %l1, [%g6]
138	membar 0x40
139
140	store_to_L2:
141	setx TEST_DATA1, %l0, %g5
142
143	set_L2_Directly_Mapped_Mode:
144	setx L2CS_PA0, %l6, %g1
145	add %g1, L2_BANK_ADDR, %g1
146	mov 0x2, %l0
147	stx %l0, [%g1]
148
149	store_to_L2_way0:
150	setx 0x002000, %l0, %g2 ! bits [21:18] select way
151	add %g2, L2_BANK_ADDR, %g2
152	stx %g5, [%g2]
153	stx %g5, [%g2+8]
154	membar #Sync
155
156	! Storing to same L2 way0 but different tag,this will write to mcu
157	write_mcu_channel_0:
158	setx 0x21002000, %l0, %g3 ! bits [21:18] select way
159	add %g3, L2_BANK_ADDR, %g3
160	stx %g5, [%g3]
161	! stx %g5, [%g3+8]
162	membar #Sync
163
164	enable_DRAM_scrub:
165	setx DRAM_SCRB_ENB_REG, %l0, %l1
166	mov 0x1, %l0
167	stx %l0, [%l1]
168	membar #Sync
169
170	setx 0x22002000, %l0, %g3 ! bits [21:18] select way
171	clr %i5
172	Nops:
173	cmp %o0, %g0
174	bne %xcc, check_error_trap
175	nop
176
177	ldx [%g3], %g1 ! cause a fill
178	nop; nop; nop
179	nop; nop; nop
180	nop; nop; nop
181	nop; nop; nop
182	nop; nop; nop
183	nop; nop; nop
184	nop; nop; nop
185	nop; nop; nop
186	nop; nop; nop
187	nop; nop; nop
188	nop; nop; nop
189	nop; nop; nop
190
191	add %g3, 0x200, %g3
192	inc %i5
193	cmp %i5, 0x10
194	bne Nops
195	nop
196
197
198	check_error_trap:
199	setx EXECUTED, %l1, %l0
200	cmp %o0, %l0
201	bne test_fail
202	nop
203	mov TT_Corrected_ECC, %l0
204	cmp %o1, %l0
205	bne test_fail
206	nop
207
208	ba test_pass
209	nop
210
211
212	/************** Trap Handler *****************/
213	My_Corrected_ECC_error_trap:
214	! Signal trap taken
215	setx EXECUTED, %l0, %o0
216	! save trap type value
217	rdpr %tt, %o1
218
219	check_l2esr:
220	setx L2ES_PA0, %g7, %g1
221	ldx [%g1], %g2
222
223	setx 0x4000000000, %g7, %g3
224	cmp %g2, %g3
225	bne %xcc, test_fail
226	nop
227
228	check_mcuesr:
229	setx DRAM_ERR_STAT_REG, %g7, %g1
230	ldx [%g1], %g2
231
232	setx 0x800000000009012, %g7, %g3 !SYND =0x2; DSC
233	cmp %g2, %g3
234	bne %xcc, test_fail
235	nop
236
237	check_DESR:
238	ldxa [%g0] 0x4c, %g2
239	setx 0x8900000000000000, %g7, %g3
240	cmp %g2, %g3
241	bne %xcc, test_fail
242	nop
243
244	check_mcu_EAR:
245	setx 0x8400000288, %l1, %g1
246	ldx [%g1], %g2
247	setx 0x2000, %l1, %g3
248	! cmp %g2, %g3
249	! bne %xcc, test_fail
250	nop
251
252	retry
253	nop
254
255	ba test_pass
256	nop
257
258	/*******************************************************
259	* Exit code
260	*******************************************************/
261
262	test_pass:
263	ta T_GOOD_TRAP
264
265
266	test_fail:
267	ta T_BAD_TRAP
268
269
270