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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / ncu / n2_err_ncu_csrs.s
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86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: n2_err_ncu_csrs.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define MAIN_PAGE_NUCLEUS_ALSO
39#define MAIN_PAGE_HV_ALSO
40
41
42#define SOC_ESR_REG 0x8000003000
43#define SOC_ELE_REG 0x8000003008
44#define SOC_EIE_REG 0x8000003010
45#define SOC_EJR_REG 0x8000003018
46#define SOC_FEE_REG 0x8000003020
47#define SOC_PER_REG 0x8000003028
48#define SOC_SII_SYN_REG 0x8000003030
49#define SOC_NCU_SYN_REG 0x8000003038
50
51
52#include "hboot.s"
53#include "asi_s.h"
54#include "err_defines.h"
55
56
57.text
58.global main
59
60
61main:
62 ta T_CHANGE_HPRIV
63
64/********************************
65* SOC Error Status Register
66*********************************/
67
68soc_err_stat_reg:
69 setx 0xffffffffffffffff, %l7, %g7
70 setx SOC_ESR_REG, %l7, %g5
71
72soc_err_stat_reg_por:
73 ldx [%g5], %i1
74
75 cmp %i1, %g0
76 bne %xcc, test_fail
77 nop
78
79soc_err_stat_reg_ones:
80 stx %g7, [%g5]
81 ldx [%g5], %i0
82
83 setx 0x8000076dbfffffff, %l7, %i2 !<24>=TestMode; R/W
84 !<39>, <36>, <33>, <30>=RSVD
85
86! cmp %i0, %i2
87! bne %xcc, test_fail
88 nop
89
90soc_err_stat_reg_zeros:
91 stx %g0, [%g5]
92 ldx [%g5], %i0
93
94 cmp %i0, %g0
95 bne %xcc, test_fail
96 nop
97
98soc_err_stat_reg_orig:
99 stx %i1, [%g5]
100
101
102/********************************
103* SOC Error Log Enable Register
104*********************************/
105! Reserved bits related to mcu/sio are still writeable in ELE
106! Fix it?
107!!!!!!!!!!!!!!!!!!!!!!
108
109soc_err_ele_reg:
110 setx SOC_ELE_REG, %l7, %g5
111 setx 0x7ffffffffff, %l7, %i3
112
113soc_err_ele_reg_por:
114 ldx [%g5], %i1
115
116 cmp %i1, %i3 ! All ONEs at reset (por, wrm)
117 bne %xcc, test_fail
118 nop
119
120soc_err_ele_reg_ones:
121 stx %g7, [%g5]
122 ldx [%g5], %i0 ! 4/15: RTL gets 07ffffffffff
123
124! cmp %i0, %i3
125! bne %xcc, test_fail
126 nop
127
128soc_err_ele_reg_zeros:
129 stx %g0, [%g5]
130 ldx [%g5], %i0
131
132 cmp %i0, %g0
133 bne %xcc, test_fail
134 nop
135
136soc_err_ele_reg_orig:
137 stx %i1, [%g5]
138
139
140
141/********************************
142* SOC Error Int Enable Register
143*********************************/
144soc_err_eie_reg:
145 setx SOC_EIE_REG, %l7, %g5
146
147soc_err_eie_reg_por:
148 ldx [%g5], %i1
149
150 cmp %i1, %g0
151 bne %xcc, test_fail
152 nop
153
154soc_err_eie_reg_ones:
155 stx %g7, [%g5]
156 ldx [%g5], %i0 ! 4/15: RTL gets 07ffffffffff
157
158! cmp %i0, %i2
159! bne %xcc, test_fail
160 nop
161
162soc_err_eie_reg_zeros:
163 stx %g0, [%g5]
164 ldx [%g5], %i0
165
166 cmp %i0, %g0
167 bne %xcc, test_fail
168 nop
169
170soc_err_eie_reg_orig:
171 stx %i1, [%g5]
172
173/********************************
174* SOC Error Injection Register
175*********************************/
176soc_err_ejr_reg:
177 setx SOC_EJR_REG, %l7, %g5
178 setx 0xffffffffffefffff, %l7, %g7 ! do not inject <20>; hangs
179
180soc_err_ejr_reg_por:
181 ldx [%g5], %i1
182
183 cmp %i1, %g0
184 bne %xcc, test_fail
185 nop
186
187/*
188causes hang; so not done.
189soc_err_ejr_reg_ones:
190 stx %g7, [%g5]
191 ldx [%g5], %i0
192
193! cmp %i0, %i2
194! bne %xcc, test_fail
195 nop
196*/
197
198soc_err_ejr_reg_zeros:
199 stx %g0, [%g5]
200 ldx [%g5], %i0
201
202 cmp %i0, %g0
203 bne %xcc, test_fail
204 nop
205
206soc_err_ejr_reg_orig:
207 stx %i1, [%g5]
208
209
210/**********************************
211* SOC Fatal Error Enable Register
212***********************************/
213soc_err_fee_reg:
214 setx SOC_FEE_REG, %l7, %g5
215 setx 0xffffffffffffffff, %l7, %g7 ! do not inject <20>; hangs
216
217soc_err_fee_reg_por:
218 ldx [%g5], %i1
219
220 cmp %i1, %g0
221 bne %xcc, test_fail
222 nop
223
224soc_err_fee_reg_ones:
225 stx %g7, [%g5]
226 ldx [%g5], %i0
227
228! cmp %i0, %i2
229! bne %xcc, test_fail
230 nop
231
232soc_err_fee_reg_zeros:
233 stx %g0, [%g5]
234 ldx [%g5], %i0
235
236 cmp %i0, %g0
237 bne %xcc, test_fail
238 nop
239
240soc_err_fee_reg_orig:
241 stx %i1, [%g5]
242
243
244/********************************
245* SOC Pending Error Register
246*********************************/
247soc_err_per_reg:
248 setx SOC_PER_REG, %l7, %g5
249
250soc_err_per_reg_por:
251 ldx [%g5], %i1
252
253 cmp %i1, %g0
254 bne %xcc, test_fail
255 nop
256
257soc_err_per_reg_ones:
258 stx %g7, [%g5]
259 ldx [%g5], %i0
260
261! cmp %i0, %i2
262! bne %xcc, test_fail
263 nop
264
265soc_err_per_reg_zeros:
266 stx %g0, [%g5]
267 ldx [%g5], %i0
268
269 cmp %i0, %g0
270 bne %xcc, test_fail
271 nop
272
273soc_err_per_reg_orig:
274 stx %i1, [%g5]
275
276
277
278/********************************
279* SOC Error SII SYN Register
280*********************************/
281soc_err_sii_synd_reg:
282 setx SOC_SII_SYN_REG, %l7, %g5
283 setx 0x87ffffffffffffff, %l7, %i3 ! <62:59> reserved
284
285soc_err_sii_synd_reg_por:
286 ldx [%g5], %i1
287
288 cmp %i1, %g0
289 bne %xcc, test_fail
290 nop
291
292soc_err_sii_synd_reg_ones:
293 stx %g7, [%g5]
294 ldx [%g5], %i0
295
296 cmp %i0, %i3
297 bne %xcc, test_fail
298 nop
299
300soc_err_sii_synd_reg_zeros:
301 stx %g0, [%g5]
302 ldx [%g5], %i0
303
304 cmp %i0, %g0
305 bne %xcc, test_fail
306 nop
307
308soc_err_sii_synd_reg_orig:
309 stx %i1, [%g5]
310
311/********************************
312* SOC Error NCU SYN Register
313*********************************/
314soc_err_ncu_synd_reg:
315 setx SOC_NCU_SYN_REG, %l7, %g5
316 setx 0xfcffffffffffffff, %l7, %i3 ! <57:56>=reserved
317
318soc_err_ncu_synd_reg_por:
319 ldx [%g5], %i1
320
321 cmp %i1, %g0
322 bne %xcc, test_fail
323 nop
324
325soc_err_ncu_synd_reg_ones:
326 stx %g7, [%g5]
327 ldx [%g5], %i0
328
329 cmp %i0, %i3
330 bne %xcc, test_fail
331 nop
332
333soc_err_ncu_synd_reg_zeros:
334 stx %g0, [%g5]
335 ldx [%g5], %i0
336
337 cmp %i0, %g0
338 bne %xcc, test_fail
339 nop
340
341soc_err_ncu_synd_reg_orig:
342 stx %i1, [%g5]
343
344
345/******************************************************
346 * Exit code
347 *******************************************************/
348
349test_pass:
350EXIT_GOOD
351
352test_fail:
353EXIT_BAD
354
Full OpenSPARC design & verification tarball including full HDL.