[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / ncu / n2_err_ncu_dmu_mondo.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: n2_err_ncu_dmu_mondo.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define H_HT0_Data_access_error_0x32  My_Data_access_error_trap
#define MAIN_PAGE_HV_ALSO

#define H_HT0_Interrupt_0x60
#define My_HT0_Interrupt_0x60 \
        call    my_trap_code; \
        nop; \
        retry; \
        nop;

#include "hboot.s"
#include "peu_defines.h"
#include "ncu_defines.h"
#include "cmp_macros.h"
#include "err_defines.h"

/************************************************************************
   Test case code start
 ************************************************************************/
.text
.global main
.global  My_Data_access_error_trap

main:
        ta T_CHANGE_HPRIV
        nop

clear_esr_first:
        setx    SOC_ESR_REG, %l7, %i0
        stx     %g0, [%i0]

set_ejr:
        set     0x1, %i1
        sllx    %i1, ERR_FIELD, %i2
        setx    SOC_EJR_REG, %l7, %i3
        stx     %i2, [%i3]
        membar  0x40


INT:
        stx     %g0, [%g7]              ! Clear this thread's interrupt count
        membar  #Sync

/*      Initialize the NCU for the interrupt.   */

        ! Disable interrupts

no_intr:
        rdpr    %pstate, %g7
        xor     %g7, 0x2, %g7           ! Reset interrupt enable
        wrpr    %g7, %pstate

        ! Initially set all the Interrupt Management Registers
        ! Not used in this diag, so set vector number to 1, thread to 0.
ncu_init:
        setx    INT_MAN, %g1, %g2       ! %g2 = INT_MAN reg. addr.
        setx    INT_MAN_COUNT, %g1, %g4 ! %g4 = INT_MAN reg. count value
        set     1, %g1

ncu_init_loop_top:
        stx     %g1, [%g2]
        add     %g2, INT_MAN_STEP, %g2
        cmp     %g4, 1
        bne     ncu_init_loop_top
        add     %g4, -1, %g4

        ! Initialize Mondo Interrupt Vector Register
        ! VECTOR = 63

ncu_mondo_int_vec:
        set     63, %g1
        setx    MONDO_INT_VEC, %g2, %g3
        stx     %g1, [%g3]

        ! Clear Mondo Interrupt Busy registers.

ncu_mondo_int_busy:
        setx    MONDO_INT_BUSY, %g1, %g2
        setx    MONDO_INT_BUSY_STEP, %g1, %g3
        setx    MONDO_INT_BUSY_COUNT, %g1, %g4

ncu_mondo_int_busy_loop_top:
        stx     %g0, [%g2]
        add     %g2, %g3, %g2
        cmp     %g4, 1
        bne     ncu_mondo_int_busy_loop_top
        dec     %g4

        ! Initialize for error interrupt in PIU
        ! First clear error in case one pending.

peu_error_clear:
        setx    PCI_E_MMU_ERR_STAT_CL_ADDR, %g1, %g2
        sub     %g0, 1, %g3                     ! W1C
        stx     %g3, [%g2]

        ! Also clear in Interrupt Clear reg.

peu_intr_clear:
        setx    PCI_E_INT_CLEAR_ADDR, %g1, %g2
        setx    PCI_E_INT_CLEAR_MONDO_62_OFFSET, %g1, %g4
        add     %g2, %g4, %g2
        stx     %g0, [%g2]

        ! Now enable Mondo 62 in PIU and set destination thread

peu_mondo62_enable:
        setx    PCI_E_INT_MAP_ADDR, %g1, %g7
        setx    PCI_E_INT_MAP_MONDO_62_OFFSET, %g1, %g3
        add     %g7, %g3, %g7
        setx    0x80000040, %g1, %g6            ! valid = 1, thread id = 0
        stx     %g6, [%g7]                      ! interrupt controller = 1

        ! Enable MMU block mondo 62 interrupts

peu_dmu_error_enable:
        setx    PCI_E_DMU_INT_ENB_ADDR, %g1, %g2
        setx    0x8000000000000002, %g1, %g3    ! DMC = 1, MMU = 1
        stx     %g3, [%g2]

        ! Enable Bypass access with BE = 0 primary error

peu_mmu_error_enable:
        setx    PCI_E_MMU_INT_ENB_ADDR, %g1, %g2
        set     1, %g3
        stx     %g3, [%g2]

        ! Enable interrupts

yes_intr:
        rdpr    %pstate, %g7
        or      %g7, 0x2, %g7           ! Set interrupt enable
        wrpr    %g7, %pstate


        /* Generate the error and therefore the interrupt */

mmu_error_set:
        setx    PCI_E_MMU_ERR_STAT_SET_ADDR, %g1, %g2
        set     1, %g3
        stx     %g3, [%g2]

        /* Wait for two interrupts to occur */

intr_wait_2:
        setx    0x800, %g1, %g2         ! timeout count
        setx    user_data_start, %g1, %g3

intr_wait_loop_top_2:
        ldx     [%g3], %g5
        cmp     %g5, 2
        be      test_passed
        dec     %g2

        cmp     %g2, 0
        bne     intr_wait_loop_top_2
        nop
        ba      test_failed
	nop

	setx	0x10, %l1, %g4
delay_loop:
	nop
	nop
	nop
	nop
	dec	%g4
	brnz	%g4, delay_loop
	nop


err_check:
	nop

  ! Check if a Corrected ECC Trap happened
check_error_trap:
        setx  EXECUTED, %l1, %l0
        cmp   %o0, %l0
        bne   test_failed
        nop
        mov   TT, %l0
        cmp   %i7, %l0
        bne   test_failed
        nop

        /******************************
                Error Check
        ******************************/
read_esr:
        setx    SOC_ESR_REG, %l7, %i0
        ldx     [%i0], %i1
        nop

        setx    0x8000000000000000, %l7, %o3    !valid bit
        set     0x1, %i2
        sllx    %i2, ERR_FIELD, %i3
        or      %i3, %o3, %i4
        sub     %i1, %i4, %i5
        brnz    %i5, test_failed
        nop
        /********************************/
	
test_passed:
	EXIT_GOOD

test_failed:
	EXIT_BAD

My_Data_access_error_trap:
  ! Signal trap taken
  setx  EXECUTED, %l0, %o0
  ! save trap type value
  rdpr  %tt, %i7
  ba  err_check
  nop

/**********************************************************************
   Interrupt trap handler.
**********************************************************************/

.global my_trap_code

my_trap_code:

        ! Get the thread id.
        ta      T_RD_THID               ! %o1 = thread id

        ! Check Mondo Interrupt Busy reg. for this thread

trap_mondo_busy:
        setx    MONDO_INT_BUSY, %l1, %l2
        setx    MONDO_INT_BUSY_STEP, %l1, %l3
        mulx    %l3, %o1, %l3
        add     %l3, %l2, %l2
        ldx     [%l2], %l4
        and     %l4, 0x40, %l5                  ! Is busy bit set?
        cmp     %l5, 0
        be      test_failed
        nop

        ! Check Mondo Interrupt Alias Busy reg.

trap_mondo_abusy:
        setx    MONDO_INT_ABUSY, %l1, %l2
        ldx     [%l2], %l3
        cmp     %l3, %l4                        ! ABUSY = BUSY ?
        bne     test_failed
        nop

        ! Check Mondo Interrupt Data 0/1 against Mondo Interrupt Alias Data 0/1

trap_mondo_data0:
        setx    MONDO_INT_DATA0, %l1, %l2
        setx    MONDO_INT_DATA0_STEP, %l1, %l3
        mulx    %l3, %o1, %l3
        add     %l3, %l2, %l2
        ldx     [%l2], %l0                      ! %l0 = mondo_int_busy0

trap_mondo_adata0:
        setx    MONDO_INT_ADATA0, %l1, %l4      ! %l5 = mondo_int_abusy0
        ldx     [%l4], %l5
        cmp     %l5, %l0
        bne     test_failed
        nop

trap_mondo_data1:
        setx    MONDO_INT_DATA1, %l1, %l2
        setx    MONDO_INT_DATA1_STEP, %l1, %l3
        mulx    %l3, %o1, %l3
        add     %l3, %l2, %l2
        ldx     [%l2], %l0                      ! %l0 = mondo_int_busy1

trap_mondo_adata1:
        setx    MONDO_INT_ADATA1, %l1, %l4      ! %l5 = mondo_int_abusy1
        ldx     [%l4], %l5
        cmp     %l5, %l0
        bne     test_failed
        nop

        ! Check error status in PIU

        ! Interrupt Clear reg.

trap_peu_intr_clear:
        setx    PCI_E_INT_CLEAR_ADDR, %l1, %l2
        setx    PCI_E_INT_CLEAR_MONDO_62_OFFSET, %l1, %l3
        add     %l2, %l3, %l2
        ldx     [%l2], %l0
        cmp     %l0, 3                  ! Should be in pending state
        bne     test_failed
        nop

        ! MMU Interrupt Status reg.

trap_mmu_intr_status:
        setx    PCI_E_MMU_INT_STAT_ADDR, %l1, %l2
        ldx     [%l2], %l0
        cmp     %l0, 1
        bne     test_failed
        nop

        ! MMU Error Status Clear reg.

trap_mmu_err_status_clear:
        setx    PCI_E_MMU_ERR_STAT_CL_ADDR, %l1, %l2
        ldx     [%l2], %l0
        cmp     %l0, 1
        bne     test_failed
        nop

        ! All status checking done.

        ! Only on second interrupt, clear the error, MMU Error Status Set reg.

trap_intr_check:
        setx    user_data_start, %l2, %l6       ! Do not overwrite %l6 !
        ldx     [%l6], %l7                      ! Do not overwrite %l7 !
        cmp     %l7, 1
        bgt     test_failed               ! Should only get 2
        nop
        be      trap_piu_mondo_clear
        nop

        ! Clear error in MMU Error Status Set reg.


trap_clear_error:
        setx    PCI_E_MMU_ERR_STAT_SET_ADDR, %l1, %l2
        stx     %g0, [%l2]
        membar  #Sync
        ldx     [%l2], %g0
        membar  #Sync                           ! Don't be hasty

        ! Clear the error, mondo 62 interrupt in the PIU, via Interrupt Clear reg.

trap_piu_mondo_clear:
        setx    PCI_E_INT_CLEAR_ADDR, %l0, %l2
        setx    PCI_E_INT_CLEAR_MONDO_62_OFFSET, %l1, %l3
        add     %l2, %l3, %l2
        set     1, %l4
        stx     %l4, [%l2]
        membar  #Sync                           ! Don't be hasty

        ! Clear the mondo interrupt in the NCU

trap_mondo_intr_clear:
        setx    MONDO_INT_ABUSY, %l0, %l1
        stx     %g0, [%l1]
        membar  #Sync

        ldx     [%l1], %l2
        and     %l2, 0x40, %l2
        cmp     %l2, 0                  ! Busy should be cleared
        bne     test_failed
        nop
        membar  #Sync                   ! Don't be hasty

        ! Clear the interrupt in the core

trap_clear_asi_intr_r:
        ldxa    [%g0]ASI_SWVR_INTR_R, %l5
        cmp     %l5, 63                 ! check for correct vector number
        bne     test_failed
        nop

        ! Indicate that the interrupt trap occured

trap_flag:
        inc     %l7
        stx     %l7, [%l6]
        membar  #Sync

        ! Done.

trap_done:
        jmpl    %o7+0x8, %g0
        nop

/************************************************************************
   Test case data start
************************************************************************/

.align  1024
.data
user_data_start:
        .word   0xffffffff
        .word   0xffffffff
        .word   0xffffffff
        .word   0xffffffff
user_data_end:
.end
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: n2_err_ncu_dmu_mondo.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define H_HT0_Data_access_error_0x32 My_Data_access_error_trap
	39	#define MAIN_PAGE_HV_ALSO
	40
	41	#define H_HT0_Interrupt_0x60
	42	#define My_HT0_Interrupt_0x60 \
	43	call my_trap_code; \
	44	nop; \
	45	retry; \
	46	nop;
	47
	48	#include "hboot.s"
	49	#include "peu_defines.h"
	50	#include "ncu_defines.h"
	51	#include "cmp_macros.h"
	52	#include "err_defines.h"
	53
	54	/************************************************************************
	55	Test case code start
	56	************************************************************************/
	57	.text
	58	.global main
	59	.global My_Data_access_error_trap
	60
	61	main:
	62	ta T_CHANGE_HPRIV
	63	nop
	64
65	clear_esr_first:
66	setx SOC_ESR_REG, %l7, %i0
67	stx %g0, [%i0]
68
69	set_ejr:
70	set 0x1, %i1
71	sllx %i1, ERR_FIELD, %i2
72	setx SOC_EJR_REG, %l7, %i3
73	stx %i2, [%i3]
74	membar 0x40
75
76
77	INT:
78	stx %g0, [%g7] ! Clear this thread's interrupt count
79	membar #Sync
80
81	/* Initialize the NCU for the interrupt. */
82
83	! Disable interrupts
84
85	no_intr:
86	rdpr %pstate, %g7
87	xor %g7, 0x2, %g7 ! Reset interrupt enable
88	wrpr %g7, %pstate
89
90	! Initially set all the Interrupt Management Registers
91	! Not used in this diag, so set vector number to 1, thread to 0.
92	ncu_init:
93	setx INT_MAN, %g1, %g2 ! %g2 = INT_MAN reg. addr.
94	setx INT_MAN_COUNT, %g1, %g4 ! %g4 = INT_MAN reg. count value
95	set 1, %g1
96
97	ncu_init_loop_top:
98	stx %g1, [%g2]
99	add %g2, INT_MAN_STEP, %g2
100	cmp %g4, 1
101	bne ncu_init_loop_top
102	add %g4, -1, %g4
103
104	! Initialize Mondo Interrupt Vector Register
105	! VECTOR = 63
106
107	ncu_mondo_int_vec:
108	set 63, %g1
109	setx MONDO_INT_VEC, %g2, %g3
110	stx %g1, [%g3]
111
112	! Clear Mondo Interrupt Busy registers.
113
114	ncu_mondo_int_busy:
115	setx MONDO_INT_BUSY, %g1, %g2
116	setx MONDO_INT_BUSY_STEP, %g1, %g3
117	setx MONDO_INT_BUSY_COUNT, %g1, %g4
118
119	ncu_mondo_int_busy_loop_top:
120	stx %g0, [%g2]
121	add %g2, %g3, %g2
122	cmp %g4, 1
123	bne ncu_mondo_int_busy_loop_top
124	dec %g4
125
126	! Initialize for error interrupt in PIU
127	! First clear error in case one pending.
128
129	peu_error_clear:
130	setx PCI_E_MMU_ERR_STAT_CL_ADDR, %g1, %g2
131	sub %g0, 1, %g3 ! W1C
132	stx %g3, [%g2]
133
134	! Also clear in Interrupt Clear reg.
135
136	peu_intr_clear:
137	setx PCI_E_INT_CLEAR_ADDR, %g1, %g2
138	setx PCI_E_INT_CLEAR_MONDO_62_OFFSET, %g1, %g4
139	add %g2, %g4, %g2
140	stx %g0, [%g2]
141
142	! Now enable Mondo 62 in PIU and set destination thread
143
144	peu_mondo62_enable:
145	setx PCI_E_INT_MAP_ADDR, %g1, %g7
146	setx PCI_E_INT_MAP_MONDO_62_OFFSET, %g1, %g3
147	add %g7, %g3, %g7
148	setx 0x80000040, %g1, %g6 ! valid = 1, thread id = 0
149	stx %g6, [%g7] ! interrupt controller = 1
150
151	! Enable MMU block mondo 62 interrupts
152
153	peu_dmu_error_enable:
154	setx PCI_E_DMU_INT_ENB_ADDR, %g1, %g2
155	setx 0x8000000000000002, %g1, %g3 ! DMC = 1, MMU = 1
156	stx %g3, [%g2]
157
158	! Enable Bypass access with BE = 0 primary error
159
160	peu_mmu_error_enable:
161	setx PCI_E_MMU_INT_ENB_ADDR, %g1, %g2
162	set 1, %g3
163	stx %g3, [%g2]
164
165	! Enable interrupts
166
167	yes_intr:
168	rdpr %pstate, %g7
169	or %g7, 0x2, %g7 ! Set interrupt enable
170	wrpr %g7, %pstate
171
172
173	/* Generate the error and therefore the interrupt */
174
175	mmu_error_set:
176	setx PCI_E_MMU_ERR_STAT_SET_ADDR, %g1, %g2
177	set 1, %g3
178	stx %g3, [%g2]
179
180	/* Wait for two interrupts to occur */
181
182	intr_wait_2:
183	setx 0x800, %g1, %g2 ! timeout count
184	setx user_data_start, %g1, %g3
185
186	intr_wait_loop_top_2:
187	ldx [%g3], %g5
188	cmp %g5, 2
189	be test_passed
190	dec %g2
191
192	cmp %g2, 0
193	bne intr_wait_loop_top_2
194	nop
195	ba test_failed
196	nop
197
198	setx 0x10, %l1, %g4
199	delay_loop:
200	nop
201	nop
202	nop
203	nop
204	dec %g4
205	brnz %g4, delay_loop
206	nop
207
208
209	err_check:
210	nop
211
212	! Check if a Corrected ECC Trap happened
213	check_error_trap:
214	setx EXECUTED, %l1, %l0
215	cmp %o0, %l0
216	bne test_failed
217	nop
218	mov TT, %l0
219	cmp %i7, %l0
220	bne test_failed
221	nop
222
223	/******************************
224	Error Check
225	******************************/
226	read_esr:
227	setx SOC_ESR_REG, %l7, %i0
228	ldx [%i0], %i1
229	nop
230
231	setx 0x8000000000000000, %l7, %o3 !valid bit
232	set 0x1, %i2
233	sllx %i2, ERR_FIELD, %i3
234	or %i3, %o3, %i4
235	sub %i1, %i4, %i5
236	brnz %i5, test_failed
237	nop
238	/********************************/
239
240	test_passed:
241	EXIT_GOOD
242
243	test_failed:
244	EXIT_BAD
245
246	My_Data_access_error_trap:
247	! Signal trap taken
248	setx EXECUTED, %l0, %o0
249	! save trap type value
250	rdpr %tt, %i7
251	ba err_check
252	nop
253
254	/**********************************************************************
255	Interrupt trap handler.
256	**********************************************************************/
257
258	.global my_trap_code
259
260	my_trap_code:
261
262	! Get the thread id.
263	ta T_RD_THID ! %o1 = thread id
264
265	! Check Mondo Interrupt Busy reg. for this thread
266
267	trap_mondo_busy:
268	setx MONDO_INT_BUSY, %l1, %l2
269	setx MONDO_INT_BUSY_STEP, %l1, %l3
270	mulx %l3, %o1, %l3
271	add %l3, %l2, %l2
272	ldx [%l2], %l4
273	and %l4, 0x40, %l5 ! Is busy bit set?
274	cmp %l5, 0
275	be test_failed
276	nop
277
278	! Check Mondo Interrupt Alias Busy reg.
279
280	trap_mondo_abusy:
281	setx MONDO_INT_ABUSY, %l1, %l2
282	ldx [%l2], %l3
283	cmp %l3, %l4 ! ABUSY = BUSY ?
284	bne test_failed
285	nop
286
287	! Check Mondo Interrupt Data 0/1 against Mondo Interrupt Alias Data 0/1
288
289	trap_mondo_data0:
290	setx MONDO_INT_DATA0, %l1, %l2
291	setx MONDO_INT_DATA0_STEP, %l1, %l3
292	mulx %l3, %o1, %l3
293	add %l3, %l2, %l2
294	ldx [%l2], %l0 ! %l0 = mondo_int_busy0
295
296	trap_mondo_adata0:
297	setx MONDO_INT_ADATA0, %l1, %l4 ! %l5 = mondo_int_abusy0
298	ldx [%l4], %l5
299	cmp %l5, %l0
300	bne test_failed
301	nop
302
303	trap_mondo_data1:
304	setx MONDO_INT_DATA1, %l1, %l2
305	setx MONDO_INT_DATA1_STEP, %l1, %l3
306	mulx %l3, %o1, %l3
307	add %l3, %l2, %l2
308	ldx [%l2], %l0 ! %l0 = mondo_int_busy1
309
310	trap_mondo_adata1:
311	setx MONDO_INT_ADATA1, %l1, %l4 ! %l5 = mondo_int_abusy1
312	ldx [%l4], %l5
313	cmp %l5, %l0
314	bne test_failed
315	nop
316
317	! Check error status in PIU
318
319	! Interrupt Clear reg.
320
321	trap_peu_intr_clear:
322	setx PCI_E_INT_CLEAR_ADDR, %l1, %l2
323	setx PCI_E_INT_CLEAR_MONDO_62_OFFSET, %l1, %l3
324	add %l2, %l3, %l2
325	ldx [%l2], %l0
326	cmp %l0, 3 ! Should be in pending state
327	bne test_failed
328	nop
329
330	! MMU Interrupt Status reg.
331
332	trap_mmu_intr_status:
333	setx PCI_E_MMU_INT_STAT_ADDR, %l1, %l2
334	ldx [%l2], %l0
335	cmp %l0, 1
336	bne test_failed
337	nop
338
339	! MMU Error Status Clear reg.
340
341	trap_mmu_err_status_clear:
342	setx PCI_E_MMU_ERR_STAT_CL_ADDR, %l1, %l2
343	ldx [%l2], %l0
344	cmp %l0, 1
345	bne test_failed
346	nop
347
348	! All status checking done.
349
350	! Only on second interrupt, clear the error, MMU Error Status Set reg.
351
352	trap_intr_check:
353	setx user_data_start, %l2, %l6 ! Do not overwrite %l6 !
354	ldx [%l6], %l7 ! Do not overwrite %l7 !
355	cmp %l7, 1
356	bgt test_failed ! Should only get 2
357	nop
358	be trap_piu_mondo_clear
359	nop
360
361	! Clear error in MMU Error Status Set reg.
362
363
364	trap_clear_error:
365	setx PCI_E_MMU_ERR_STAT_SET_ADDR, %l1, %l2
366	stx %g0, [%l2]
367	membar #Sync
368	ldx [%l2], %g0
369	membar #Sync ! Don't be hasty
370
371	! Clear the error, mondo 62 interrupt in the PIU, via Interrupt Clear reg.
372
373	trap_piu_mondo_clear:
374	setx PCI_E_INT_CLEAR_ADDR, %l0, %l2
375	setx PCI_E_INT_CLEAR_MONDO_62_OFFSET, %l1, %l3
376	add %l2, %l3, %l2
377	set 1, %l4
378	stx %l4, [%l2]
379	membar #Sync ! Don't be hasty
380
381	! Clear the mondo interrupt in the NCU
382
383	trap_mondo_intr_clear:
384	setx MONDO_INT_ABUSY, %l0, %l1
385	stx %g0, [%l1]
386	membar #Sync
387
388	ldx [%l1], %l2
389	and %l2, 0x40, %l2
390	cmp %l2, 0 ! Busy should be cleared
391	bne test_failed
392	nop
393	membar #Sync ! Don't be hasty
394
395	! Clear the interrupt in the core
396
397	trap_clear_asi_intr_r:
398	ldxa [%g0]ASI_SWVR_INTR_R, %l5
399	cmp %l5, 63 ! check for correct vector number
400	bne test_failed
401	nop
402
403	! Indicate that the interrupt trap occured
404
405	trap_flag:
406	inc %l7
407	stx %l7, [%l6]
408	membar #Sync
409
410	! Done.
411
412	trap_done:
413	jmpl %o7+0x8, %g0
414	nop
415
416	/************************************************************************
417	Test case data start
418	************************************************************************/
419
420	.align 1024
421	.data
422	user_data_start:
423	.word 0xffffffff
424	.word 0xffffffff
425	.word 0xffffffff
426	.word 0xffffffff
427	user_data_end:
428	.end
429