[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / ncu / n2_err_ncu_dmu_mondo_2th.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: n2_err_ncu_dmu_mondo_2th.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define MAIN_PAGE_HV_ALSO

#define H_HT0_Interrupt_0x60
#define My_HT0_Interrupt_0x60 \
        call    my_trap_code; \
        nop; \
        retry; \
        nop;

#include "hboot.s"
#include "peu_defines.h"
#include "ncu_defines.h"
#include "cmp_macros.h"
#include "err_defines.h"

/************************************************************************
   Test case code start
 ************************************************************************/
.text
.global main

main:
        ta T_CHANGE_HPRIV
        nop

get_th_id_o0:
        ta      T_RD_THID

        cmp     %o1, 0x0
        be      main_t0
        nop

        cmp     %o1, 0x1
        be      main_t1
        nop

        /**************************************
                THREAD 0
        **************************************/
main_t0:
        nop

clear_esr_first:
        setx    SOC_ESR_REG, %l7, %i0
        stx     %g0, [%i0]

        /**********************************************
                RAS
        ***********************************************/
set_ejr:
        set     0x1, %i1
        sllx    %i1, ERR_FIELD, %i2
        setx    SOC_EJR_REG, %l7, %i3
        stx     %i2, [%i3]
        membar  0x40
        /**********************************************/

INT:
        stx     %g0, [%g7]              ! Clear this thread's interrupt count
        membar  #Sync

/*      Initialize the NCU for the interrupt.   */

        ! Disable interrupts

no_intr:
        rdpr    %pstate, %g7
        xor     %g7, 0x2, %g7           ! Reset interrupt enable
        wrpr    %g7, %pstate

        ! Initially set all the Interrupt Management Registers
        ! Not used in this diag, so set vector number to 1, thread to 0.
ncu_init:
        setx    INT_MAN, %g1, %g2       ! %g2 = INT_MAN reg. addr.
        setx    INT_MAN_COUNT, %g1, %g4 ! %g4 = INT_MAN reg. count value
        set     1, %g1

ncu_init_loop_top:
        stx     %g1, [%g2]
        add     %g2, INT_MAN_STEP, %g2
        cmp     %g4, 1
        bne     ncu_init_loop_top
        add     %g4, -1, %g4

        ! Initialize Mondo Interrupt Vector Register
        ! VECTOR = 63

ncu_mondo_int_vec:
        set     63, %g1
        setx    MONDO_INT_VEC, %g2, %g3
        stx     %g1, [%g3]

        ! Clear Mondo Interrupt Busy registers.

ncu_mondo_int_busy:
        setx    MONDO_INT_BUSY, %g1, %g2
        setx    MONDO_INT_BUSY_STEP, %g1, %g3
        setx    MONDO_INT_BUSY_COUNT, %g1, %g4

ncu_mondo_int_busy_loop_top:
        stx     %g0, [%g2]
        add     %g2, %g3, %g2
        cmp     %g4, 1
        bne     ncu_mondo_int_busy_loop_top
        dec     %g4

        ! Initialize for error interrupt in PIU
        ! First clear error in case one pending.

peu_error_clear:
        setx    PCI_E_MMU_ERR_STAT_CL_ADDR, %g1, %g2
        sub     %g0, 1, %g3                     ! W1C
        stx     %g3, [%g2]

        ! Also clear in Interrupt Clear reg.

peu_intr_clear:
        setx    PCI_E_INT_CLEAR_ADDR, %g1, %g2
        setx    PCI_E_INT_CLEAR_MONDO_62_OFFSET, %g1, %g4
        add     %g2, %g4, %g2
        stx     %g0, [%g2]

        ! Now enable Mondo 62 in PIU and set destination thread

peu_mondo62_enable:
        setx    PCI_E_INT_MAP_ADDR, %g1, %g7
        setx    PCI_E_INT_MAP_MONDO_62_OFFSET, %g1, %g3
        add     %g7, %g3, %g7
        setx    0x80000040, %g1, %g6            ! valid = 1, thread id = 0
        stx     %g6, [%g7]                      ! interrupt controller = 1

        ! Enable MMU block mondo 62 interrupts


peu_dmu_error_enable:
        setx    PCI_E_DMU_INT_ENB_ADDR, %g1, %g2
        setx    0x8000000000000002, %g1, %g3    ! DMC = 1, MMU = 1
        stx     %g3, [%g2]

        ! Enable Bypass access with BE = 0 primary error

peu_mmu_error_enable:
        setx    PCI_E_MMU_INT_ENB_ADDR, %g1, %g2
        set     1, %g3
        stx     %g3, [%g2]

        ! Enable interrupts

yes_intr:
        rdpr    %pstate, %g7
        or      %g7, 0x2, %g7           ! Set interrupt enable
        wrpr    %g7, %pstate


        /* Generate the error and therefore the interrupt */

mmu_error_set:
        setx    PCI_E_MMU_ERR_STAT_SET_ADDR, %g1, %g2
        set     1, %g3
        stx     %g3, [%g2]

        /* Wait for two interrupts to occur */

intr_wait_2:
        setx    0x800, %g1, %g2         ! timeout count
        setx    user_data_start, %g1, %g3

intr_wait_loop_top_2:
        ldx     [%g3], %g5
        cmp     %g5, 2
        be      test_passed
        dec     %g2

        cmp     %g2, 0
        bne     intr_wait_loop_top_2
        nop
        ba      test_failed
	nop

	setx	0x10, %l1, %g4
delay_loop:
	nop
	nop
	nop
	nop
	dec	%g4
	brnz	%g4, delay_loop
	nop


        /**************************************
                THREAD 1
        **************************************/
main_t1:
        nop

        setx    SOC_EJR_REG, %l7, %i3
        setx     0x1000, %l7, %g1
read_ejr:
	dec	%g1
        cmp     %g1, %g0
        be      %xcc, test_failed       ! Timeout check
        nop

        ldx     [%i3], %o2
        cmp     %o2, %g0
        be      %xcc, read_ejr
        nop

        setx     0x400, %l7, %g1
read_esr:
	dec 	%g1
        cmp     %g1, %g0
        be      %xcc, test_failed       ! Timeout check
        nop

        setx    SOC_ESR_REG, %l7, %i3
        ldx     [%i3], %o2

        cmp     %o2, %g0
        be      %xcc, read_esr
        nop

        setx    0x8000000000000000, %l7, %o3    !valid bit
        set     0x1, %i2
        sllx    %i2, ERR_FIELD, %i3
        or      %i3, %o3, %i4
        sub     %o2, %i4, %i5
        brnz    %i5, test_failed
        nop


test_passed:
	EXIT_GOOD

test_failed:
	EXIT_BAD


/**********************************************************************
   Interrupt trap handler.
**********************************************************************/

.global my_trap_code

my_trap_code:

        ! Get the thread id.
        ta      T_RD_THID               ! %o1 = thread id

        ! Check Mondo Interrupt Busy reg. for this thread

trap_mondo_busy:
        setx    MONDO_INT_BUSY, %l1, %l2
        setx    MONDO_INT_BUSY_STEP, %l1, %l3
        mulx    %l3, %o1, %l3
        add     %l3, %l2, %l2
        ldx     [%l2], %l4
        and     %l4, 0x40, %l5                  ! Is busy bit set?
        cmp     %l5, 0
        be      test_failed
        nop

        ! Check Mondo Interrupt Alias Busy reg.

trap_mondo_abusy:
        setx    MONDO_INT_ABUSY, %l1, %l2
        ldx     [%l2], %l3
        cmp     %l3, %l4                        ! ABUSY = BUSY ?
        bne     test_failed
        nop

        ! Check Mondo Interrupt Data 0/1 against Mondo Interrupt Alias Data 0/1

trap_mondo_data0:
        setx    MONDO_INT_DATA0, %l1, %l2
        setx    MONDO_INT_DATA0_STEP, %l1, %l3
        mulx    %l3, %o1, %l3
        add     %l3, %l2, %l2
        ldx     [%l2], %l0                      ! %l0 = mondo_int_busy0

trap_mondo_adata0:
        setx    MONDO_INT_ADATA0, %l1, %l4      ! %l5 = mondo_int_abusy0
        ldx     [%l4], %l5
        cmp     %l5, %l0
        bne     test_failed
        nop

trap_mondo_data1:
        setx    MONDO_INT_DATA1, %l1, %l2
        setx    MONDO_INT_DATA1_STEP, %l1, %l3
        mulx    %l3, %o1, %l3
        add     %l3, %l2, %l2
        ldx     [%l2], %l0                      ! %l0 = mondo_int_busy1

trap_mondo_adata1:
        setx    MONDO_INT_ADATA1, %l1, %l4      ! %l5 = mondo_int_abusy1
        ldx     [%l4], %l5
        cmp     %l5, %l0
        bne     test_failed
        nop

        ! Check error status in PIU

        ! Interrupt Clear reg.

trap_peu_intr_clear:
        setx    PCI_E_INT_CLEAR_ADDR, %l1, %l2
        setx    PCI_E_INT_CLEAR_MONDO_62_OFFSET, %l1, %l3
        add     %l2, %l3, %l2
        ldx     [%l2], %l0
        cmp     %l0, 3                  ! Should be in pending state
        bne     test_failed
        nop

        ! MMU Interrupt Status reg.

trap_mmu_intr_status:
        setx    PCI_E_MMU_INT_STAT_ADDR, %l1, %l2
        ldx     [%l2], %l0
        cmp     %l0, 1
        bne     test_failed
        nop

        ! MMU Error Status Clear reg.

trap_mmu_err_status_clear:
        setx    PCI_E_MMU_ERR_STAT_CL_ADDR, %l1, %l2
        ldx     [%l2], %l0
        cmp     %l0, 1
        bne     test_failed
        nop

        ! All status checking done.

        ! Only on second interrupt, clear the error, MMU Error Status Set reg.

trap_intr_check:
        setx    user_data_start, %l2, %l6       ! Do not overwrite %l6 !
        ldx     [%l6], %l7                      ! Do not overwrite %l7 !
        cmp     %l7, 1
        bgt     test_failed               ! Should only get 2
        nop
        be      trap_piu_mondo_clear
        nop

        ! Clear error in MMU Error Status Set reg.


trap_clear_error:
        setx    PCI_E_MMU_ERR_STAT_SET_ADDR, %l1, %l2
        stx     %g0, [%l2]
        membar  #Sync
        ldx     [%l2], %g0
        membar  #Sync                           ! Don't be hasty

        ! Clear the error, mondo 62 interrupt in the PIU, via Interrupt Clear reg.

trap_piu_mondo_clear:
        setx    PCI_E_INT_CLEAR_ADDR, %l0, %l2
        setx    PCI_E_INT_CLEAR_MONDO_62_OFFSET, %l1, %l3
        add     %l2, %l3, %l2
        set     1, %l4
        stx     %l4, [%l2]
        membar  #Sync                           ! Don't be hasty

        ! Clear the mondo interrupt in the NCU

trap_mondo_intr_clear:
        setx    MONDO_INT_ABUSY, %l0, %l1
        stx     %g0, [%l1]
        membar  #Sync

        ldx     [%l1], %l2
        and     %l2, 0x40, %l2
        cmp     %l2, 0                  ! Busy should be cleared
        bne     test_failed
        nop
        membar  #Sync                   ! Don't be hasty

        ! Clear the interrupt in the core

trap_clear_asi_intr_r:
        ldxa    [%g0]ASI_SWVR_INTR_R, %l5
        cmp     %l5, 63                 ! check for correct vector number
        bne     test_failed
        nop

        ! Indicate that the interrupt trap occured

trap_flag:
        inc     %l7
        stx     %l7, [%l6]
        membar  #Sync

        ! Done.

trap_done:
        jmpl    %o7+0x8, %g0
        nop

/************************************************************************
   Test case data start
************************************************************************/

.align  1024
.data
user_data_start:
        .word   0xffffffff
        .word   0xffffffff
        .word   0xffffffff
        .word   0xffffffff
user_data_end:
.end
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: n2_err_ncu_dmu_mondo_2th.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define MAIN_PAGE_HV_ALSO
	39
	40	#define H_HT0_Interrupt_0x60
	41	#define My_HT0_Interrupt_0x60 \
	42	call my_trap_code; \
	43	nop; \
	44	retry; \
	45	nop;
	46
	47	#include "hboot.s"
	48	#include "peu_defines.h"
	49	#include "ncu_defines.h"
	50	#include "cmp_macros.h"
	51	#include "err_defines.h"
	52
	53	/************************************************************************
	54	Test case code start
	55	************************************************************************/
	56	.text
	57	.global main
	58
	59	main:
	60	ta T_CHANGE_HPRIV
	61	nop
	62
	63	get_th_id_o0:
	64	ta T_RD_THID
65
66	cmp %o1, 0x0
67	be main_t0
68	nop
69
70	cmp %o1, 0x1
71	be main_t1
72	nop
73
74	/**************************************
75	THREAD 0
76	**************************************/
77	main_t0:
78	nop
79
80	clear_esr_first:
81	setx SOC_ESR_REG, %l7, %i0
82	stx %g0, [%i0]
83
84	/**********************************************
85	RAS
86	***********************************************/
87	set_ejr:
88	set 0x1, %i1
89	sllx %i1, ERR_FIELD, %i2
90	setx SOC_EJR_REG, %l7, %i3
91	stx %i2, [%i3]
92	membar 0x40
93	/**********************************************/
94
95	INT:
96	stx %g0, [%g7] ! Clear this thread's interrupt count
97	membar #Sync
98
99	/* Initialize the NCU for the interrupt. */
100
101	! Disable interrupts
102
103	no_intr:
104	rdpr %pstate, %g7
105	xor %g7, 0x2, %g7 ! Reset interrupt enable
106	wrpr %g7, %pstate
107
108	! Initially set all the Interrupt Management Registers
109	! Not used in this diag, so set vector number to 1, thread to 0.
110	ncu_init:
111	setx INT_MAN, %g1, %g2 ! %g2 = INT_MAN reg. addr.
112	setx INT_MAN_COUNT, %g1, %g4 ! %g4 = INT_MAN reg. count value
113	set 1, %g1
114
115	ncu_init_loop_top:
116	stx %g1, [%g2]
117	add %g2, INT_MAN_STEP, %g2
118	cmp %g4, 1
119	bne ncu_init_loop_top
120	add %g4, -1, %g4
121
122	! Initialize Mondo Interrupt Vector Register
123	! VECTOR = 63
124
125	ncu_mondo_int_vec:
126	set 63, %g1
127	setx MONDO_INT_VEC, %g2, %g3
128	stx %g1, [%g3]
129
130	! Clear Mondo Interrupt Busy registers.
131
132	ncu_mondo_int_busy:
133	setx MONDO_INT_BUSY, %g1, %g2
134	setx MONDO_INT_BUSY_STEP, %g1, %g3
135	setx MONDO_INT_BUSY_COUNT, %g1, %g4
136
137	ncu_mondo_int_busy_loop_top:
138	stx %g0, [%g2]
139	add %g2, %g3, %g2
140	cmp %g4, 1
141	bne ncu_mondo_int_busy_loop_top
142	dec %g4
143
144	! Initialize for error interrupt in PIU
145	! First clear error in case one pending.
146
147	peu_error_clear:
148	setx PCI_E_MMU_ERR_STAT_CL_ADDR, %g1, %g2
149	sub %g0, 1, %g3 ! W1C
150	stx %g3, [%g2]
151
152	! Also clear in Interrupt Clear reg.
153
154	peu_intr_clear:
155	setx PCI_E_INT_CLEAR_ADDR, %g1, %g2
156	setx PCI_E_INT_CLEAR_MONDO_62_OFFSET, %g1, %g4
157	add %g2, %g4, %g2
158	stx %g0, [%g2]
159
160	! Now enable Mondo 62 in PIU and set destination thread
161
162	peu_mondo62_enable:
163	setx PCI_E_INT_MAP_ADDR, %g1, %g7
164	setx PCI_E_INT_MAP_MONDO_62_OFFSET, %g1, %g3
165	add %g7, %g3, %g7
166	setx 0x80000040, %g1, %g6 ! valid = 1, thread id = 0
167	stx %g6, [%g7] ! interrupt controller = 1
168
169	! Enable MMU block mondo 62 interrupts
170
171
172	peu_dmu_error_enable:
173	setx PCI_E_DMU_INT_ENB_ADDR, %g1, %g2
174	setx 0x8000000000000002, %g1, %g3 ! DMC = 1, MMU = 1
175	stx %g3, [%g2]
176
177	! Enable Bypass access with BE = 0 primary error
178
179	peu_mmu_error_enable:
180	setx PCI_E_MMU_INT_ENB_ADDR, %g1, %g2
181	set 1, %g3
182	stx %g3, [%g2]
183
184	! Enable interrupts
185
186	yes_intr:
187	rdpr %pstate, %g7
188	or %g7, 0x2, %g7 ! Set interrupt enable
189	wrpr %g7, %pstate
190
191
192	/* Generate the error and therefore the interrupt */
193
194	mmu_error_set:
195	setx PCI_E_MMU_ERR_STAT_SET_ADDR, %g1, %g2
196	set 1, %g3
197	stx %g3, [%g2]
198
199	/* Wait for two interrupts to occur */
200
201	intr_wait_2:
202	setx 0x800, %g1, %g2 ! timeout count
203	setx user_data_start, %g1, %g3
204
205	intr_wait_loop_top_2:
206	ldx [%g3], %g5
207	cmp %g5, 2
208	be test_passed
209	dec %g2
210
211	cmp %g2, 0
212	bne intr_wait_loop_top_2
213	nop
214	ba test_failed
215	nop
216
217	setx 0x10, %l1, %g4
218	delay_loop:
219	nop
220	nop
221	nop
222	nop
223	dec %g4
224	brnz %g4, delay_loop
225	nop
226
227
228	/**************************************
229	THREAD 1
230	**************************************/
231	main_t1:
232	nop
233
234	setx SOC_EJR_REG, %l7, %i3
235	setx 0x1000, %l7, %g1
236	read_ejr:
237	dec %g1
238	cmp %g1, %g0
239	be %xcc, test_failed ! Timeout check
240	nop
241
242	ldx [%i3], %o2
243	cmp %o2, %g0
244	be %xcc, read_ejr
245	nop
246
247	setx 0x400, %l7, %g1
248	read_esr:
249	dec %g1
250	cmp %g1, %g0
251	be %xcc, test_failed ! Timeout check
252	nop
253
254	setx SOC_ESR_REG, %l7, %i3
255	ldx [%i3], %o2
256
257	cmp %o2, %g0
258	be %xcc, read_esr
259	nop
260
261	setx 0x8000000000000000, %l7, %o3 !valid bit
262	set 0x1, %i2
263	sllx %i2, ERR_FIELD, %i3
264	or %i3, %o3, %i4
265	sub %o2, %i4, %i5
266	brnz %i5, test_failed
267	nop
268
269
270	test_passed:
271	EXIT_GOOD
272
273	test_failed:
274	EXIT_BAD
275
276
277	/**********************************************************************
278	Interrupt trap handler.
279	**********************************************************************/
280
281	.global my_trap_code
282
283	my_trap_code:
284
285	! Get the thread id.
286	ta T_RD_THID ! %o1 = thread id
287
288	! Check Mondo Interrupt Busy reg. for this thread
289
290	trap_mondo_busy:
291	setx MONDO_INT_BUSY, %l1, %l2
292	setx MONDO_INT_BUSY_STEP, %l1, %l3
293	mulx %l3, %o1, %l3
294	add %l3, %l2, %l2
295	ldx [%l2], %l4
296	and %l4, 0x40, %l5 ! Is busy bit set?
297	cmp %l5, 0
298	be test_failed
299	nop
300
301	! Check Mondo Interrupt Alias Busy reg.
302
303	trap_mondo_abusy:
304	setx MONDO_INT_ABUSY, %l1, %l2
305	ldx [%l2], %l3
306	cmp %l3, %l4 ! ABUSY = BUSY ?
307	bne test_failed
308	nop
309
310	! Check Mondo Interrupt Data 0/1 against Mondo Interrupt Alias Data 0/1
311
312	trap_mondo_data0:
313	setx MONDO_INT_DATA0, %l1, %l2
314	setx MONDO_INT_DATA0_STEP, %l1, %l3
315	mulx %l3, %o1, %l3
316	add %l3, %l2, %l2
317	ldx [%l2], %l0 ! %l0 = mondo_int_busy0
318
319	trap_mondo_adata0:
320	setx MONDO_INT_ADATA0, %l1, %l4 ! %l5 = mondo_int_abusy0
321	ldx [%l4], %l5
322	cmp %l5, %l0
323	bne test_failed
324	nop
325
326	trap_mondo_data1:
327	setx MONDO_INT_DATA1, %l1, %l2
328	setx MONDO_INT_DATA1_STEP, %l1, %l3
329	mulx %l3, %o1, %l3
330	add %l3, %l2, %l2
331	ldx [%l2], %l0 ! %l0 = mondo_int_busy1
332
333	trap_mondo_adata1:
334	setx MONDO_INT_ADATA1, %l1, %l4 ! %l5 = mondo_int_abusy1
335	ldx [%l4], %l5
336	cmp %l5, %l0
337	bne test_failed
338	nop
339
340	! Check error status in PIU
341
342	! Interrupt Clear reg.
343
344	trap_peu_intr_clear:
345	setx PCI_E_INT_CLEAR_ADDR, %l1, %l2
346	setx PCI_E_INT_CLEAR_MONDO_62_OFFSET, %l1, %l3
347	add %l2, %l3, %l2
348	ldx [%l2], %l0
349	cmp %l0, 3 ! Should be in pending state
350	bne test_failed
351	nop
352
353	! MMU Interrupt Status reg.
354
355	trap_mmu_intr_status:
356	setx PCI_E_MMU_INT_STAT_ADDR, %l1, %l2
357	ldx [%l2], %l0
358	cmp %l0, 1
359	bne test_failed
360	nop
361
362	! MMU Error Status Clear reg.
363
364	trap_mmu_err_status_clear:
365	setx PCI_E_MMU_ERR_STAT_CL_ADDR, %l1, %l2
366	ldx [%l2], %l0
367	cmp %l0, 1
368	bne test_failed
369	nop
370
371	! All status checking done.
372
373	! Only on second interrupt, clear the error, MMU Error Status Set reg.
374
375	trap_intr_check:
376	setx user_data_start, %l2, %l6 ! Do not overwrite %l6 !
377	ldx [%l6], %l7 ! Do not overwrite %l7 !
378	cmp %l7, 1
379	bgt test_failed ! Should only get 2
380	nop
381	be trap_piu_mondo_clear
382	nop
383
384	! Clear error in MMU Error Status Set reg.
385
386
387	trap_clear_error:
388	setx PCI_E_MMU_ERR_STAT_SET_ADDR, %l1, %l2
389	stx %g0, [%l2]
390	membar #Sync
391	ldx [%l2], %g0
392	membar #Sync ! Don't be hasty
393
394	! Clear the error, mondo 62 interrupt in the PIU, via Interrupt Clear reg.
395
396	trap_piu_mondo_clear:
397	setx PCI_E_INT_CLEAR_ADDR, %l0, %l2
398	setx PCI_E_INT_CLEAR_MONDO_62_OFFSET, %l1, %l3
399	add %l2, %l3, %l2
400	set 1, %l4
401	stx %l4, [%l2]
402	membar #Sync ! Don't be hasty
403
404	! Clear the mondo interrupt in the NCU
405
406	trap_mondo_intr_clear:
407	setx MONDO_INT_ABUSY, %l0, %l1
408	stx %g0, [%l1]
409	membar #Sync
410
411	ldx [%l1], %l2
412	and %l2, 0x40, %l2
413	cmp %l2, 0 ! Busy should be cleared
414	bne test_failed
415	nop
416	membar #Sync ! Don't be hasty
417
418	! Clear the interrupt in the core
419
420	trap_clear_asi_intr_r:
421	ldxa [%g0]ASI_SWVR_INTR_R, %l5
422	cmp %l5, 63 ! check for correct vector number
423	bne test_failed
424	nop
425
426	! Indicate that the interrupt trap occured
427
428	trap_flag:
429	inc %l7
430	stx %l7, [%l6]
431	membar #Sync
432
433	! Done.
434
435	trap_done:
436	jmpl %o7+0x8, %g0
437	nop
438
439	/************************************************************************
440	Test case data start
441	************************************************************************/
442
443	.align 1024
444	.data
445	user_data_start:
446	.word 0xffffffff
447	.word 0xffffffff
448	.word 0xffffffff
449	.word 0xffffffff
450	user_data_end:
451	.end
452