[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / siu / n2_err_siu_dmu.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: n2_err_siu_dmu.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define MAIN_PAGE_HV_ALSO

#include "err_defines.h"
#include "hboot.s"
#include "peu_defines.h"
!#include "dmu_peu_regs.h"

#define CFG_RD_ADDR mpeval(N2_PCIE_BASE_ADDR + IOCFG_OFFSET_MASK_REG_DATA)
#define CFG_RD_DATA 64'h33323130


/************************************************************************
   Test case code start
 ************************************************************************/
.text
.global main

main:
        ta T_CHANGE_HPRIV
        nop

#include "peu_init.h"
!
! Thread 0 Start
!
!
thread_0:
CONFIGURE_NCU_FOR_PCIE_TRAFFIC:
        setx    IOCFG_OFFSET_BASE_REG_ADDR, %g1, %g2
        setx    IOCFG_OFFSET_BASE_REG_DATA, %g1, %g3
        stx     %g3, [%g2]
        nop
        ldx     [%g2], %g4
        nop

        setx    IOCFG_OFFSET_MASK_REG_ADDR, %g1, %g2
        setx    IOCFG_OFFSET_MASK_REG_DATA, %g1, %g3
        stx     %g3, [%g2]
        nop
        ldx     [%g2], %g4
        nop

	! enable bypass in IOMMU
	setx	FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
	setx	FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
	stx	%g3, [%g2]
	ldx	[%g2], %g3


set_ejr:
        set     0x1, %i1
        sllx    %i1, ERR_FIELD, %i2
        setx    SOC_EJR_REG, %l7, %i3
        stx     %i2, [%i3]
        membar  0x40
	
XmtUsrEvnt:
	nop         ! $EV trig_pc_d(1, @VA(.MAIN.XmtUsrEvnt)) -> EnablePCIeIgCmd ("DMAWR", IOMMU_BYP_SADDR, IOMMU_BYP_SADDR, 64'h40, 64'd1 )

XmtCmd:
	! select a CFG address in PCI address range and transmit the command to NCU
	setx CFG_RD_ADDR, %g1, %g2
	nop
	
	setx	FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR, %g1, %g2
	setx	0x020, %g1, %g4


delay_loop:
	ldx	[%g2], %g5
	nop
	nop
	nop
	nop
	dec	%g4
	brnz	%g4, delay_loop
	nop

        setx    SOC_ESR_REG, %l7, %i0
        ldx     [%i0], %i1
        nop

check_esr:
        setx    0x8000000000000000, %l7, %o3    !valid bit
        set     0x1, %i2
        sllx    %i2, ERR_FIELD, %i3
        or      %i3, %o3, %i4
        sub     %i1, %i4, %i5
        brnz    %i5, test_failed
        nop

	
test_passed:
	EXIT_GOOD

test_failed:
	EXIT_BAD


/************************************************************************
   Test case data start
 ************************************************************************/

/************************************************************************/
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: n2_err_siu_dmu.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define MAIN_PAGE_HV_ALSO
	39
	40	#include "err_defines.h"
	41	#include "hboot.s"
	42	#include "peu_defines.h"
	43	!#include "dmu_peu_regs.h"
	44
	45	#define CFG_RD_ADDR mpeval(N2_PCIE_BASE_ADDR + IOCFG_OFFSET_MASK_REG_DATA)
	46	#define CFG_RD_DATA 64'h33323130
	47
	48
	49	/************************************************************************
	50	Test case code start
	51	************************************************************************/
	52	.text
	53	.global main
	54
	55	main:
	56	ta T_CHANGE_HPRIV
	57	nop
	58
	59	#include "peu_init.h"
	60	!
	61	! Thread 0 Start
	62	!
	63	!
	64	thread_0:
65	CONFIGURE_NCU_FOR_PCIE_TRAFFIC:
66	setx IOCFG_OFFSET_BASE_REG_ADDR, %g1, %g2
67	setx IOCFG_OFFSET_BASE_REG_DATA, %g1, %g3
68	stx %g3, [%g2]
69	nop
70	ldx [%g2], %g4
71	nop
72
73	setx IOCFG_OFFSET_MASK_REG_ADDR, %g1, %g2
74	setx IOCFG_OFFSET_MASK_REG_DATA, %g1, %g3
75	stx %g3, [%g2]
76	nop
77	ldx [%g2], %g4
78	nop
79
80	! enable bypass in IOMMU
81	setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
82	setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
83	stx %g3, [%g2]
84	ldx [%g2], %g3
85
86
87	set_ejr:
88	set 0x1, %i1
89	sllx %i1, ERR_FIELD, %i2
90	setx SOC_EJR_REG, %l7, %i3
91	stx %i2, [%i3]
92	membar 0x40
93
94	XmtUsrEvnt:
95	nop ! $EV trig_pc_d(1, @VA(.MAIN.XmtUsrEvnt)) -> EnablePCIeIgCmd ("DMAWR", IOMMU_BYP_SADDR, IOMMU_BYP_SADDR, 64'h40, 64'd1 )
96
97	XmtCmd:
98	! select a CFG address in PCI address range and transmit the command to NCU
99	setx CFG_RD_ADDR, %g1, %g2
100	nop
101
102	setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR, %g1, %g2
103	setx 0x020, %g1, %g4
104
105
106	delay_loop:
107	ldx [%g2], %g5
108	nop
109	nop
110	nop
111	nop
112	dec %g4
113	brnz %g4, delay_loop
114	nop
115
116	setx SOC_ESR_REG, %l7, %i0
117	ldx [%i0], %i1
118	nop
119
120	check_esr:
121	setx 0x8000000000000000, %l7, %o3 !valid bit
122	set 0x1, %i2
123	sllx %i2, ERR_FIELD, %i3
124	or %i3, %o3, %i4
125	sub %i1, %i4, %i5
126	brnz %i5, test_failed
127	nop
128
129
130	test_passed:
131	EXIT_GOOD
132
133	test_failed:
134	EXIT_BAD
135
136
137	/************************************************************************
138	Test case data start
139	************************************************************************/
140
141	/************************************************************************/
142