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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: n2_err_siu_dmu_trap.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap | |
39 | #define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap | |
40 | ||
41 | ||
42 | ||
43 | /* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */ | |
44 | #define MAIN_PAGE_HV_ALSO | |
45 | ||
46 | #include "err_defines.h" | |
47 | #include "hboot.s" | |
48 | #include "peu_defines.h" | |
49 | !#include "dmu_peu_regs.h" | |
50 | ||
51 | #define CFG_RD_ADDR mpeval(N2_PCIE_BASE_ADDR + IOCFG_OFFSET_MASK_REG_DATA) | |
52 | #define CFG_RD_DATA 64'h33323130 | |
53 | ||
54 | ||
55 | /************************************************************************ | |
56 | Test case code start | |
57 | ************************************************************************/ | |
58 | .text | |
59 | .global main | |
60 | .global My_Corrected_ECC_error_trap | |
61 | .global My_Recoverable_Sw_error_trap | |
62 | ||
63 | main: | |
64 | ta T_CHANGE_HPRIV | |
65 | nop | |
66 | ||
67 | #include "peu_init.h" | |
68 | ! | |
69 | ! Thread 0 Start | |
70 | ! | |
71 | ! | |
72 | thread_0: | |
73 | CONFIGURE_NCU_FOR_PCIE_TRAFFIC: | |
74 | setx IOCFG_OFFSET_BASE_REG_ADDR, %g1, %g2 | |
75 | setx IOCFG_OFFSET_BASE_REG_DATA, %g1, %g3 | |
76 | stx %g3, [%g2] | |
77 | nop | |
78 | ldx [%g2], %g4 | |
79 | nop | |
80 | ||
81 | setx IOCFG_OFFSET_MASK_REG_ADDR, %g1, %g2 | |
82 | setx IOCFG_OFFSET_MASK_REG_DATA, %g1, %g3 | |
83 | stx %g3, [%g2] | |
84 | nop | |
85 | ldx [%g2], %g4 | |
86 | nop | |
87 | ||
88 | ! enable bypass in IOMMU | |
89 | setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2 | |
90 | setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3 | |
91 | stx %g3, [%g2] | |
92 | ldx [%g2], %g3 | |
93 | ||
94 | ||
95 | set_ejr: | |
96 | set 0x1, %i1 | |
97 | sllx %i1, ERR_FIELD, %i2 | |
98 | setx SOC_EJR_REG, %l7, %i3 | |
99 | stx %i2, [%i3] | |
100 | membar 0x40 | |
101 | ||
102 | eie_reg_ones: | |
103 | setx SOC_EIE_REG, %l7, %g5 | |
104 | stx %i2, [%g5] | |
105 | membar 0x40 | |
106 | ||
107 | ||
108 | XmtUsrEvnt: | |
109 | nop ! $EV trig_pc_d(1, @VA(.MAIN.XmtUsrEvnt)) -> EnablePCIeIgCmd ("DMAWR", IOMMU_BYP_SADDR, IOMMU_BYP_SADDR, 64'h40, 64'd1 ) | |
110 | ||
111 | XmtCmd: | |
112 | ! select a CFG address in PCI address range and transmit the command to NCU | |
113 | setx CFG_RD_ADDR, %g1, %g2 | |
114 | nop | |
115 | ||
116 | setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR, %g1, %g2 | |
117 | setx 0x020, %g1, %g4 | |
118 | ||
119 | ||
120 | delay_loop: | |
121 | ldx [%g2], %g5 | |
122 | nop | |
123 | nop | |
124 | nop | |
125 | nop | |
126 | dec %g4 | |
127 | brnz %g4, delay_loop | |
128 | nop | |
129 | ||
130 | ! ESR is cleared in INT | |
131 | ! but the next error causes it to log again; | |
132 | ! Get from Uday a diag which has just 1 DMA | |
133 | ||
134 | /* | |
135 | check_esr: | |
136 | setx SOC_ESR_REG, %l7, %i0 | |
137 | ldx [%i0], %i1 | |
138 | ! sub %i1, %g0, %i5 | |
139 | ! brnz %i5, test_failed | |
140 | ! nop | |
141 | ||
142 | setx 0x8000000000000000, %l7, %o3 !valid bit | |
143 | set 0x1, %i2 | |
144 | sllx %i2, ERR_FIELD, %i3 | |
145 | or %i3, %o3, %i4 | |
146 | sub %i1, %i4, %i5 | |
147 | brnz %i5, test_failed | |
148 | nop | |
149 | */ | |
150 | ||
151 | check_per: | |
152 | setx SOC_PER_REG, %l7, %i0 | |
153 | ldx [%i0], %i1 | |
154 | nop | |
155 | ||
156 | sub %i1, %i4, %i5 | |
157 | brnz %i5, test_failed | |
158 | nop | |
159 | ||
160 | ||
161 | ! Check if a Corrected ECC Trap happened | |
162 | check_error_trap: | |
163 | setx EXECUTED, %l1, %l0 | |
164 | cmp %o6, %l0 | |
165 | bne test_failed | |
166 | nop | |
167 | mov TT, %l0 | |
168 | cmp %o7, %l0 | |
169 | bne test_failed | |
170 | nop | |
171 | ||
172 | setx SOC_ESR_REG, %l7, %i0 | |
173 | ldx [%i0], %i1 | |
174 | nop | |
175 | ||
176 | setx 0x8000000000000000, %l7, %o3 !valid bit | |
177 | set 0x1, %i2 | |
178 | sllx %i2, ERR_FIELD, %i3 | |
179 | or %i3, %o3, %i4 | |
180 | sub %i1, %i4, %i5 | |
181 | brnz %i5, test_failed | |
182 | nop | |
183 | ||
184 | ||
185 | test_passed: | |
186 | EXIT_GOOD | |
187 | ||
188 | test_failed: | |
189 | EXIT_BAD | |
190 | ||
191 | ||
192 | ||
193 | ||
194 | /************************************************************************ | |
195 | Trap Handlers | |
196 | ************************************************************************/ | |
197 | My_Recoverable_Sw_error_trap: | |
198 | ! Signal trap taken | |
199 | setx EXECUTED, %l0, %o6 | |
200 | ! save trap type value | |
201 | rdpr %tt, %o7 | |
202 | retry | |
203 | nop | |
204 | ||
205 | My_Corrected_ECC_error_trap: | |
206 | ! Signal trap taken | |
207 | setx EXECUTED, %l0, %o6 | |
208 | ! save trap type value | |
209 | rdpr %tt, %o7 | |
210 | retry | |
211 | nop | |
212 | ||
213 | /************************************************************************ | |
214 | Test case data start | |
215 | ************************************************************************/ | |
216 | ||
217 | /************************************************************************/ | |
218 |