Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / siu / n2_err_siu_dmu_wr.s
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1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: n2_err_siu_dmu_wr.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define ENABLE_PCIE_LINK_TRAINING
39/* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */
40#define MAIN_PAGE_HV_ALSO
41
42#include "err_defines.h"
43#include "hboot.s"
44#include "peu_defines.h"
45
46#define DMA_DATA_ADDR 0x0000000123456700
47#define DMA_DATA_BYP_ADDR1 0xfffc000123456700
48#define DMA_DATA_BYP_ADDR2 0xfffc000123456780
49#define DMA_DATA_BYP_ADDR3 0xfffc000123456800
50
51
52/************************************************************************
53 Test case code start
54 ************************************************************************/
55.text
56.global main
57
58main:
59 ta T_CHANGE_HPRIV
60 nop
61
62 /*********************************
63 RAS
64 *********************************/
65set_ejr:
66 set 0x1, %i1
67 sllx %i1, ERR_FIELD, %i2
68 setx SOC_EJR_REG, %l7, %i3
69 stx %i2, [%i3]
70 membar 0x40
71 /********************************/
72
73 ! enable bypass in IOMMU
74 setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
75 setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
76 stx %g3, [%g2]
77 ldx [%g2], %g3
78
79XmtUsrEvnt1: nop;
80 ! $EV trig_pc_d(1, @VA(.MAIN.XmtUsrEvnt1)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h20", 1 )
81 ldx [%g2], %g3
82 ldx [%g2], %g3
83 ldx [%g2], %g3
84 ldx [%g2], %g3
85
86
87 ! select a CSR in the PIU and transmit the command to NCU
88
89 setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR, %g1, %g2
90 setx 0x020, %g1, %g4
91
92delay_loop:
93 ldx [%g2], %g5
94 nop
95 nop
96 nop
97 nop
98 dec %g4
99 brnz %g4, delay_loop
100 nop
101
102 setx SOC_ESR_REG, %l7, %i0
103 ldx [%i0], %i1
104 nop
105
106 /*********************************
107 RAS
108 *********************************/
109check_esr:
110 setx 0x8000000000000000, %l7, %o3 !valid bit
111 set 0x1, %i2
112 sllx %i2, ERR_FIELD, %i3
113 or %i3, %o3, %i4
114 sub %i1, %i4, %i5
115 brnz %i5, test_failed
116 nop
117 /********************************/
118
119
120test_passed:
121 EXIT_GOOD
122
123test_failed:
124 EXIT_BAD
125
126/************************************************************************
127 Test case data start
128************************************************************************/
129
130SECTION .DATA DATA_VA=DMA_DATA_ADDR
131attr_data {
132 Name = .DATA,
133 hypervisor,
134 compressimage
135}
136
137.data
138.global PCIAddr9
139 .xword 0x0001020304050607
140 .xword 0x08090a0b0c0d0e0f
141 .xword 0x1011121314151617
142 .xword 0x18191a1b1c1d1e1f
143 .xword 0x2021222324252627
144 .xword 0x28292a2b2c2d2e2f
145 .xword 0x3031323334353637
146 .xword 0x38393a3b3c3d3e3f
147
148 .xword 0x4041424344454647
149 .xword 0x48494a4b4c4d4e4f
150 .xword 0x5051525354555657
151 .xword 0x58595a5b5c5d5e5f
152 .xword 0x6061626364656667
153 .xword 0x68696a6b6c6d6e6f
154 .xword 0x7071727374757677
155 .xword 0x78797a7b7c7d7e7f
156
157 .xword 0x8081828384858687
158 .xword 0x88898a8b8c8d8e8f
159 .xword 0x9091929394959697
160 .xword 0x98999a9b9c9d9e9f
161 .xword 0xa0a1a2a3a4a5a6a7
162 .xword 0xa8a9aaabacadaeaf
163 .xword 0xb0b1b2b3b4b5b6b7
164 .xword 0xb8b9babbbcbdbebf
165
166 .xword 0xc0c1c2c3c4c5c6c7
167 .xword 0xc8c9cacbcccdcecf
168 .xword 0xd0d1d2d3d4d5d6d7
169 .xword 0xd8d9dadbdcdddedf
170 .xword 0xe0e1e2e3e4e5e6e7
171 .xword 0xe8e9eaebecedeeef
172 .xword 0xf0f1f2f3f4f5f6f7
173 .xword 0xf8f9fafbfcfdfeff
174
175 .xword 0x0001020304050607
176 .xword 0x08090a0b0c0d0e0f
177 .xword 0x1011121314151617
178 .xword 0x18191a1b1c1d1e1f
179 .xword 0x2021222324252627
180 .xword 0x28292a2b2c2d2e2f
181 .xword 0x3031323334353637
182 .xword 0x38393a3b3c3d3e3f
183
184 .xword 0x4041424344454647
185 .xword 0x48494a4b4c4d4e4f
186 .xword 0x5051525354555657
187 .xword 0x58595a5b5c5d5e5f
188 .xword 0x6061626364656667
189 .xword 0x68696a6b6c6d6e6f
190 .xword 0x7071727374757677
191 .xword 0x78797a7b7c7d7e7f
192
193 .xword 0x8081828384858687
194 .xword 0x88898a8b8c8d8e8f
195 .xword 0x9091929394959697
196 .xword 0x98999a9b9c9d9e9f
197 .xword 0xa0a1a2a3a4a5a6a7
198 .xword 0xa8a9aaabacadaeaf
199 .xword 0xb0b1b2b3b4b5b6b7
200 .xword 0xb8b9babbbcbdbebf
201
202 .xword 0xc0c1c2c3c4c5c6c7
203 .xword 0xc8c9cacbcccdcecf
204 .xword 0xd0d1d2d3d4d5d6d7
205 .xword 0xd8d9dadbdcdddedf
206 .xword 0xe0e1e2e3e4e5e6e7
207 .xword 0xe8e9eaebecedeeef
208 .xword 0xf0f1f2f3f4f5f6f7
209 .xword 0xf8f9fafbfcfdfeff
210
211/************************************************************************/
212