[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / siu / n2_err_siu_dmu_wr_trap.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: n2_err_siu_dmu_wr_trap.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
#define H_HT0_Sw_Recoverable_Error_0x40  My_Recoverable_Sw_error_trap

#define ENABLE_PCIE_LINK_TRAINING
/* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */
#define MAIN_PAGE_HV_ALSO

#include "err_defines.h"
#include "hboot.s"
#include "peu_defines.h"

#define DMA_DATA_ADDR           0x0000000123456700
#define DMA_DATA_BYP_ADDR1      0xfffc000123456700
#define DMA_DATA_BYP_ADDR2      0xfffc000123456780
#define DMA_DATA_BYP_ADDR3      0xfffc000123456800

    
/************************************************************************
   Test case code start
 ************************************************************************/
.text
.global main
.global  My_Corrected_ECC_error_trap
.global  My_Recoverable_Sw_error_trap

main:
        ta T_CHANGE_HPRIV
        nop

	/*********************************
		RAS
	*********************************/
set_ejr:
        set     0x1, %i1
        sllx    %i1, ERR_FIELD, %i2
        setx    SOC_EJR_REG, %l7, %i3
        stx     %i2, [%i3]
        membar  0x40

eie_reg_ones:
        setx    SOC_EIE_REG, %l7, %g5
        stx     %i2, [%g5]
        membar  0x40

	/********************************/

        ! enable bypass in IOMMU
        setx    FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
        setx    FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
        stx     %g3, [%g2]
        ldx     [%g2], %g3

XmtUsrEvnt1: nop;
        ! $EV trig_pc_d(1, @VA(.MAIN.XmtUsrEvnt1)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h20", 1 )
        ldx     [%g2], %g3
        ldx     [%g2], %g3
        ldx     [%g2], %g3
        ldx     [%g2], %g3

	
        ! select a CSR in the PIU and transmit the command to NCU

        setx    FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR, %g1, %g2
        setx    0x020, %g1, %g4

delay_loop:
        ldx     [%g2], %g5
        nop
        nop
        nop
        nop
        dec     %g4
        brnz    %g4, delay_loop
        nop

        setx    SOC_ESR_REG, %l7, %i0
        ldx     [%i0], %i1
        nop

        /*********************************
                RAS
        *********************************/
        ! ESR is cleared in INT
        ! but the next error causes it to log again;
        ! Get from Uday a diag which has just 1 DMA

/*
check_esr:
        setx    SOC_ESR_REG, %l7, %i0
        ldx     [%i0], %i1
!        sub     %i1, %g0, %i5
!        brnz    %i5, test_failed
!        nop

        setx    0x8000000000000000, %l7, %o3    !valid bit
        set     0x1, %i2
        sllx    %i2, ERR_FIELD, %i3
        or      %i3, %o3, %i4
        sub     %i1, %i4, %i5
        brnz    %i5, test_failed
        nop
*/


  ! Check if a Corrected ECC Trap happened
check_error_trap:
        setx  EXECUTED, %l1, %l0
        cmp   %o6, %l0
        bne   test_failed
        nop
        mov   TT, %l0
        cmp   %o7, %l0
        bne   test_failed
        nop

        /********************************/

	
test_passed:
	EXIT_GOOD

test_failed:
	EXIT_BAD


/************************************************************************
	RAS
   	Trap Handlers
 ************************************************************************/
My_Recoverable_Sw_error_trap:
        ! Signal trap taken
        setx  EXECUTED, %l0, %o6
        ! save trap type value
        rdpr  %tt, %o7

check_desr_tt40:
        ldxa  [%g0]0x4c, %g2
        nop
        setx    0xb300000000000000, %l0, %g3
        subcc   %g2, %g3, %g4
        brnz    %g4, test_failed 
	nop

check_per_tt40:
        setx    SOC_PER_REG, %l7, %i0
        ldx     [%i0], %i1
        setx    0x8000000000000000, %l7, %o3    !valid bit
        set     0x1, %i2
        sllx    %i2, ERR_FIELD, %i3
        or      %i3, %o3, %i4
        sub     %i1, %i4, %i5
        brnz    %i5, test_failed
        nop

clear_per_tt40:
        setx    SOC_PER_REG, %l7, %i0
        stx     %g0, [%i0]
        nop
       	done 
        nop


My_Corrected_ECC_error_trap:
        ! Signal trap taken
        setx  EXECUTED, %l0, %o6
        ! save trap type value
        rdpr  %tt, %o7

check_desr_tt63:
        ldxa  [%g0]0x4c, %g2
        nop
        setx    0x8b00000000000000, %l0, %g3
        subcc   %g2, %g3, %g4
        brnz    %g4, test_failed 

check_per_tt63:
        setx    SOC_PER_REG, %l7, %i0
        ldx     [%i0], %i1
        setx    0x8000000000000000, %l7, %o3    !valid bit
        set     0x1, %i2
        sllx    %i2, ERR_FIELD, %i3
        or      %i3, %o3, %i4
        sub     %i1, %i4, %i5
        brnz    %i5, test_failed
        nop

clear_per_tt63:
        setx    SOC_PER_REG, %l7, %i0
        stx     %g0, [%i0]
        nop
        done
        nop


/************************************************************************
   Test case data start
************************************************************************/

SECTION       .DATA DATA_VA=DMA_DATA_ADDR
attr_data {
      Name = .DATA,
      hypervisor,
      compressimage
}

.data
.global PCIAddr9
        .xword 0x0001020304050607
        .xword 0x08090a0b0c0d0e0f
        .xword 0x1011121314151617
        .xword 0x18191a1b1c1d1e1f
        .xword 0x2021222324252627
        .xword 0x28292a2b2c2d2e2f
        .xword 0x3031323334353637
        .xword 0x38393a3b3c3d3e3f

        .xword 0x4041424344454647
        .xword 0x48494a4b4c4d4e4f
        .xword 0x5051525354555657
        .xword 0x58595a5b5c5d5e5f
        .xword 0x6061626364656667
        .xword 0x68696a6b6c6d6e6f
        .xword 0x7071727374757677
        .xword 0x78797a7b7c7d7e7f

        .xword 0x8081828384858687
        .xword 0x88898a8b8c8d8e8f
        .xword 0x9091929394959697
        .xword 0x98999a9b9c9d9e9f
        .xword 0xa0a1a2a3a4a5a6a7
        .xword 0xa8a9aaabacadaeaf
        .xword 0xb0b1b2b3b4b5b6b7
        .xword 0xb8b9babbbcbdbebf

        .xword 0xc0c1c2c3c4c5c6c7
        .xword 0xc8c9cacbcccdcecf
        .xword 0xd0d1d2d3d4d5d6d7
        .xword 0xd8d9dadbdcdddedf
        .xword 0xe0e1e2e3e4e5e6e7
        .xword 0xe8e9eaebecedeeef
        .xword 0xf0f1f2f3f4f5f6f7
        .xword 0xf8f9fafbfcfdfeff

        .xword 0x0001020304050607
        .xword 0x08090a0b0c0d0e0f
        .xword 0x1011121314151617
        .xword 0x18191a1b1c1d1e1f
        .xword 0x2021222324252627
        .xword 0x28292a2b2c2d2e2f
        .xword 0x3031323334353637
        .xword 0x38393a3b3c3d3e3f

        .xword 0x4041424344454647
        .xword 0x48494a4b4c4d4e4f
        .xword 0x5051525354555657
        .xword 0x58595a5b5c5d5e5f
        .xword 0x6061626364656667
        .xword 0x68696a6b6c6d6e6f
        .xword 0x7071727374757677
        .xword 0x78797a7b7c7d7e7f

        .xword 0x8081828384858687
        .xword 0x88898a8b8c8d8e8f
        .xword 0x9091929394959697
        .xword 0x98999a9b9c9d9e9f
        .xword 0xa0a1a2a3a4a5a6a7
        .xword 0xa8a9aaabacadaeaf
        .xword 0xb0b1b2b3b4b5b6b7
        .xword 0xb8b9babbbcbdbebf

        .xword 0xc0c1c2c3c4c5c6c7
        .xword 0xc8c9cacbcccdcecf
        .xword 0xd0d1d2d3d4d5d6d7
        .xword 0xd8d9dadbdcdddedf
        .xword 0xe0e1e2e3e4e5e6e7
        .xword 0xe8e9eaebecedeeef
        .xword 0xf0f1f2f3f4f5f6f7
        .xword 0xf8f9fafbfcfdfeff

/************************************************************************/
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: n2_err_siu_dmu_wr_trap.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
	39	#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
	40
	41	#define ENABLE_PCIE_LINK_TRAINING
	42	/* #define MAIN_PAGE_NUCLEUS_ALSO / / Access main in priviledge mode */
	43	#define MAIN_PAGE_HV_ALSO
	44
	45	#include "err_defines.h"
	46	#include "hboot.s"
	47	#include "peu_defines.h"
	48
	49	#define DMA_DATA_ADDR 0x0000000123456700
	50	#define DMA_DATA_BYP_ADDR1 0xfffc000123456700
	51	#define DMA_DATA_BYP_ADDR2 0xfffc000123456780
	52	#define DMA_DATA_BYP_ADDR3 0xfffc000123456800
	53
	54
	55	/************************************************************************
	56	Test case code start
	57	************************************************************************/
	58	.text
	59	.global main
	60	.global My_Corrected_ECC_error_trap
	61	.global My_Recoverable_Sw_error_trap
	62
	63	main:
	64	ta T_CHANGE_HPRIV
65	nop
66
67	/*********************************
68	RAS
69	*********************************/
70	set_ejr:
71	set 0x1, %i1
72	sllx %i1, ERR_FIELD, %i2
73	setx SOC_EJR_REG, %l7, %i3
74	stx %i2, [%i3]
75	membar 0x40
76
77	eie_reg_ones:
78	setx SOC_EIE_REG, %l7, %g5
79	stx %i2, [%g5]
80	membar 0x40
81
82	/********************************/
83
84	! enable bypass in IOMMU
85	setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
86	setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
87	stx %g3, [%g2]
88	ldx [%g2], %g3
89
90	XmtUsrEvnt1: nop;
91	! $EV trig_pc_d(1, @VA(.MAIN.XmtUsrEvnt1)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h20", 1 )
92	ldx [%g2], %g3
93	ldx [%g2], %g3
94	ldx [%g2], %g3
95	ldx [%g2], %g3
96
97
98	! select a CSR in the PIU and transmit the command to NCU
99
100	setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR, %g1, %g2
101	setx 0x020, %g1, %g4
102
103	delay_loop:
104	ldx [%g2], %g5
105	nop
106	nop
107	nop
108	nop
109	dec %g4
110	brnz %g4, delay_loop
111	nop
112
113	setx SOC_ESR_REG, %l7, %i0
114	ldx [%i0], %i1
115	nop
116
117	/*********************************
118	RAS
119	*********************************/
120	! ESR is cleared in INT
121	! but the next error causes it to log again;
122	! Get from Uday a diag which has just 1 DMA
123
124	/*
125	check_esr:
126	setx SOC_ESR_REG, %l7, %i0
127	ldx [%i0], %i1
128	! sub %i1, %g0, %i5
129	! brnz %i5, test_failed
130	! nop
131
132	setx 0x8000000000000000, %l7, %o3 !valid bit
133	set 0x1, %i2
134	sllx %i2, ERR_FIELD, %i3
135	or %i3, %o3, %i4
136	sub %i1, %i4, %i5
137	brnz %i5, test_failed
138	nop
139	*/
140
141
142	! Check if a Corrected ECC Trap happened
143	check_error_trap:
144	setx EXECUTED, %l1, %l0
145	cmp %o6, %l0
146	bne test_failed
147	nop
148	mov TT, %l0
149	cmp %o7, %l0
150	bne test_failed
151	nop
152
153	/********************************/
154
155
156	test_passed:
157	EXIT_GOOD
158
159	test_failed:
160	EXIT_BAD
161
162
163	/************************************************************************
164	RAS
165	Trap Handlers
166	************************************************************************/
167	My_Recoverable_Sw_error_trap:
168	! Signal trap taken
169	setx EXECUTED, %l0, %o6
170	! save trap type value
171	rdpr %tt, %o7
172
173	check_desr_tt40:
174	ldxa [%g0]0x4c, %g2
175	nop
176	setx 0xb300000000000000, %l0, %g3
177	subcc %g2, %g3, %g4
178	brnz %g4, test_failed
179	nop
180
181	check_per_tt40:
182	setx SOC_PER_REG, %l7, %i0
183	ldx [%i0], %i1
184	setx 0x8000000000000000, %l7, %o3 !valid bit
185	set 0x1, %i2
186	sllx %i2, ERR_FIELD, %i3
187	or %i3, %o3, %i4
188	sub %i1, %i4, %i5
189	brnz %i5, test_failed
190	nop
191
192	clear_per_tt40:
193	setx SOC_PER_REG, %l7, %i0
194	stx %g0, [%i0]
195	nop
196	done
197	nop
198
199
200
201	My_Corrected_ECC_error_trap:
202	! Signal trap taken
203	setx EXECUTED, %l0, %o6
204	! save trap type value
205	rdpr %tt, %o7
206
207	check_desr_tt63:
208	ldxa [%g0]0x4c, %g2
209	nop
210	setx 0x8b00000000000000, %l0, %g3
211	subcc %g2, %g3, %g4
212	brnz %g4, test_failed
213
214	check_per_tt63:
215	setx SOC_PER_REG, %l7, %i0
216	ldx [%i0], %i1
217	setx 0x8000000000000000, %l7, %o3 !valid bit
218	set 0x1, %i2
219	sllx %i2, ERR_FIELD, %i3
220	or %i3, %o3, %i4
221	sub %i1, %i4, %i5
222	brnz %i5, test_failed
223	nop
224
225	clear_per_tt63:
226	setx SOC_PER_REG, %l7, %i0
227	stx %g0, [%i0]
228	nop
229	done
230	nop
231
232
233	/************************************************************************
234	Test case data start
235	************************************************************************/
236
237	SECTION .DATA DATA_VA=DMA_DATA_ADDR
238	attr_data {
239	Name = .DATA,
240	hypervisor,
241	compressimage
242	}
243
244	.data
245	.global PCIAddr9
246	.xword 0x0001020304050607
247	.xword 0x08090a0b0c0d0e0f
248	.xword 0x1011121314151617
249	.xword 0x18191a1b1c1d1e1f
250	.xword 0x2021222324252627
251	.xword 0x28292a2b2c2d2e2f
252	.xword 0x3031323334353637
253	.xword 0x38393a3b3c3d3e3f
254
255	.xword 0x4041424344454647
256	.xword 0x48494a4b4c4d4e4f
257	.xword 0x5051525354555657
258	.xword 0x58595a5b5c5d5e5f
259	.xword 0x6061626364656667
260	.xword 0x68696a6b6c6d6e6f
261	.xword 0x7071727374757677
262	.xword 0x78797a7b7c7d7e7f
263
264	.xword 0x8081828384858687
265	.xword 0x88898a8b8c8d8e8f
266	.xword 0x9091929394959697
267	.xword 0x98999a9b9c9d9e9f
268	.xword 0xa0a1a2a3a4a5a6a7
269	.xword 0xa8a9aaabacadaeaf
270	.xword 0xb0b1b2b3b4b5b6b7
271	.xword 0xb8b9babbbcbdbebf
272
273	.xword 0xc0c1c2c3c4c5c6c7
274	.xword 0xc8c9cacbcccdcecf
275	.xword 0xd0d1d2d3d4d5d6d7
276	.xword 0xd8d9dadbdcdddedf
277	.xword 0xe0e1e2e3e4e5e6e7
278	.xword 0xe8e9eaebecedeeef
279	.xword 0xf0f1f2f3f4f5f6f7
280	.xword 0xf8f9fafbfcfdfeff
281
282	.xword 0x0001020304050607
283	.xword 0x08090a0b0c0d0e0f
284	.xword 0x1011121314151617
285	.xword 0x18191a1b1c1d1e1f
286	.xword 0x2021222324252627
287	.xword 0x28292a2b2c2d2e2f
288	.xword 0x3031323334353637
289	.xword 0x38393a3b3c3d3e3f
290
291	.xword 0x4041424344454647
292	.xword 0x48494a4b4c4d4e4f
293	.xword 0x5051525354555657
294	.xword 0x58595a5b5c5d5e5f
295	.xword 0x6061626364656667
296	.xword 0x68696a6b6c6d6e6f
297	.xword 0x7071727374757677
298	.xword 0x78797a7b7c7d7e7f
299
300	.xword 0x8081828384858687
301	.xword 0x88898a8b8c8d8e8f
302	.xword 0x9091929394959697
303	.xword 0x98999a9b9c9d9e9f
304	.xword 0xa0a1a2a3a4a5a6a7
305	.xword 0xa8a9aaabacadaeaf
306	.xword 0xb0b1b2b3b4b5b6b7
307	.xword 0xb8b9babbbcbdbebf
308
309	.xword 0xc0c1c2c3c4c5c6c7
310	.xword 0xc8c9cacbcccdcecf
311	.xword 0xd0d1d2d3d4d5d6d7
312	.xword 0xd8d9dadbdcdddedf
313	.xword 0xe0e1e2e3e4e5e6e7
314	.xword 0xe8e9eaebecedeeef
315	.xword 0xf0f1f2f3f4f5f6f7
316	.xword 0xf8f9fafbfcfdfeff
317
318	/************************************************************************/
319