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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / siu / n2_err_siu_dmu_wrm.s
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86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: n2_err_siu_dmu_wrm.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define ENABLE_PCIE_LINK_TRAINING
39/* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */
40#define MAIN_PAGE_HV_ALSO
41
42#include "err_defines.h"
43#include "hboot.s"
44#include "peu_defines.h"
45
46#define DMA_DATA_ADDR 0x0000000123456700
47#define DMA_DATA_BYP_ADDR1 0xfffc000123456700
48#define DMA_DATA_BYP_ADDR2 0xfffc000123456780
49#define DMA_DATA_BYP_ADDR3 0xfffc000123456800
50
51
52
53#define DRAM_0_ERR_STAT_REG 0x8400000280
54#define DRAM_1_ERR_STAT_REG 0x8400001280
55#define DRAM_2_ERR_STAT_REG 0x8400002280
56#define DRAM_3_ERR_STAT_REG 0x8400003280
57
58#define L2_0_ERR_STAT_REG 0xAB00000000
59#define L2_1_ERR_STAT_REG 0xAB00000040
60#define L2_2_ERR_STAT_REG 0xAB00000080
61#define L2_3_ERR_STAT_REG 0xAB000000c0
62#define L2_4_ERR_STAT_REG 0xAB00000100
63#define L2_5_ERR_STAT_REG 0xAB00000140
64#define L2_6_ERR_STAT_REG 0xAB00000180
65#define L2_7_ERR_STAT_REG 0xAB000001c0
66
67
68/************************************************************************
69 Test case code start
70 ************************************************************************/
71.text
72.global main
73
74main:
75 ta T_CHANGE_HPRIV
76 nop
77
78 /*********************************
79 RAS
80 *********************************/
81set_ejr:
82 set 0x1, %i1
83 sllx %i1, ERR_FIELD, %i2
84 setx SOC_EJR_REG, %l7, %i3
85 stx %i2, [%i3]
86 membar 0x40
87 /********************************/
88
89 ! enable bypass in IOMMU
90 setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
91 setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
92 stx %g3, [%g2]
93 ldx [%g2], %g3
94
95XmtUsrEvnt1: nop;
96 ! $EV trig_pc_d(1, @VA(.MAIN.XmtUsrEvnt1)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h20", 1 )
97 ldx [%g2], %g3
98 ldx [%g2], %g3
99 ldx [%g2], %g3
100 ldx [%g2], %g3
101
102
103 ! select a CSR in the PIU and transmit the command to NCU
104
105 setx FIRE_PLC_TLU_CTB_TLR_CSR_A_TLU_CTL_ADDR, %g1, %g2
106 setx 0x020, %g1, %g4
107
108delay_loop:
109 ldx [%g2], %g5
110 nop
111 nop
112 nop
113 nop
114 dec %g4
115 brnz %g4, delay_loop
116 nop
117
118 /*********************************
119 RAS
120 *********************************/
121check_mcu_esr:
122 setx DRAM_0_ERR_STAT_REG, %g7, %g6
123 ldx [%g6], %g3
124 sub %g3, %g0, %g1
125 brnz %g1, test_failed
126 nop
127
128 setx DRAM_1_ERR_STAT_REG, %g7, %g6
129 ldx [%g6], %g3
130 sub %g3, %g0, %g1
131 brnz %g1, test_failed
132 nop
133
134 setx DRAM_2_ERR_STAT_REG, %g7, %g6
135 ldx [%g6], %g3
136 sub %g3, %g0, %g1
137 brnz %g1, test_failed
138 nop
139
140 setx DRAM_3_ERR_STAT_REG, %g7, %g6
141 ldx [%g6], %g3
142 sub %g3, %g0, %g1
143 brnz %g1, test_failed
144 nop
145
146check_L2_4_ESR_L2Trap_tt40:
147 setx L2_0_ERR_STAT_REG, %l3, %g5
148 ldx [%g5], %g3
149 sub %g3, %g0, %g1
150 brnz %g1, test_failed
151 nop
152
153 setx L2_1_ERR_STAT_REG, %l3, %g5
154 ldx [%g5], %g3
155 sub %g3, %g0, %g1
156 brnz %g1, test_failed
157 nop
158
159 setx L2_2_ERR_STAT_REG, %l3, %g5
160 ldx [%g5], %g3
161 sub %g3, %g0, %g1
162 brnz %g1, test_failed
163 nop
164
165
166 setx L2_3_ERR_STAT_REG, %l3, %g5
167 ldx [%g5], %g3
168 sub %g3, %g0, %g1
169 brnz %g1, test_failed
170 nop
171
172 setx L2_4_ERR_STAT_REG, %l3, %g5
173 ldx [%g5], %g3
174 sub %g3, %g0, %g1
175 brnz %g1, test_failed
176 nop
177
178 setx L2_5_ERR_STAT_REG, %l3, %g5
179 ldx [%g5], %g3
180 sub %g3, %g0, %g1
181 brnz %g1, test_failed
182 nop
183
184 setx L2_6_ERR_STAT_REG, %l3, %g5
185 ldx [%g5], %g3
186 sub %g3, %g0, %g1
187 brnz %g1, test_failed
188 nop
189
190 setx L2_7_ERR_STAT_REG, %l3, %g5
191 ldx [%g5], %g3
192 sub %g3, %g0, %g1
193 brnz %g1, test_failed
194 nop
195
196check_esr:
197 setx SOC_ESR_REG, %l7, %i0
198 ldx [%i0], %i1
199 sub %i1, %g0, %i5
200 brnz %i5, test_failed
201 nop
202 /********************************/
203
204
205test_passed:
206 EXIT_GOOD
207
208test_failed:
209 EXIT_BAD
210
211/************************************************************************
212 Test case data start
213************************************************************************/
214
215SECTION .DATA DATA_VA=DMA_DATA_ADDR
216attr_data {
217 Name = .DATA,
218 hypervisor,
219 compressimage
220}
221
222.data
223.global PCIAddr9
224 .xword 0x0001020304050607
225 .xword 0x08090a0b0c0d0e0f
226 .xword 0x1011121314151617
227 .xword 0x18191a1b1c1d1e1f
228 .xword 0x2021222324252627
229 .xword 0x28292a2b2c2d2e2f
230 .xword 0x3031323334353637
231 .xword 0x38393a3b3c3d3e3f
232
233 .xword 0x4041424344454647
234 .xword 0x48494a4b4c4d4e4f
235 .xword 0x5051525354555657
236 .xword 0x58595a5b5c5d5e5f
237 .xword 0x6061626364656667
238 .xword 0x68696a6b6c6d6e6f
239 .xword 0x7071727374757677
240 .xword 0x78797a7b7c7d7e7f
241
242 .xword 0x8081828384858687
243 .xword 0x88898a8b8c8d8e8f
244 .xword 0x9091929394959697
245 .xword 0x98999a9b9c9d9e9f
246 .xword 0xa0a1a2a3a4a5a6a7
247 .xword 0xa8a9aaabacadaeaf
248 .xword 0xb0b1b2b3b4b5b6b7
249 .xword 0xb8b9babbbcbdbebf
250
251 .xword 0xc0c1c2c3c4c5c6c7
252 .xword 0xc8c9cacbcccdcecf
253 .xword 0xd0d1d2d3d4d5d6d7
254 .xword 0xd8d9dadbdcdddedf
255 .xword 0xe0e1e2e3e4e5e6e7
256 .xword 0xe8e9eaebecedeeef
257 .xword 0xf0f1f2f3f4f5f6f7
258 .xword 0xf8f9fafbfcfdfeff
259
260 .xword 0x0001020304050607
261 .xword 0x08090a0b0c0d0e0f
262 .xword 0x1011121314151617
263 .xword 0x18191a1b1c1d1e1f
264 .xword 0x2021222324252627
265 .xword 0x28292a2b2c2d2e2f
266 .xword 0x3031323334353637
267 .xword 0x38393a3b3c3d3e3f
268
269 .xword 0x4041424344454647
270 .xword 0x48494a4b4c4d4e4f
271 .xword 0x5051525354555657
272 .xword 0x58595a5b5c5d5e5f
273 .xword 0x6061626364656667
274 .xword 0x68696a6b6c6d6e6f
275 .xword 0x7071727374757677
276 .xword 0x78797a7b7c7d7e7f
277
278 .xword 0x8081828384858687
279 .xword 0x88898a8b8c8d8e8f
280 .xword 0x9091929394959697
281 .xword 0x98999a9b9c9d9e9f
282 .xword 0xa0a1a2a3a4a5a6a7
283 .xword 0xa8a9aaabacadaeaf
284 .xword 0xb0b1b2b3b4b5b6b7
285 .xword 0xb8b9babbbcbdbebf
286
287 .xword 0xc0c1c2c3c4c5c6c7
288 .xword 0xc8c9cacbcccdcecf
289 .xword 0xd0d1d2d3d4d5d6d7
290 .xword 0xd8d9dadbdcdddedf
291 .xword 0xe0e1e2e3e4e5e6e7
292 .xword 0xe8e9eaebecedeeef
293 .xword 0xf0f1f2f3f4f5f6f7
294 .xword 0xf8f9fafbfcfdfeff
295
296/************************************************************************/
297
Full OpenSPARC design & verification tarball including full HDL.