Commit | Line | Data |
---|---|---|
86530b38 AT |
1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: n2_err_l2_LVC_8core.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap | |
39 | ||
40 | ||
41 | #define MAIN_PAGE_HV_ALSO | |
42 | ||
43 | #define L2_ENTRY_PA 0x517590000 | |
44 | #define TEST_DATA 0x555555555555555 | |
45 | #define L2_ES_W1C_VALUE 0xc03ffff800000000 | |
46 | #define L2ES_LVC 34 | |
47 | ||
48 | ||
49 | #define L2_ESR_MASK 0xfffffffff0000000 | |
50 | #define L2_VEC 36 | |
51 | #define L2_LDWC 51 | |
52 | #define L2_LDAC 53 | |
53 | #define L2_LVC 34 | |
54 | ||
55 | #define SYNC_ADDR 0x55500000 | |
56 | ||
57 | #include "hboot.s" | |
58 | #include "asi_s.h" | |
59 | #include "err_defines.h" | |
60 | ||
61 | .text | |
62 | .global main | |
63 | .global My_Corrected_ECC_error_trap | |
64 | ||
65 | ||
66 | main: | |
67 | ! Boot code does not provide TLB translation for IO address space | |
68 | ta T_CHANGE_HPRIV | |
69 | clr %i2 | |
70 | ||
71 | ||
72 | get_th_id_o0: | |
73 | ta T_RD_THID | |
74 | ||
75 | cmp %o1, 0 | |
76 | be main_th_0 | |
77 | nop | |
78 | ||
79 | ba main_all_other_threads | |
80 | ||
81 | main_th_0: | |
82 | ! Now access L2 control and status registers | |
83 | ||
84 | enable_err_reporting: | |
85 | setx L2EE_PA0, %l0, %l1 | |
86 | ldx [%l1], %l2 | |
87 | mov 0x3, %l0 | |
88 | or %l2, %l0, %l2 | |
89 | stx %l2, [%l1] | |
90 | ||
91 | initialize_SYNC_ADDR: | |
92 | setx SYNC_ADDR, %g7, %o2 | |
93 | setx 0x1111111111111111, %g7, %g2 | |
94 | stx %g2, [%o2] | |
95 | ||
96 | st_data: | |
97 | setx 0x44400000, %l0, %g1 | |
98 | setx 0x3ffc0, %l0, %g2 ! Mask for extracting [17:6] | |
99 | clr %i3 | |
100 | clr %i4 | |
101 | err_inj_loop: | |
102 | nop | |
103 | ||
104 | ! With each iteration ERROR_STEERING value goes from 0, 1, 2, ...63 | |
105 | ! Dont read the register value | |
106 | set_L2_Directly_Mapped_Mode_errorsteer: | |
107 | setx L2CS_PA0, %l6, %g4 | |
108 | ! ldx [%g4], %o6 | |
109 | ||
110 | mov 0x2, %o5 ! L2_CSR_REG<1>=1 => DM mode | |
111 | ||
112 | sllx %i3, 15, %o4 ! %i3 has the thread id = 0, 1, 2,3, ...63 ; | |
113 | ! to write as core-steering thread | |
114 | or %o5, %o4, %o5 | |
115 | ||
116 | ! or %o6, %o5, %o6 | |
117 | ||
118 | stx %o5, [%g4] | |
119 | membar 0x40 | |
120 | ||
121 | LVC_diagnostic_access: | |
122 | setx 0x5555555555555555, %g7, %g4 | |
123 | stx %g4, [%g1] | |
124 | !to confirm fill done | |
125 | ld [%g1], %l1 | |
126 | ||
127 | ! Generate L2 VD Diag read address | |
128 | ! Addressing: [39:32] See PRM, [22] 1 for V/D, [17:8] set, [8:6] bank, [2:0] = 0 | |
129 | ||
130 | and %g1, %g2, %g5 | |
131 | ||
132 | mov 0xb6, %g4 | |
133 | sllx %g4, 32, %g6 ! Bits [39:32] | |
134 | or %g5, %g6, %g7 | |
135 | ||
136 | mov UA_VD, %g4 | |
137 | sllx %g4, 22, %g5 ! Bit [22] | |
138 | or %g7, %g5, %g6 | |
139 | ||
140 | ldx [%g6], %g4 !Diagnostic access | |
141 | ||
142 | mov 0x1, %g5 | |
143 | sllx %g5, %i4, %g7 ! %i3=1,2,3,....16 | |
144 | ||
145 | xor %g4, %g7, %g5 ! inject single bit error | |
146 | ||
147 | inject_err: | |
148 | stx %g5, [%g6] | |
149 | ||
150 | ld_st_2: | |
151 | setx 0xaaaaaaaa, %g7, %g5 | |
152 | sllx %i3, 24, %g6 ! %i3=1,2,3,....16 | |
153 | ! to have different tag; same index | |
154 | ! to cause L2 miss | |
155 | or %g1, %g6, %g3 ! %g1 had the PA | |
156 | ||
157 | ! msa | |
158 | ldx [%g1], %o5 | |
159 | stx %g5, [%g1] | |
160 | nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; | |
161 | nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; | |
162 | nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; | |
163 | nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; | |
164 | nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; | |
165 | nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; | |
166 | nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; | |
167 | nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; | |
168 | ||
169 | ! wait for the trap | |
170 | set 0x400, %l1 | |
171 | wait_for_trap_loop: | |
172 | nop | |
173 | dec %l1 | |
174 | cmp %l1, %g0 | |
175 | be test_failed | |
176 | nop | |
177 | ||
178 | ! Each Thread will Write its THID to SYNC_ADDR | |
179 | setx SYNC_ADDR, %g7, %o2 | |
180 | ldx [%o2], %o3 ! Each thread will write to SYNC_ADDR its THID in trap handler | |
181 | cmp %o3, %i3 ! %i3 has the THID which will get the Trap | |
182 | bne %xcc, wait_for_trap_loop | |
183 | nop | |
184 | ||
185 | set 0x200, %g4 | |
186 | add %g1, %g4, %g1 ! to go to the next Set; <17:9> | |
187 | ||
188 | cmp %i4, 38 | |
189 | bne inc_loop | |
190 | nop | |
191 | ||
192 | clr %i4 ! reset %i4 when goes to 38 | |
193 | ||
194 | inc_loop: | |
195 | inc %i3 | |
196 | inc %i4 | |
197 | set INJ_LOOP, %l2 | |
198 | cmp %i3, %l2 | |
199 | bne %xcc, err_inj_loop | |
200 | nop | |
201 | nop | |
202 | nop | |
203 | ||
204 | !trap handler increases %i0 | |
205 | check_err_trap_taken_th0: | |
206 | cmp %i0, 1 | |
207 | bne test_failed | |
208 | nop | |
209 | ||
210 | passed_th0: | |
211 | ba test_passed | |
212 | nop | |
213 | ||
214 | /************************ NON-ZERO THREADS ***********************************/ | |
215 | main_all_other_threads: | |
216 | clr %i0 | |
217 | ||
218 | ! timeout for TH1=0x400, TH2=0x800 | |
219 | sllx %o1, 10, %i6 | |
220 | wait_for_err_trap_all_th: | |
221 | dec %i6 | |
222 | cmp %i6, %g0 | |
223 | timeout_all_th: | |
224 | be %xcc, test_failed | |
225 | nop; nop; nop | |
226 | nop; nop; nop | |
227 | nop; nop; nop | |
228 | nop; nop; nop | |
229 | nop; nop; nop | |
230 | ||
231 | !trap handler increases %i0 | |
232 | cmp %i0, 1 | |
233 | bne wait_for_err_trap_all_th | |
234 | nop | |
235 | ||
236 | nonzero_th_pass: | |
237 | nop | |
238 | ||
239 | /******************************************************* | |
240 | * Exit code | |
241 | *******************************************************/ | |
242 | ||
243 | test_passed: | |
244 | ta T_GOOD_TRAP | |
245 | ||
246 | test_failed: | |
247 | ta T_BAD_TRAP | |
248 | ||
249 | ||
250 | My_Corrected_ECC_error_trap: | |
251 | inc %i0 | |
252 | ||
253 | l2_esr_ch_63: | |
254 | setx L2ES_PA0, %g7, %g2 | |
255 | ldx [%g2], %g1 | |
256 | setx L2_ESR_MASK, %g7, %g3 | |
257 | and %g1, %g3, %g5 | |
258 | ||
259 | mov 0x1, %g6 | |
260 | sllx %g6, L2_VEC, %g2 | |
261 | sllx %g6, L2_LVC, %g3 | |
262 | or %g2, %g3, %g4 | |
263 | ||
264 | cmp %g4, %g5 | |
265 | bne %xcc, test_failed | |
266 | nop | |
267 | ||
268 | synd_chk: | |
269 | setx LVC_MASK_ZERO, %g7, %g2 | |
270 | and %g1, %g2, %g2 ! %g1 has esr value | |
271 | cmp %g2, %g0 ! makes sure <27:14>, <6:0> are 0 for VD | |
272 | ! makes sure <27:14>, <13:7> are 0 for UA | |
273 | bne test_failed | |
274 | nop | |
275 | ||
276 | setx LVC_MASK_NONZERO, %g7, %g2 | |
277 | and %g1, %g2, %g2 ! %g1 has esr value | |
278 | cmp %g2, %g0 ! makes sure <13:7> nonzero for VD | |
279 | ! makes sure <6:0> nonzero for UA | |
280 | be %xcc, test_failed | |
281 | nop | |
282 | ||
283 | clear_l2esr: | |
284 | setx 0xc03ffffc00000000, %g7, %g2 | |
285 | setx L2ES_PA0, %g7, %g3 | |
286 | stx %g2, [%g3] | |
287 | ||
288 | load_DESR_L2C: | |
289 | ldxa [%g0] 0x4c, %g1 | |
290 | setx 0xff00000000000000, %g7, %g2 | |
291 | and %g1, %g2, %g3 | |
292 | setx 0x8900000000000000, %g7, %g4 | |
293 | cmp %g3, %g4 | |
294 | bne %xcc, test_failed | |
295 | nop | |
296 | ||
297 | sync_addr_0x63: | |
298 | setx SYNC_ADDR, %g7, %o2 | |
299 | stx %o1, [%o2] | |
300 | ||
301 | retry | |
302 | nop | |
303 | ||
304 |