[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / vec / n2_ras_vec_adv_mcuUe_piuRd.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: n2_ras_vec_adv_mcuUe_piuRd.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
#define H_HT0_Sw_Recoverable_Error_0x40  My_Recoverable_Sw_error_trap

#define ENABLE_PCIE_LINK_TRAINING
/* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */
#define MAIN_PAGE_HV_ALSO

#include "err_defines.h"
#include "hboot.s"
#include "peu_defines.h"

#define DMA_DATA_ADDR           0x0000000123456700
#define DMA_DATA_BYP_ADDR1      0xfffc000123456700
#define DMA_DATA_BYP_ADDR2      0xfffc000123456780
#define DMA_DATA_BYP_ADDR3      0xfffc000123456800

#define DMA_DATA_ADDR           0x0000000123456700
#define DMA_DATA_BYP_SADDR      0xfffc000123456700
#define DMA_DATA_BYP_EADDR      0xfffc000123456800

#define ADDR1      		0xfffc00002000aa00
#define TEST_DATA1		0xaaaaaaaaaaaaaaaa
#define  DRAM_ERR_INJ_REG   	0x8400000290

#define ERR_BITS                0x2
#define ERR_BITS_EXPECT         0x8000000000000002


#ifdef L2_0
#define L2CS_REG		0xA900000000
#define L2_ERR_STAT_REG         0xAB00000000

#define DRAM_ERR_INJ_REG	0x8400000290
#define DRAM_ERR_STAT_REG	0x8400000280
   
#define L2_ADDR1                0x2000aa00
#define L2_ADDR2                0x1000aa00

#define ADDR1                   0xfffc00002000aa00
#endif


#ifdef L2_1
#define L2CS_REG		0xA900000040
#define L2_ERR_STAT_REG         0xAB00000040

#define DRAM_ERR_INJ_REG	0x8400000290
#define DRAM_ERR_STAT_REG	0x8400000280
   
#define L2_ADDR1                0x2000aa40
#define L2_ADDR2                0x1000aa40

#define ADDR1                   0xfffc00002000aa40
#endif

#ifdef L2_2
#define L2CS_REG		0xA900000080
#define L2_ERR_STAT_REG         0xAB00000080

#define DRAM_ERR_INJ_REG	0x8400001290
#define DRAM_ERR_STAT_REG	0x8400001280
   
#define L2_ADDR1                0x2000aa80
#define L2_ADDR2                0x1000aa80

#define ADDR1                   0xfffc00002000aa80
#endif


#ifdef L2_3
#define L2CS_REG		0xA9000000c0
#define L2_ERR_STAT_REG         0xAB000000c0

#define DRAM_ERR_INJ_REG	0x8400001290
#define DRAM_ERR_STAT_REG	0x8400001280
   
#define L2_ADDR1                0x2000aac0
#define L2_ADDR2                0x1000aac0

#define ADDR1                   0xfffc00002000aac0
#endif

#ifdef L2_4
#define L2CS_REG		0xA900000100
#define L2_ERR_STAT_REG         0xAB00000100

#define DRAM_ERR_INJ_REG	0x8400002290
#define DRAM_ERR_STAT_REG	0x8400002280
   
#define L2_ADDR1                0x2000ab00
#define L2_ADDR2                0x1000ab00

#define ADDR1                   0xfffc00002000ab00
#endif

#ifdef L2_5
#define L2CS_REG		0xA900000140
#define L2_ERR_STAT_REG         0xAB00000140

#define DRAM_ERR_INJ_REG	0x8400002290
#define DRAM_ERR_STAT_REG	0x8400002280
   
#define L2_ADDR1                0x2000ab40
#define L2_ADDR2                0x1000ab40

#define ADDR1                   0xfffc00002000ab40
#endif

#ifdef L2_6
#define L2CS_REG		0xA900000180
#define L2_ERR_STAT_REG         0xAB00000180

#define DRAM_ERR_INJ_REG	0x8400003290
#define DRAM_ERR_STAT_REG	0x8400003280
   
#define L2_ADDR1                0x2000ab80
#define L2_ADDR2                0x1000ab80

#define ADDR1                   0xfffc00002000ab80
#endif

#ifdef L2_7
#define L2CS_REG		0xA9000001c0
#define L2_ERR_STAT_REG         0xAB000001c0

#define DRAM_ERR_INJ_REG	0x8400003290
#define DRAM_ERR_STAT_REG	0x8400003280
   
#define L2_ADDR1                0x2000abc0
#define L2_ADDR2                0x1000abc0

#define ADDR1                   0xfffc00002000abc0
#endif


/************************************************************************
   Test case code start
 ************************************************************************/
.text
.global main
.global  My_Corrected_ECC_error_trap
.global  My_Recoverable_Sw_error_trap

main:
        ta T_CHANGE_HPRIV
        nop

	clr	%i7
	clr	%o6
	clr	%o7
	clr	%i0

disable_l1:
  	ldxa  [%g0] ASI_LSU_CONTROL, %l0
  	! Remove the lower 2 bits (I-Cache and D-Cache enables)
  	andn  %l0, 0x3, %l0
  	stxa  %l0, [%g0] ASI_LSU_CONTROL


set_DRAM_error_inject_ch0:
	mov   0x606, %l1                ! ECC Mask (2-bit error)
	mov   0x1, %l2
	sllx  %l2, DRAM_EI_SSHOT, %l3
	Or    %l1, %l3, %l1           ! Set single shot ;
	mov   0x1, %l2
	sllx  %l2, DRAM_EI_ENB, %l3
	or    %l1, %l3, %l1           ! Enable error injection for the next write
	setx  DRAM_ERR_INJ_REG, %l3, %g6
	stx   %l1, [%g6]
	membar 0x40

L2_err_enable:
        set     0x3, %l1
        mov     0xaa, %g2
        sllx    %g2, 32, %g2
        stx     %l1, [%g2]
        stx     %l1, [%g2 + 0x40]
        stx     %l1, [%g2 + 0x80]
        stx     %l1, [%g2 + 0xc0]
        stx     %l1, [%g2 + 0x100]
        stx     %l1, [%g2 + 0x140]
        stx     %l1, [%g2 + 0x180]
        stx     %l1, [%g2 + 0x1c0]


set_L2_Directly_Mapped_Mode_errorsteer:
	setx  	L2CS_REG, %l6, %g1
	ldx	[%g1], %o6

	mov	0x2, %o5		! L2_CSR_REG<1>=1 => DM mode

	ldxa	[%g0]ASI_INTR_ID, %o4	! get the thread id; for core-portable
	sllx	%o4, 15, %o4		! L2_CSR_REG<21:15> = ERROR_STEER

	or	%o5, %o4, %o5

	or	%o6, %o5, %o6

	stx	%o6, [%g1]
	membar	0x40

store_to_L2_way0:
	setx  TEST_DATA1, %l0, %g5
!	setx  0x2000aa00, %l0, %g2  ! bits [21:18] select way
	setx  L2_ADDR1, %l0, %g2  ! bits [21:18] select way
	stx %g5, [%g2]
	membar #Sync

	! Storing to same L2 way0 but different tag,this will write to mcu
write_mcu_channel_0:
!	setx  0x1000aa00, %l0, %g3 ! bits [21:18] select way
	setx  L2_ADDR2, %l0, %g3 ! bits [21:18] select way
	stx %g5, [%g3]
	membar #Sync

piu_iommu:
        ! enable bypass in IOMMU
        setx    FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
        setx    FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
        stx     %g3, [%g2]
        ldx     [%g2], %g3

	/*******************************************************
		RDD from DMU
	********************************************************/

dma_rdd:
	nop
UsrEvnt_rdd:
        nop         ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_rdd)) -> EnablePCIeIgCmd ("DMARD_UE", ADDR1, ADDR1, "64'h40", 1, *, * )

        ldx     [%g2], %g3
        ldx     [%g2], %g3
        ldx     [%g2], %g3
        ldx     [%g2], %g3

l2_esr:
        mov     0x1, %g1
        sllx    %g1, L2ES_DRU, %g2

        mov     0x1, %g1
        sllx    %g1, L2ES_VEU, %g3

        or      %g2, %g3, %g4

        setx	0x7ffffffff0000000, %g7, %g5
	setx	0x30, %g7, %g6
check_l2_esr:
        cmp     %g6, %g0
        be      %xcc, test_failed
        nop
	dec	%g6

	setx	L2_ERR_STAT_REG, %g7, %g1  
	ldx	[%g1], %g2
	andcc	%g2, %g5, %g3			! Donot check L2ESR SYND bits and MEC

	cmp	%g3, %g4
	bne	%xcc, check_l2_esr 
	nop

cause_trap:
	setx	0x2222222222222222, %g3, %g2
	setx	0x20008000, %g3, %g1
	stx	%g2, [%g1]
	setx	0x80080000, %g3, %g1
	ldx	[%g1], %g2

	setx	0x20000040, %g3, %g1
	stx	 %g2, [%g1]
	setx	0x80080040, %g3, %g1
	ldx	[%g1], %g2

	setx	0x20000080, %g3, %g1
	stx	 %g2, [%g1]
	setx	0x80080000, %g3, %g1
	ldx	[%g1], %g2

	setx	0x200080c0, %g3, %g1
	stx	 %g2, [%g1]
	setx	0x800800c0, %g3, %g1
	ldx	[%g1], %g2

	setx	0x20000100, %g3, %g1
	stx	 %g2, [%g1]
	setx	0x80000100, %g3, %g1
	ldx	[%g1], %g2

	setx	0x20000140, %g3, %g1
	stx	 %g2, [%g1]
	setx	0x80000140, %g3, %g1
	ldx	[%g1], %g2

	setx	0x20000180, %g3, %g1
	stx	 %g2, [%g1]
	setx	0x80000180, %g3, %g1
	ldx	[%g1], %g2

	setx	0x200001c0, %g3, %g1
	stx	 %g2, [%g1]
	setx	0x800001c0, %g3, %g1
	ldx	[%g1], %g2


eie_reg_ones_rdd:
        setx    SOC_EIE_REG, %g3, %g2
        setx 	0xffffffffffffffff, %g3, %g1
        stx     %g1, [%g2]
        membar  0x40

	set	0x1, %g1
        setx    0x30, %g7, %g6
err_trap_loop_rdd:
        cmp     %g6, %g0
        be      %xcc, test_failed
        nop

	cmp	%g1, %i7
	be	%xcc, check_tt_rdd
	nop

	ba	err_trap_loop_rdd
	nop

check_tt_rdd:
        mov     0x40, %l0
        cmp     %o7, %l0
        bne     %xcc, test_failed
        nop


check_l2_trap_cnt:
	set	0x1, %l0
	cmp	%i0, %l0
	bne	test_failed
	nop

test_passed:
	EXIT_GOOD

test_failed:
	EXIT_BAD


/************************************************************************
	RAS
   	Trap Handlers
 ************************************************************************/
My_Recoverable_Sw_error_trap:
        ! Signal trap taken
        setx  EXECUTED, %l0, %o6
        ! save trap type value
        rdpr  %tt, %o7

        inc	%i7

check_desr_NcuTrap_tt40:
        ldxa  [%g0]0x4c, %g2
        nop

        setx    0xb300000000000000, %l0, %g3
        subcc   %g2, %g3, %g4
        brnz    %g4, l2_trap 
	nop

check_per_tt40:
	ba	test_failed
	nop


l2_trap:
	nop
	inc	%i0

check_desr_L2Trap_tt40:
        setx    0xb000000000000000, %l0, %g3
        subcc   %g2, %g3, %g4
        brnz    %g4, test_failed 
        nop

check_mcu2_esr_L2Trap_tt40:
        mov     0x1, %l1
        sllx    %l1, DRAM_ES_DAU, %l0

        setx  DRAM_ERR_STAT_REG, %l3, %g5  
        ldx   [%g5], %l3

        setx  0xffffffffffff0000, %l2, %l1
        andcc %l1, %l3, %l4                   ! Donot check SYND bits

        sub     %l0, %l4, %i4
        brnz    %i4, test_failed
        nop

clear_mcu_esr_L2Trap_tt40:
        stx     %g0, [%g5]


check_L2_4_ESR_L2Trap_tt40:
        setx  	L2_ERR_STAT_REG, %l3, %g5  
        ldx   	[%g5], %l6

        setx  	0x7ffffffff0000000, %l3, %l0
        andcc 	%l0, %l6, %l5                   ! Donot check L2ESR SYND bits and MEU

        mov   	0x1, %l1
        sllx  	%l1, L2ES_DRU, %l0

        mov   	0x1, %l1
        sllx  	%l1, L2ES_VEU, %l2

        or    	%l0, %l2, %i4

        cmp   	%l5, %i4
        bne   	%xcc, test_failed
        nop

clear_l2_esr_L2Trap_tt40:
	stx	%g0, [%g5]

trap_done_tt40:
       	retry 
        nop


My_Corrected_ECC_error_trap:
	ba	test_failed
        nop


/************************************************************************
   Test case data start
************************************************************************/

SECTION       .DATA DATA_VA=DMA_DATA_ADDR
attr_data {
      Name = .DATA,
      hypervisor,
      compressimage
}

.data
.global PCIAddr9
        .xword 0x0001020304050607
        .xword 0x08090a0b0c0d0e0f
        .xword 0x1011121314151617
        .xword 0x18191a1b1c1d1e1f
        .xword 0x2021222324252627
        .xword 0x28292a2b2c2d2e2f
        .xword 0x3031323334353637
        .xword 0x38393a3b3c3d3e3f

        .xword 0x4041424344454647
        .xword 0x48494a4b4c4d4e4f
        .xword 0x5051525354555657
        .xword 0x58595a5b5c5d5e5f
        .xword 0x6061626364656667
        .xword 0x68696a6b6c6d6e6f
        .xword 0x7071727374757677
        .xword 0x78797a7b7c7d7e7f

        .xword 0x8081828384858687
        .xword 0x88898a8b8c8d8e8f
        .xword 0x9091929394959697
        .xword 0x98999a9b9c9d9e9f
        .xword 0xa0a1a2a3a4a5a6a7
        .xword 0xa8a9aaabacadaeaf
        .xword 0xb0b1b2b3b4b5b6b7
        .xword 0xb8b9babbbcbdbebf

        .xword 0xc0c1c2c3c4c5c6c7
        .xword 0xc8c9cacbcccdcecf
        .xword 0xd0d1d2d3d4d5d6d7
        .xword 0xd8d9dadbdcdddedf
        .xword 0xe0e1e2e3e4e5e6e7
        .xword 0xe8e9eaebecedeeef
        .xword 0xf0f1f2f3f4f5f6f7
        .xword 0xf8f9fafbfcfdfeff

        .xword 0x0001020304050607
        .xword 0x08090a0b0c0d0e0f
        .xword 0x1011121314151617
        .xword 0x18191a1b1c1d1e1f
        .xword 0x2021222324252627
        .xword 0x28292a2b2c2d2e2f
        .xword 0x3031323334353637
        .xword 0x38393a3b3c3d3e3f

        .xword 0x4041424344454647
        .xword 0x48494a4b4c4d4e4f
        .xword 0x5051525354555657
        .xword 0x58595a5b5c5d5e5f
        .xword 0x6061626364656667
        .xword 0x68696a6b6c6d6e6f
        .xword 0x7071727374757677
        .xword 0x78797a7b7c7d7e7f

        .xword 0x8081828384858687
        .xword 0x88898a8b8c8d8e8f
        .xword 0x9091929394959697
        .xword 0x98999a9b9c9d9e9f
        .xword 0xa0a1a2a3a4a5a6a7
        .xword 0xa8a9aaabacadaeaf
        .xword 0xb0b1b2b3b4b5b6b7
        .xword 0xb8b9babbbcbdbebf

        .xword 0xc0c1c2c3c4c5c6c7
        .xword 0xc8c9cacbcccdcecf
        .xword 0xd0d1d2d3d4d5d6d7
        .xword 0xd8d9dadbdcdddedf
        .xword 0xe0e1e2e3e4e5e6e7
        .xword 0xe8e9eaebecedeeef
        .xword 0xf0f1f2f3f4f5f6f7
        .xword 0xf8f9fafbfcfdfeff

/************************************************************************/
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: n2_ras_vec_adv_mcuUe_piuRd.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
	39	#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
	40
	41	#define ENABLE_PCIE_LINK_TRAINING
	42	/* #define MAIN_PAGE_NUCLEUS_ALSO / / Access main in priviledge mode */
	43	#define MAIN_PAGE_HV_ALSO
	44
	45	#include "err_defines.h"
	46	#include "hboot.s"
	47	#include "peu_defines.h"
	48
	49	#define DMA_DATA_ADDR 0x0000000123456700
	50	#define DMA_DATA_BYP_ADDR1 0xfffc000123456700
	51	#define DMA_DATA_BYP_ADDR2 0xfffc000123456780
	52	#define DMA_DATA_BYP_ADDR3 0xfffc000123456800
	53
	54	#define DMA_DATA_ADDR 0x0000000123456700
	55	#define DMA_DATA_BYP_SADDR 0xfffc000123456700
	56	#define DMA_DATA_BYP_EADDR 0xfffc000123456800
	57
	58	#define ADDR1 0xfffc00002000aa00
	59	#define TEST_DATA1 0xaaaaaaaaaaaaaaaa
	60	#define DRAM_ERR_INJ_REG 0x8400000290
	61
	62	#define ERR_BITS 0x2
	63	#define ERR_BITS_EXPECT 0x8000000000000002
	64
65
66	#ifdef L2_0
67	#define L2CS_REG 0xA900000000
68	#define L2_ERR_STAT_REG 0xAB00000000
69
70	#define DRAM_ERR_INJ_REG 0x8400000290
71	#define DRAM_ERR_STAT_REG 0x8400000280
72
73	#define L2_ADDR1 0x2000aa00
74	#define L2_ADDR2 0x1000aa00
75
76	#define ADDR1 0xfffc00002000aa00
77	#endif
78
79
80	#ifdef L2_1
81	#define L2CS_REG 0xA900000040
82	#define L2_ERR_STAT_REG 0xAB00000040
83
84	#define DRAM_ERR_INJ_REG 0x8400000290
85	#define DRAM_ERR_STAT_REG 0x8400000280
86
87	#define L2_ADDR1 0x2000aa40
88	#define L2_ADDR2 0x1000aa40
89
90	#define ADDR1 0xfffc00002000aa40
91	#endif
92
93	#ifdef L2_2
94	#define L2CS_REG 0xA900000080
95	#define L2_ERR_STAT_REG 0xAB00000080
96
97	#define DRAM_ERR_INJ_REG 0x8400001290
98	#define DRAM_ERR_STAT_REG 0x8400001280
99
100	#define L2_ADDR1 0x2000aa80
101	#define L2_ADDR2 0x1000aa80
102
103	#define ADDR1 0xfffc00002000aa80
104	#endif
105
106
107	#ifdef L2_3
108	#define L2CS_REG 0xA9000000c0
109	#define L2_ERR_STAT_REG 0xAB000000c0
110
111	#define DRAM_ERR_INJ_REG 0x8400001290
112	#define DRAM_ERR_STAT_REG 0x8400001280
113
114	#define L2_ADDR1 0x2000aac0
115	#define L2_ADDR2 0x1000aac0
116
117	#define ADDR1 0xfffc00002000aac0
118	#endif
119
120	#ifdef L2_4
121	#define L2CS_REG 0xA900000100
122	#define L2_ERR_STAT_REG 0xAB00000100
123
124	#define DRAM_ERR_INJ_REG 0x8400002290
125	#define DRAM_ERR_STAT_REG 0x8400002280
126
127	#define L2_ADDR1 0x2000ab00
128	#define L2_ADDR2 0x1000ab00
129
130	#define ADDR1 0xfffc00002000ab00
131	#endif
132
133	#ifdef L2_5
134	#define L2CS_REG 0xA900000140
135	#define L2_ERR_STAT_REG 0xAB00000140
136
137	#define DRAM_ERR_INJ_REG 0x8400002290
138	#define DRAM_ERR_STAT_REG 0x8400002280
139
140	#define L2_ADDR1 0x2000ab40
141	#define L2_ADDR2 0x1000ab40
142
143	#define ADDR1 0xfffc00002000ab40
144	#endif
145
146	#ifdef L2_6
147	#define L2CS_REG 0xA900000180
148	#define L2_ERR_STAT_REG 0xAB00000180
149
150	#define DRAM_ERR_INJ_REG 0x8400003290
151	#define DRAM_ERR_STAT_REG 0x8400003280
152
153	#define L2_ADDR1 0x2000ab80
154	#define L2_ADDR2 0x1000ab80
155
156	#define ADDR1 0xfffc00002000ab80
157	#endif
158
159	#ifdef L2_7
160	#define L2CS_REG 0xA9000001c0
161	#define L2_ERR_STAT_REG 0xAB000001c0
162
163	#define DRAM_ERR_INJ_REG 0x8400003290
164	#define DRAM_ERR_STAT_REG 0x8400003280
165
166	#define L2_ADDR1 0x2000abc0
167	#define L2_ADDR2 0x1000abc0
168
169	#define ADDR1 0xfffc00002000abc0
170	#endif
171
172
173
174
175	/************************************************************************
176	Test case code start
177	************************************************************************/
178	.text
179	.global main
180	.global My_Corrected_ECC_error_trap
181	.global My_Recoverable_Sw_error_trap
182
183	main:
184	ta T_CHANGE_HPRIV
185	nop
186
187	clr %i7
188	clr %o6
189	clr %o7
190	clr %i0
191
192	disable_l1:
193	ldxa [%g0] ASI_LSU_CONTROL, %l0
194	! Remove the lower 2 bits (I-Cache and D-Cache enables)
195	andn %l0, 0x3, %l0
196	stxa %l0, [%g0] ASI_LSU_CONTROL
197
198
199	set_DRAM_error_inject_ch0:
200	mov 0x606, %l1 ! ECC Mask (2-bit error)
201	mov 0x1, %l2
202	sllx %l2, DRAM_EI_SSHOT, %l3
203	Or %l1, %l3, %l1 ! Set single shot ;
204	mov 0x1, %l2
205	sllx %l2, DRAM_EI_ENB, %l3
206	or %l1, %l3, %l1 ! Enable error injection for the next write
207	setx DRAM_ERR_INJ_REG, %l3, %g6
208	stx %l1, [%g6]
209	membar 0x40
210
211	L2_err_enable:
212	set 0x3, %l1
213	mov 0xaa, %g2
214	sllx %g2, 32, %g2
215	stx %l1, [%g2]
216	stx %l1, [%g2 + 0x40]
217	stx %l1, [%g2 + 0x80]
218	stx %l1, [%g2 + 0xc0]
219	stx %l1, [%g2 + 0x100]
220	stx %l1, [%g2 + 0x140]
221	stx %l1, [%g2 + 0x180]
222	stx %l1, [%g2 + 0x1c0]
223
224
225	set_L2_Directly_Mapped_Mode_errorsteer:
226	setx L2CS_REG, %l6, %g1
227	ldx [%g1], %o6
228
229	mov 0x2, %o5 ! L2_CSR_REG<1>=1 => DM mode
230
231	ldxa [%g0]ASI_INTR_ID, %o4 ! get the thread id; for core-portable
232	sllx %o4, 15, %o4 ! L2_CSR_REG<21:15> = ERROR_STEER
233
234	or %o5, %o4, %o5
235
236	or %o6, %o5, %o6
237
238	stx %o6, [%g1]
239	membar 0x40
240
241	store_to_L2_way0:
242	setx TEST_DATA1, %l0, %g5
243	! setx 0x2000aa00, %l0, %g2 ! bits [21:18] select way
244	setx L2_ADDR1, %l0, %g2 ! bits [21:18] select way
245	stx %g5, [%g2]
246	membar #Sync
247
248	! Storing to same L2 way0 but different tag,this will write to mcu
249	write_mcu_channel_0:
250	! setx 0x1000aa00, %l0, %g3 ! bits [21:18] select way
251	setx L2_ADDR2, %l0, %g3 ! bits [21:18] select way
252	stx %g5, [%g3]
253	membar #Sync
254
255	piu_iommu:
256	! enable bypass in IOMMU
257	setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
258	setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
259	stx %g3, [%g2]
260	ldx [%g2], %g3
261
262	/*******************************************************
263	RDD from DMU
264	********************************************************/
265
266	dma_rdd:
267	nop
268	UsrEvnt_rdd:
269	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_rdd)) -> EnablePCIeIgCmd ("DMARD_UE", ADDR1, ADDR1, "64'h40", 1, , )
270
271	ldx [%g2], %g3
272	ldx [%g2], %g3
273	ldx [%g2], %g3
274	ldx [%g2], %g3
275
276	l2_esr:
277	mov 0x1, %g1
278	sllx %g1, L2ES_DRU, %g2
279
280	mov 0x1, %g1
281	sllx %g1, L2ES_VEU, %g3
282
283	or %g2, %g3, %g4
284
285	setx 0x7ffffffff0000000, %g7, %g5
286	setx 0x30, %g7, %g6
287	check_l2_esr:
288	cmp %g6, %g0
289	be %xcc, test_failed
290	nop
291	dec %g6
292
293	setx L2_ERR_STAT_REG, %g7, %g1
294	ldx [%g1], %g2
295	andcc %g2, %g5, %g3 ! Donot check L2ESR SYND bits and MEC
296
297	cmp %g3, %g4
298	bne %xcc, check_l2_esr
299	nop
300
301	cause_trap:
302	setx 0x2222222222222222, %g3, %g2
303	setx 0x20008000, %g3, %g1
304	stx %g2, [%g1]
305	setx 0x80080000, %g3, %g1
306	ldx [%g1], %g2
307
308	setx 0x20000040, %g3, %g1
309	stx %g2, [%g1]
310	setx 0x80080040, %g3, %g1
311	ldx [%g1], %g2
312
313	setx 0x20000080, %g3, %g1
314	stx %g2, [%g1]
315	setx 0x80080000, %g3, %g1
316	ldx [%g1], %g2
317
318	setx 0x200080c0, %g3, %g1
319	stx %g2, [%g1]
320	setx 0x800800c0, %g3, %g1
321	ldx [%g1], %g2
322
323	setx 0x20000100, %g3, %g1
324	stx %g2, [%g1]
325	setx 0x80000100, %g3, %g1
326	ldx [%g1], %g2
327
328	setx 0x20000140, %g3, %g1
329	stx %g2, [%g1]
330	setx 0x80000140, %g3, %g1
331	ldx [%g1], %g2
332
333	setx 0x20000180, %g3, %g1
334	stx %g2, [%g1]
335	setx 0x80000180, %g3, %g1
336	ldx [%g1], %g2
337
338	setx 0x200001c0, %g3, %g1
339	stx %g2, [%g1]
340	setx 0x800001c0, %g3, %g1
341	ldx [%g1], %g2
342
343
344	eie_reg_ones_rdd:
345	setx SOC_EIE_REG, %g3, %g2
346	setx 0xffffffffffffffff, %g3, %g1
347	stx %g1, [%g2]
348	membar 0x40
349
350	set 0x1, %g1
351	setx 0x30, %g7, %g6
352	err_trap_loop_rdd:
353	cmp %g6, %g0
354	be %xcc, test_failed
355	nop
356
357	cmp %g1, %i7
358	be %xcc, check_tt_rdd
359	nop
360
361	ba err_trap_loop_rdd
362	nop
363
364	check_tt_rdd:
365	mov 0x40, %l0
366	cmp %o7, %l0
367	bne %xcc, test_failed
368	nop
369
370
371	check_l2_trap_cnt:
372	set 0x1, %l0
373	cmp %i0, %l0
374	bne test_failed
375	nop
376
377	test_passed:
378	EXIT_GOOD
379
380	test_failed:
381	EXIT_BAD
382
383
384	/************************************************************************
385	RAS
386	Trap Handlers
387	************************************************************************/
388	My_Recoverable_Sw_error_trap:
389	! Signal trap taken
390	setx EXECUTED, %l0, %o6
391	! save trap type value
392	rdpr %tt, %o7
393
394	inc %i7
395
396	check_desr_NcuTrap_tt40:
397	ldxa [%g0]0x4c, %g2
398	nop
399
400	setx 0xb300000000000000, %l0, %g3
401	subcc %g2, %g3, %g4
402	brnz %g4, l2_trap
403	nop
404
405	check_per_tt40:
406	ba test_failed
407	nop
408
409
410	l2_trap:
411	nop
412	inc %i0
413
414	check_desr_L2Trap_tt40:
415	setx 0xb000000000000000, %l0, %g3
416	subcc %g2, %g3, %g4
417	brnz %g4, test_failed
418	nop
419
420	check_mcu2_esr_L2Trap_tt40:
421	mov 0x1, %l1
422	sllx %l1, DRAM_ES_DAU, %l0
423
424	setx DRAM_ERR_STAT_REG, %l3, %g5
425	ldx [%g5], %l3
426
427	setx 0xffffffffffff0000, %l2, %l1
428	andcc %l1, %l3, %l4 ! Donot check SYND bits
429
430	sub %l0, %l4, %i4
431	brnz %i4, test_failed
432	nop
433
434	clear_mcu_esr_L2Trap_tt40:
435	stx %g0, [%g5]
436
437
438	check_L2_4_ESR_L2Trap_tt40:
439	setx L2_ERR_STAT_REG, %l3, %g5
440	ldx [%g5], %l6
441
442	setx 0x7ffffffff0000000, %l3, %l0
443	andcc %l0, %l6, %l5 ! Donot check L2ESR SYND bits and MEU
444
445	mov 0x1, %l1
446	sllx %l1, L2ES_DRU, %l0
447
448	mov 0x1, %l1
449	sllx %l1, L2ES_VEU, %l2
450
451	or %l0, %l2, %i4
452
453	cmp %l5, %i4
454	bne %xcc, test_failed
455	nop
456
457	clear_l2_esr_L2Trap_tt40:
458	stx %g0, [%g5]
459
460	trap_done_tt40:
461	retry
462	nop
463
464
465
466	My_Corrected_ECC_error_trap:
467	ba test_failed
468	nop
469
470
471	/************************************************************************
472	Test case data start
473	************************************************************************/
474
475	SECTION .DATA DATA_VA=DMA_DATA_ADDR
476	attr_data {
477	Name = .DATA,
478	hypervisor,
479	compressimage
480	}
481
482	.data
483	.global PCIAddr9
484	.xword 0x0001020304050607
485	.xword 0x08090a0b0c0d0e0f
486	.xword 0x1011121314151617
487	.xword 0x18191a1b1c1d1e1f
488	.xword 0x2021222324252627
489	.xword 0x28292a2b2c2d2e2f
490	.xword 0x3031323334353637
491	.xword 0x38393a3b3c3d3e3f
492
493	.xword 0x4041424344454647
494	.xword 0x48494a4b4c4d4e4f
495	.xword 0x5051525354555657
496	.xword 0x58595a5b5c5d5e5f
497	.xword 0x6061626364656667
498	.xword 0x68696a6b6c6d6e6f
499	.xword 0x7071727374757677
500	.xword 0x78797a7b7c7d7e7f
501
502	.xword 0x8081828384858687
503	.xword 0x88898a8b8c8d8e8f
504	.xword 0x9091929394959697
505	.xword 0x98999a9b9c9d9e9f
506	.xword 0xa0a1a2a3a4a5a6a7
507	.xword 0xa8a9aaabacadaeaf
508	.xword 0xb0b1b2b3b4b5b6b7
509	.xword 0xb8b9babbbcbdbebf
510
511	.xword 0xc0c1c2c3c4c5c6c7
512	.xword 0xc8c9cacbcccdcecf
513	.xword 0xd0d1d2d3d4d5d6d7
514	.xword 0xd8d9dadbdcdddedf
515	.xword 0xe0e1e2e3e4e5e6e7
516	.xword 0xe8e9eaebecedeeef
517	.xword 0xf0f1f2f3f4f5f6f7
518	.xword 0xf8f9fafbfcfdfeff
519
520	.xword 0x0001020304050607
521	.xword 0x08090a0b0c0d0e0f
522	.xword 0x1011121314151617
523	.xword 0x18191a1b1c1d1e1f
524	.xword 0x2021222324252627
525	.xword 0x28292a2b2c2d2e2f
526	.xword 0x3031323334353637
527	.xword 0x38393a3b3c3d3e3f
528
529	.xword 0x4041424344454647
530	.xword 0x48494a4b4c4d4e4f
531	.xword 0x5051525354555657
532	.xword 0x58595a5b5c5d5e5f
533	.xword 0x6061626364656667
534	.xword 0x68696a6b6c6d6e6f
535	.xword 0x7071727374757677
536	.xword 0x78797a7b7c7d7e7f
537
538	.xword 0x8081828384858687
539	.xword 0x88898a8b8c8d8e8f
540	.xword 0x9091929394959697
541	.xword 0x98999a9b9c9d9e9f
542	.xword 0xa0a1a2a3a4a5a6a7
543	.xword 0xa8a9aaabacadaeaf
544	.xword 0xb0b1b2b3b4b5b6b7
545	.xword 0xb8b9babbbcbdbebf
546
547	.xword 0xc0c1c2c3c4c5c6c7
548	.xword 0xc8c9cacbcccdcecf
549	.xword 0xd0d1d2d3d4d5d6d7
550	.xword 0xd8d9dadbdcdddedf
551	.xword 0xe0e1e2e3e4e5e6e7
552	.xword 0xe8e9eaebecedeeef
553	.xword 0xf0f1f2f3f4f5f6f7
554	.xword 0xf8f9fafbfcfdfeff
555
556	/************************************************************************/
557