[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / vec / n2_ras_vec_adv_piu_strm_wri_ejr.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: n2_ras_vec_adv_piu_strm_wri_ejr.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
#define H_HT0_Sw_Recoverable_Error_0x40  My_Recoverable_Sw_error_trap

#define ENABLE_PCIE_LINK_TRAINING
/* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */
#define MAIN_PAGE_HV_ALSO

#define  DRAM_0_ERR_STAT_REG              0x8400000280
#define  DRAM_1_ERR_STAT_REG              0x8400001280
#define  DRAM_2_ERR_STAT_REG              0x8400002280
#define  DRAM_3_ERR_STAT_REG              0x8400003280

#define  L2_0_ERR_STAT_REG                0xAB00000000
#define  L2_1_ERR_STAT_REG                0xAB00000040
#define  L2_2_ERR_STAT_REG                0xAB00000080
#define  L2_3_ERR_STAT_REG                0xAB000000c0
#define  L2_4_ERR_STAT_REG                0xAB00000100
#define  L2_5_ERR_STAT_REG                0xAB00000140
#define  L2_6_ERR_STAT_REG                0xAB00000180
#define  L2_7_ERR_STAT_REG                0xAB000001c0


#include "err_defines.h"
#include "hboot.s"
#include "peu_defines.h"

#define DMA_DATA_ADDR           0x0000000123456700

#define DMA_DATA_BYP_ADDR1      0xfffc000123410000
#define DMA_DATA_BYP_ADDR2      0xfffc000123410200
#define DMA_DATA_BYP_ADDR3      0xfffc000123410400
#define DMA_DATA_BYP_ADDR4      0xfffc000123410600
#define DMA_DATA_BYP_ADDR5      0xfffc000123410800
#define DMA_DATA_BYP_ADDR6      0xfffc000123410a00
#define DMA_DATA_BYP_ADDR7      0xfffc000123410c00
#define DMA_DATA_BYP_ADDR8      0xfffc000123410e00
#define DMA_DATA_BYP_ADDR9      0xfffc000123411000
#define DMA_DATA_BYP_ADDR10     0xfffc000123411200
#define DMA_DATA_BYP_ADDR11     0xfffc000123411400
#define DMA_DATA_BYP_ADDR12     0xfffc000123411600
#define DMA_DATA_BYP_ADDR13     0xfffc000123411800
#define DMA_DATA_BYP_ADDR14     0xfffc000123411a00
#define DMA_DATA_BYP_ADDR15     0xfffc000123411c00
#define DMA_DATA_BYP_ADDR16     0xfffc000123411e00
#define DMA_DATA_BYP_ADDR17	0xfffc000123412000
#define DMA_DATA_BYP_ADDR18	0xfffc000123412200
#define DMA_DATA_BYP_ADDR19     0xfffc000123412400
#define DMA_DATA_BYP_ADDR20	0xfffc000123412600
#define DMA_DATA_BYP_ADDR21     0xfffc000123412800
#define DMA_DATA_BYP_ADDR22     0xfffc000123412a00
#define DMA_DATA_BYP_ADDR23     0xfffc000123412c00


#define ERR_BITS                0x80
#define ERR_BITS_EXPECT         0x8000000000000080

#define SOC_ERR_STEERING_REG	0x9001041000
    
/************************************************************************
   Test case code start
 ************************************************************************/
.text
.global main
.global  My_Corrected_ECC_error_trap
.global  My_Recoverable_Sw_error_trap

main:
        ta T_CHANGE_HPRIV
        nop

	clr	%i7
	clr	%o6
	clr	%o7
	clr	%i0


errorsteer:
	ldxa	[%g0]ASI_INTR_ID, %o4			! get the thread id; for core-portable
	setx	SOC_ERR_STEERING_REG, %g7, %g1
	stx	%o4, [%g1]
	membar	0x40

L2_err_enable:
        set	0x3, %l1 
        mov     0xaa, %g2
        sllx    %g2, 32, %g2
        stx     %l1, [%g2]
        stx     %l1, [%g2 + 0x40]
        stx     %l1, [%g2 + 0x80]
        stx     %l1, [%g2 + 0xc0]
        stx     %l1, [%g2 + 0x100]
        stx     %l1, [%g2 + 0x140]
        stx     %l1, [%g2 + 0x180]
        stx     %l1, [%g2 + 0x1c0]

bypass_iommu:
        ! enable bypass in IOMMU
        setx    FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
        setx    FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
        stx     %g3, [%g2]
        ldx     [%g2], %g3

	/*******************************************************
		RDD from DMU
	********************************************************/
set_eie:
        mov     0x1, %g1
        sllx    %g1, ERR_FIELD, %g2
        setx    SOC_EIE_REG, %g7, %g3
        stx     %g2, [%g3]
        membar  0x40


set_ejr_1:
        setx    SOC_EJR_REG, %g7, %g6
        stx     %g2, [%g6]
        membar  0x40


UsrEvnt_wri_1:
	nop	    ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_1)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h40", 1, *, * )

	setx	0x100, %g7, %g5
chk_ejr_1:
	cmp	%g5, %g0
	be	%xcc, test_failed
	nop

	ldx	[%g6], %g1
	cmp	%g1, %g0
	be	%xcc, UsrEvnt_wri_2 
	nop

	dec	%g5

	ba	chk_ejr_1
	nop

UsrEvnt_wri_2:
	nop
	nop
	nop
	nop	    ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_2)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR2, DMA_DATA_BYP_ADDR2, "64'h40", 1, *, * )

UsrEvnt_wri_3:
	nop	    ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_3)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR3, DMA_DATA_BYP_ADDR3, "64'h40", 1, *, * )

UsrEvnt_wri_4:
	nop	    ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_4)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR4, DMA_DATA_BYP_ADDR4, "64'h40", 1, *, * )

UsrEvnt_wri_5:
	nop	    ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_5)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR5, DMA_DATA_BYP_ADDR5, "64'h40", 1, *, * )

UsrEvnt_wri_6:
	nop	    ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_6)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR6, DMA_DATA_BYP_ADDR6, "64'h40", 1, *, * )

UsrEvnt_wri_7:
	nop	    ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_7)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR7, DMA_DATA_BYP_ADDR7, "64'h40", 1, *, * )


set_ejr_2:
	stx	%g2, [%g6]
	membar	0x40


UsrEvnt_wri_8:
	nop	    ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_8)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR8, DMA_DATA_BYP_ADDR8, "64'h40", 1, *, * )

	setx	0x100, %g7, %g5
chk_ejr_2:
	cmp	%g5, %g0
	be	%xcc, test_failed
	nop

	ldx	[%g6], %g1
	cmp	 %g1, %g0
	be	 %xcc, UsrEvnt_wri_9
	nop

	dec	%g5

	ba	chk_ejr_2
	nop

UsrEvnt_wri_9:
	nop
	nop
	nop

	nop	    ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_9)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR9, DMA_DATA_BYP_ADDR9, "64'h40", 1, *, * )

UsrEvnt_wri_10:
	nop	    ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_10)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR10, DMA_DATA_BYP_ADDR10, "64'h40", 1, *, * )

UsrEvnt_wri_11:
	nop	    ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_11)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR11, DMA_DATA_BYP_ADDR11, "64'h40", 1, *, * )

UsrEvnt_wri_12:
	nop	    ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_12)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR12, DMA_DATA_BYP_ADDR12, "64'h40", 1, *, * )

UsrEvnt_wri_13:
	nop	    ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_13)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR13, DMA_DATA_BYP_ADDR13, "64'h40", 1, *, * )


set_ejr_3:
        stx     %g2, [%g6]
        membar  0x40

UsrEvnt_wri_14:
        nop         ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_14)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR14, DMA_DATA_BYP_ADDR14, "64'h40", 1, *, * )

	setx	0x100, %g7, %g5
chk_ejr_3:
	cmp	%g5, %g0
	be	%xcc, test_failed
	nop

	ldx	[%g6], %g1
	cmp	 %g1, %g0
	be	 %xcc, UsrEvnt_wri_15
	nop

	dec	%g5

	ba	chk_ejr_3
	nop

UsrEvnt_wri_15:
	nop
	nop
	nop
	nop
	nop	       ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_15)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR15, DMA_DATA_BYP_ADDR15, "64'h40", 1, *, * )

UsrEvnt_wri_16:
	nop	       ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_16)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR16, DMA_DATA_BYP_ADDR16, "64'h40", 1, *, * )

UsrEvnt_wri_17:
	nop	       ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_17)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR17, DMA_DATA_BYP_ADDR17, "64'h40", 1, *, * )

UsrEvnt_wri_18:
	nop	       ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_18)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR18, DMA_DATA_BYP_ADDR18, "64'h40", 1, *, * )

UsrEvnt_wri_19:
	nop	       ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_19)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR19, DMA_DATA_BYP_ADDR19, "64'h40", 1, *, * )

UsrEvnt_wri_20:
	nop	       ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_20)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR20, DMA_DATA_BYP_ADDR20, "64'h40", 1, *, * )

UsrEvnt_wri_21:
	nop	       ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_21)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR21, DMA_DATA_BYP_ADDR21, "64'h40", 1, *, * )

pios:
	setx	FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
        ldx     [%g2], %g3
        ldx     [%g2], %g3
        ldx     [%g2], %g3
        ldx     [%g2], %g3

/*
	set	0x3, %g1		
        setx    0x100, %g7, %g5
err_trap_loop_rdd:
        cmp     %g5, %g0
        be      %xcc, test_failed
        nop

	cmp	%g1, %i7
	be	%xcc, check_mcu_esr
	nop

	dec	%g5

	ba	err_trap_loop_rdd
	nop
*/


check_mcu_esr:
        setx  DRAM_0_ERR_STAT_REG, %g7, %g6 
        ldx   [%g6], %g3
        sub     %g3, %g0, %g1
        brnz    %g1, test_failed
        nop

        setx  DRAM_1_ERR_STAT_REG, %g7, %g6  
        ldx   [%g6], %g3
        sub     %g3, %g0, %g1
        brnz    %g1, test_failed
        nop

        setx  DRAM_2_ERR_STAT_REG, %g7, %g6  
        ldx   [%g6], %g3
        sub     %g3, %g0, %g1
        brnz    %g1, test_failed
        nop

        setx  DRAM_3_ERR_STAT_REG, %g7, %g6  
        ldx   [%g6], %g3
        sub     %g3, %g0, %g1
        brnz    %g1, test_failed
        nop

check_L2_ESR:
        setx    L2_0_ERR_STAT_REG, %l3, %g5
        ldx     [%g5], %g3
        sub     %g3, %g0, %g1
        brnz    %g1, test_failed
        nop

        setx    L2_1_ERR_STAT_REG, %l3, %g5
        ldx     [%g5], %g3
        sub     %g3, %g0, %g1
        brnz    %g1, test_failed
        nop

        setx    L2_2_ERR_STAT_REG, %l3, %g5
        ldx     [%g5], %g3
        sub     %g3, %g0, %g1
        brnz    %g1, test_failed
        nop

        setx    L2_3_ERR_STAT_REG, %l3, %g5
        ldx     [%g5], %g3
        sub     %g3, %g0, %g1
        brnz    %g1, test_failed
        nop

        setx    L2_4_ERR_STAT_REG, %l3, %g5
        ldx     [%g5], %g3
        sub     %g3, %g0, %g1
        brnz    %g1, test_failed
        nop

        setx    L2_5_ERR_STAT_REG, %l3, %g5
        ldx     [%g5], %g3
        sub     %g3, %g0, %g1
        brnz    %g1, test_failed
        nop

        setx    L2_6_ERR_STAT_REG, %l3, %g5
        ldx     [%g5], %g3
        sub     %g3, %g0, %g1
        brnz    %g1, test_failed
        nop

        setx    L2_7_ERR_STAT_REG, %l3, %g5
        ldx     [%g5], %g3
        sub     %g3, %g0, %g1
        brnz    %g1, test_failed
        nop


check_tt_rdd:
        mov     0x40, %l0
        cmp     %o7, %l0
        bne     %xcc, test_failed
        nop

test_passed:
	EXIT_GOOD

test_failed:
	EXIT_BAD


/************************************************************************
	RAS
   	Trap Handlers
 ************************************************************************/
My_Recoverable_Sw_error_trap:
        ! Signal trap taken
        setx  EXECUTED, %l0, %o6
        ! save trap type value
        rdpr  %tt, %o7

        inc	%i7

check_desr_NcuTrap_tt40:
        ldxa  [%g0]0x4c, %g2
        nop

        setx    0xb300000000000000, %l0, %g3
        subcc   %g2, %g3, %g4
        brnz    %g4, test_failed 
	nop

check_per_tt40:
        mov     0x1, %g1
        sllx    %g1, ERR_FIELD, %g2
        setx    0x8000000000000000, %g7, %g3
        or      %g2, %g3, %g1

        setx    SOC_PER_REG, %g7, %g2
        ldx     [%g2], %g3

        cmp     %g1, %g3
        bne     %xcc, test_failed
        nop

clear_per_tt40:
        setx    SOC_PER_REG, %l7, %g1
        stx     %g0, [%g1]
        nop

clear_ejr_tt40:
	setx	SOC_EJR_REG, %l7, %g1
	stx	%g0, [%g1]
	nop

trap_done_tt40:
       	retry			
        nop


My_Corrected_ECC_error_trap:
	ba	test_failed
        nop


/************************************************************************
   Test case data start
************************************************************************/

SECTION       .DATA DATA_VA=DMA_DATA_ADDR
attr_data {
      Name = .DATA,
      hypervisor,
      compressimage
}

.data
.global PCIAddr9
        .xword 0x0001020304050607
        .xword 0x08090a0b0c0d0e0f
        .xword 0x1011121314151617
        .xword 0x18191a1b1c1d1e1f
        .xword 0x2021222324252627
        .xword 0x28292a2b2c2d2e2f
        .xword 0x3031323334353637
        .xword 0x38393a3b3c3d3e3f

        .xword 0x4041424344454647
        .xword 0x48494a4b4c4d4e4f
        .xword 0x5051525354555657
        .xword 0x58595a5b5c5d5e5f
        .xword 0x6061626364656667
        .xword 0x68696a6b6c6d6e6f
        .xword 0x7071727374757677
        .xword 0x78797a7b7c7d7e7f

        .xword 0x8081828384858687
        .xword 0x88898a8b8c8d8e8f
        .xword 0x9091929394959697
        .xword 0x98999a9b9c9d9e9f
        .xword 0xa0a1a2a3a4a5a6a7
        .xword 0xa8a9aaabacadaeaf
        .xword 0xb0b1b2b3b4b5b6b7
        .xword 0xb8b9babbbcbdbebf

        .xword 0xc0c1c2c3c4c5c6c7
        .xword 0xc8c9cacbcccdcecf
        .xword 0xd0d1d2d3d4d5d6d7
        .xword 0xd8d9dadbdcdddedf
        .xword 0xe0e1e2e3e4e5e6e7
        .xword 0xe8e9eaebecedeeef
        .xword 0xf0f1f2f3f4f5f6f7
        .xword 0xf8f9fafbfcfdfeff

        .xword 0x0001020304050607
        .xword 0x08090a0b0c0d0e0f
        .xword 0x1011121314151617
        .xword 0x18191a1b1c1d1e1f
        .xword 0x2021222324252627
        .xword 0x28292a2b2c2d2e2f
        .xword 0x3031323334353637
        .xword 0x38393a3b3c3d3e3f

        .xword 0x4041424344454647
        .xword 0x48494a4b4c4d4e4f
        .xword 0x5051525354555657
        .xword 0x58595a5b5c5d5e5f
        .xword 0x6061626364656667
        .xword 0x68696a6b6c6d6e6f
        .xword 0x7071727374757677
        .xword 0x78797a7b7c7d7e7f

        .xword 0x8081828384858687
        .xword 0x88898a8b8c8d8e8f
        .xword 0x9091929394959697
        .xword 0x98999a9b9c9d9e9f
        .xword 0xa0a1a2a3a4a5a6a7
        .xword 0xa8a9aaabacadaeaf
        .xword 0xb0b1b2b3b4b5b6b7
        .xword 0xb8b9babbbcbdbebf

        .xword 0xc0c1c2c3c4c5c6c7
        .xword 0xc8c9cacbcccdcecf
        .xword 0xd0d1d2d3d4d5d6d7
        .xword 0xd8d9dadbdcdddedf
        .xword 0xe0e1e2e3e4e5e6e7
        .xword 0xe8e9eaebecedeeef
        .xword 0xf0f1f2f3f4f5f6f7
        .xword 0xf8f9fafbfcfdfeff

/************************************************************************/
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: n2_ras_vec_adv_piu_strm_wri_ejr.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
	39	#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
	40
	41	#define ENABLE_PCIE_LINK_TRAINING
	42	/* #define MAIN_PAGE_NUCLEUS_ALSO / / Access main in priviledge mode */
	43	#define MAIN_PAGE_HV_ALSO
	44
	45	#define DRAM_0_ERR_STAT_REG 0x8400000280
	46	#define DRAM_1_ERR_STAT_REG 0x8400001280
	47	#define DRAM_2_ERR_STAT_REG 0x8400002280
	48	#define DRAM_3_ERR_STAT_REG 0x8400003280
	49
	50	#define L2_0_ERR_STAT_REG 0xAB00000000
	51	#define L2_1_ERR_STAT_REG 0xAB00000040
	52	#define L2_2_ERR_STAT_REG 0xAB00000080
	53	#define L2_3_ERR_STAT_REG 0xAB000000c0
	54	#define L2_4_ERR_STAT_REG 0xAB00000100
	55	#define L2_5_ERR_STAT_REG 0xAB00000140
	56	#define L2_6_ERR_STAT_REG 0xAB00000180
	57	#define L2_7_ERR_STAT_REG 0xAB000001c0
	58
	59
	60	#include "err_defines.h"
	61	#include "hboot.s"
	62	#include "peu_defines.h"
	63
	64	#define DMA_DATA_ADDR 0x0000000123456700
65
66	#define DMA_DATA_BYP_ADDR1 0xfffc000123410000
67	#define DMA_DATA_BYP_ADDR2 0xfffc000123410200
68	#define DMA_DATA_BYP_ADDR3 0xfffc000123410400
69	#define DMA_DATA_BYP_ADDR4 0xfffc000123410600
70	#define DMA_DATA_BYP_ADDR5 0xfffc000123410800
71	#define DMA_DATA_BYP_ADDR6 0xfffc000123410a00
72	#define DMA_DATA_BYP_ADDR7 0xfffc000123410c00
73	#define DMA_DATA_BYP_ADDR8 0xfffc000123410e00
74	#define DMA_DATA_BYP_ADDR9 0xfffc000123411000
75	#define DMA_DATA_BYP_ADDR10 0xfffc000123411200
76	#define DMA_DATA_BYP_ADDR11 0xfffc000123411400
77	#define DMA_DATA_BYP_ADDR12 0xfffc000123411600
78	#define DMA_DATA_BYP_ADDR13 0xfffc000123411800
79	#define DMA_DATA_BYP_ADDR14 0xfffc000123411a00
80	#define DMA_DATA_BYP_ADDR15 0xfffc000123411c00
81	#define DMA_DATA_BYP_ADDR16 0xfffc000123411e00
82	#define DMA_DATA_BYP_ADDR17 0xfffc000123412000
83	#define DMA_DATA_BYP_ADDR18 0xfffc000123412200
84	#define DMA_DATA_BYP_ADDR19 0xfffc000123412400
85	#define DMA_DATA_BYP_ADDR20 0xfffc000123412600
86	#define DMA_DATA_BYP_ADDR21 0xfffc000123412800
87	#define DMA_DATA_BYP_ADDR22 0xfffc000123412a00
88	#define DMA_DATA_BYP_ADDR23 0xfffc000123412c00
89
90
91	#define ERR_BITS 0x80
92	#define ERR_BITS_EXPECT 0x8000000000000080
93
94	#define SOC_ERR_STEERING_REG 0x9001041000
95
96	/************************************************************************
97	Test case code start
98	************************************************************************/
99	.text
100	.global main
101	.global My_Corrected_ECC_error_trap
102	.global My_Recoverable_Sw_error_trap
103
104	main:
105	ta T_CHANGE_HPRIV
106	nop
107
108	clr %i7
109	clr %o6
110	clr %o7
111	clr %i0
112
113
114	errorsteer:
115	ldxa [%g0]ASI_INTR_ID, %o4 ! get the thread id; for core-portable
116	setx SOC_ERR_STEERING_REG, %g7, %g1
117	stx %o4, [%g1]
118	membar 0x40
119
120	L2_err_enable:
121	set 0x3, %l1
122	mov 0xaa, %g2
123	sllx %g2, 32, %g2
124	stx %l1, [%g2]
125	stx %l1, [%g2 + 0x40]
126	stx %l1, [%g2 + 0x80]
127	stx %l1, [%g2 + 0xc0]
128	stx %l1, [%g2 + 0x100]
129	stx %l1, [%g2 + 0x140]
130	stx %l1, [%g2 + 0x180]
131	stx %l1, [%g2 + 0x1c0]
132
133	bypass_iommu:
134	! enable bypass in IOMMU
135	setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
136	setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
137	stx %g3, [%g2]
138	ldx [%g2], %g3
139
140	/*******************************************************
141	RDD from DMU
142	********************************************************/
143	set_eie:
144	mov 0x1, %g1
145	sllx %g1, ERR_FIELD, %g2
146	setx SOC_EIE_REG, %g7, %g3
147	stx %g2, [%g3]
148	membar 0x40
149
150
151	set_ejr_1:
152	setx SOC_EJR_REG, %g7, %g6
153	stx %g2, [%g6]
154	membar 0x40
155
156
157	UsrEvnt_wri_1:
158	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_1)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR1, DMA_DATA_BYP_ADDR1, "64'h40", 1, , )
159
160	setx 0x100, %g7, %g5
161	chk_ejr_1:
162	cmp %g5, %g0
163	be %xcc, test_failed
164	nop
165
166	ldx [%g6], %g1
167	cmp %g1, %g0
168	be %xcc, UsrEvnt_wri_2
169	nop
170
171	dec %g5
172
173	ba chk_ejr_1
174	nop
175
176	UsrEvnt_wri_2:
177	nop
178	nop
179	nop
180	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_2)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR2, DMA_DATA_BYP_ADDR2, "64'h40", 1, , )
181
182	UsrEvnt_wri_3:
183	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_3)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR3, DMA_DATA_BYP_ADDR3, "64'h40", 1, , )
184
185	UsrEvnt_wri_4:
186	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_4)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR4, DMA_DATA_BYP_ADDR4, "64'h40", 1, , )
187
188	UsrEvnt_wri_5:
189	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_5)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR5, DMA_DATA_BYP_ADDR5, "64'h40", 1, , )
190
191	UsrEvnt_wri_6:
192	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_6)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR6, DMA_DATA_BYP_ADDR6, "64'h40", 1, , )
193
194	UsrEvnt_wri_7:
195	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_7)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR7, DMA_DATA_BYP_ADDR7, "64'h40", 1, , )
196
197
198	set_ejr_2:
199	stx %g2, [%g6]
200	membar 0x40
201
202
203	UsrEvnt_wri_8:
204	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_8)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR8, DMA_DATA_BYP_ADDR8, "64'h40", 1, , )
205
206	setx 0x100, %g7, %g5
207	chk_ejr_2:
208	cmp %g5, %g0
209	be %xcc, test_failed
210	nop
211
212	ldx [%g6], %g1
213	cmp %g1, %g0
214	be %xcc, UsrEvnt_wri_9
215	nop
216
217	dec %g5
218
219	ba chk_ejr_2
220	nop
221
222	UsrEvnt_wri_9:
223	nop
224	nop
225	nop
226
227	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_9)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR9, DMA_DATA_BYP_ADDR9, "64'h40", 1, , )
228
229	UsrEvnt_wri_10:
230	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_10)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR10, DMA_DATA_BYP_ADDR10, "64'h40", 1, , )
231
232	UsrEvnt_wri_11:
233	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_11)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR11, DMA_DATA_BYP_ADDR11, "64'h40", 1, , )
234
235	UsrEvnt_wri_12:
236	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_12)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR12, DMA_DATA_BYP_ADDR12, "64'h40", 1, , )
237
238	UsrEvnt_wri_13:
239	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_13)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR13, DMA_DATA_BYP_ADDR13, "64'h40", 1, , )
240
241
242	set_ejr_3:
243	stx %g2, [%g6]
244	membar 0x40
245
246	UsrEvnt_wri_14:
247	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_14)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR14, DMA_DATA_BYP_ADDR14, "64'h40", 1, , )
248
249	setx 0x100, %g7, %g5
250	chk_ejr_3:
251	cmp %g5, %g0
252	be %xcc, test_failed
253	nop
254
255	ldx [%g6], %g1
256	cmp %g1, %g0
257	be %xcc, UsrEvnt_wri_15
258	nop
259
260	dec %g5
261
262	ba chk_ejr_3
263	nop
264
265	UsrEvnt_wri_15:
266	nop
267	nop
268	nop
269	nop
270	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_15)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR15, DMA_DATA_BYP_ADDR15, "64'h40", 1, , )
271
272	UsrEvnt_wri_16:
273	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_16)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR16, DMA_DATA_BYP_ADDR16, "64'h40", 1, , )
274
275	UsrEvnt_wri_17:
276	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_17)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR17, DMA_DATA_BYP_ADDR17, "64'h40", 1, , )
277
278	UsrEvnt_wri_18:
279	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_18)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR18, DMA_DATA_BYP_ADDR18, "64'h40", 1, , )
280
281	UsrEvnt_wri_19:
282	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_19)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR19, DMA_DATA_BYP_ADDR19, "64'h40", 1, , )
283
284	UsrEvnt_wri_20:
285	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_20)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR20, DMA_DATA_BYP_ADDR20, "64'h40", 1, , )
286
287	UsrEvnt_wri_21:
288	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_wri_21)) -> EnablePCIeIgCmd ("DMAWR", DMA_DATA_BYP_ADDR21, DMA_DATA_BYP_ADDR21, "64'h40", 1, , )
289
290	pios:
291	setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
292	ldx [%g2], %g3
293	ldx [%g2], %g3
294	ldx [%g2], %g3
295	ldx [%g2], %g3
296
297	/*
298	set 0x3, %g1
299	setx 0x100, %g7, %g5
300	err_trap_loop_rdd:
301	cmp %g5, %g0
302	be %xcc, test_failed
303	nop
304
305	cmp %g1, %i7
306	be %xcc, check_mcu_esr
307	nop
308
309	dec %g5
310
311	ba err_trap_loop_rdd
312	nop
313	*/
314
315
316	check_mcu_esr:
317	setx DRAM_0_ERR_STAT_REG, %g7, %g6
318	ldx [%g6], %g3
319	sub %g3, %g0, %g1
320	brnz %g1, test_failed
321	nop
322
323	setx DRAM_1_ERR_STAT_REG, %g7, %g6
324	ldx [%g6], %g3
325	sub %g3, %g0, %g1
326	brnz %g1, test_failed
327	nop
328
329	setx DRAM_2_ERR_STAT_REG, %g7, %g6
330	ldx [%g6], %g3
331	sub %g3, %g0, %g1
332	brnz %g1, test_failed
333	nop
334
335	setx DRAM_3_ERR_STAT_REG, %g7, %g6
336	ldx [%g6], %g3
337	sub %g3, %g0, %g1
338	brnz %g1, test_failed
339	nop
340
341	check_L2_ESR:
342	setx L2_0_ERR_STAT_REG, %l3, %g5
343	ldx [%g5], %g3
344	sub %g3, %g0, %g1
345	brnz %g1, test_failed
346	nop
347
348	setx L2_1_ERR_STAT_REG, %l3, %g5
349	ldx [%g5], %g3
350	sub %g3, %g0, %g1
351	brnz %g1, test_failed
352	nop
353
354	setx L2_2_ERR_STAT_REG, %l3, %g5
355	ldx [%g5], %g3
356	sub %g3, %g0, %g1
357	brnz %g1, test_failed
358	nop
359
360	setx L2_3_ERR_STAT_REG, %l3, %g5
361	ldx [%g5], %g3
362	sub %g3, %g0, %g1
363	brnz %g1, test_failed
364	nop
365
366	setx L2_4_ERR_STAT_REG, %l3, %g5
367	ldx [%g5], %g3
368	sub %g3, %g0, %g1
369	brnz %g1, test_failed
370	nop
371
372	setx L2_5_ERR_STAT_REG, %l3, %g5
373	ldx [%g5], %g3
374	sub %g3, %g0, %g1
375	brnz %g1, test_failed
376	nop
377
378	setx L2_6_ERR_STAT_REG, %l3, %g5
379	ldx [%g5], %g3
380	sub %g3, %g0, %g1
381	brnz %g1, test_failed
382	nop
383
384	setx L2_7_ERR_STAT_REG, %l3, %g5
385	ldx [%g5], %g3
386	sub %g3, %g0, %g1
387	brnz %g1, test_failed
388	nop
389
390
391	check_tt_rdd:
392	mov 0x40, %l0
393	cmp %o7, %l0
394	bne %xcc, test_failed
395	nop
396
397	test_passed:
398	EXIT_GOOD
399
400	test_failed:
401	EXIT_BAD
402
403
404	/************************************************************************
405	RAS
406	Trap Handlers
407	************************************************************************/
408	My_Recoverable_Sw_error_trap:
409	! Signal trap taken
410	setx EXECUTED, %l0, %o6
411	! save trap type value
412	rdpr %tt, %o7
413
414	inc %i7
415
416	check_desr_NcuTrap_tt40:
417	ldxa [%g0]0x4c, %g2
418	nop
419
420	setx 0xb300000000000000, %l0, %g3
421	subcc %g2, %g3, %g4
422	brnz %g4, test_failed
423	nop
424
425	check_per_tt40:
426	mov 0x1, %g1
427	sllx %g1, ERR_FIELD, %g2
428	setx 0x8000000000000000, %g7, %g3
429	or %g2, %g3, %g1
430
431	setx SOC_PER_REG, %g7, %g2
432	ldx [%g2], %g3
433
434	cmp %g1, %g3
435	bne %xcc, test_failed
436	nop
437
438	clear_per_tt40:
439	setx SOC_PER_REG, %l7, %g1
440	stx %g0, [%g1]
441	nop
442
443	clear_ejr_tt40:
444	setx SOC_EJR_REG, %l7, %g1
445	stx %g0, [%g1]
446	nop
447
448	trap_done_tt40:
449	retry
450	nop
451
452
453
454	My_Corrected_ECC_error_trap:
455	ba test_failed
456	nop
457
458
459	/************************************************************************
460	Test case data start
461	************************************************************************/
462
463	SECTION .DATA DATA_VA=DMA_DATA_ADDR
464	attr_data {
465	Name = .DATA,
466	hypervisor,
467	compressimage
468	}
469
470	.data
471	.global PCIAddr9
472	.xword 0x0001020304050607
473	.xword 0x08090a0b0c0d0e0f
474	.xword 0x1011121314151617
475	.xword 0x18191a1b1c1d1e1f
476	.xword 0x2021222324252627
477	.xword 0x28292a2b2c2d2e2f
478	.xword 0x3031323334353637
479	.xword 0x38393a3b3c3d3e3f
480
481	.xword 0x4041424344454647
482	.xword 0x48494a4b4c4d4e4f
483	.xword 0x5051525354555657
484	.xword 0x58595a5b5c5d5e5f
485	.xword 0x6061626364656667
486	.xword 0x68696a6b6c6d6e6f
487	.xword 0x7071727374757677
488	.xword 0x78797a7b7c7d7e7f
489
490	.xword 0x8081828384858687
491	.xword 0x88898a8b8c8d8e8f
492	.xword 0x9091929394959697
493	.xword 0x98999a9b9c9d9e9f
494	.xword 0xa0a1a2a3a4a5a6a7
495	.xword 0xa8a9aaabacadaeaf
496	.xword 0xb0b1b2b3b4b5b6b7
497	.xword 0xb8b9babbbcbdbebf
498
499	.xword 0xc0c1c2c3c4c5c6c7
500	.xword 0xc8c9cacbcccdcecf
501	.xword 0xd0d1d2d3d4d5d6d7
502	.xword 0xd8d9dadbdcdddedf
503	.xword 0xe0e1e2e3e4e5e6e7
504	.xword 0xe8e9eaebecedeeef
505	.xword 0xf0f1f2f3f4f5f6f7
506	.xword 0xf8f9fafbfcfdfeff
507
508	.xword 0x0001020304050607
509	.xword 0x08090a0b0c0d0e0f
510	.xword 0x1011121314151617
511	.xword 0x18191a1b1c1d1e1f
512	.xword 0x2021222324252627
513	.xword 0x28292a2b2c2d2e2f
514	.xword 0x3031323334353637
515	.xword 0x38393a3b3c3d3e3f
516
517	.xword 0x4041424344454647
518	.xword 0x48494a4b4c4d4e4f
519	.xword 0x5051525354555657
520	.xword 0x58595a5b5c5d5e5f
521	.xword 0x6061626364656667
522	.xword 0x68696a6b6c6d6e6f
523	.xword 0x7071727374757677
524	.xword 0x78797a7b7c7d7e7f
525
526	.xword 0x8081828384858687
527	.xword 0x88898a8b8c8d8e8f
528	.xword 0x9091929394959697
529	.xword 0x98999a9b9c9d9e9f
530	.xword 0xa0a1a2a3a4a5a6a7
531	.xword 0xa8a9aaabacadaeaf
532	.xword 0xb0b1b2b3b4b5b6b7
533	.xword 0xb8b9babbbcbdbebf
534
535	.xword 0xc0c1c2c3c4c5c6c7
536	.xword 0xc8c9cacbcccdcecf
537	.xword 0xd0d1d2d3d4d5d6d7
538	.xword 0xd8d9dadbdcdddedf
539	.xword 0xe0e1e2e3e4e5e6e7
540	.xword 0xe8e9eaebecedeeef
541	.xword 0xf0f1f2f3f4f5f6f7
542	.xword 0xf8f9fafbfcfdfeff
543
544	/************************************************************************/
545