[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / vec / n2_ras_vec_dau_nd_8core_6core.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: n2_ras_vec_dau_nd_8core_6core.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
#define H_HT0_Sw_Recoverable_Error_0x40  My_Recoverable_Sw_error_trap
#define H_HT0_Data_access_error_0x32  My_Precise_data_access_error_trap

#define ENABLE_PCIE_LINK_TRAINING
/* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */
#define MAIN_PAGE_HV_ALSO

#include "err_defines.h"
#include "hboot.s"
#include "peu_defines.h"

#define TEST_DATA1		0xaaaaaaaaaaaaaaaa

#define L2_ADDR1		0x2000aa00
#define L2_ADDR2		0x1000aa00

#define	DRAM_ERR_INJ_REG	0x8400000290
#define L2_ERR_STAT_REG         0xAB00000000
#define DRAM_ERR_STAT_REG	0x8400000280

#define L2_ND_REG         	0xAE00000000
   
#define SYNC_ADDR		0x5550000


/************************************************************************
   Test case code start
 ************************************************************************/
.text
.global main
.global  My_Corrected_ECC_error_trap
.global  My_Recoverable_Sw_error_trap
.global	 My_Precise_data_access_error_trap

main:
        ta T_CHANGE_HPRIV
        nop


disable_l1:
	ldxa  [%g0] ASI_LSU_CONTROL, %l0
	! Remove the lower 2 bits (I-Cache and D-Cache enables)
	andn  %l0, 0x3, %l0
	stxa  %l0, [%g0] ASI_LSU_CONTROL
	ldxa  [%g0] ASI_LSU_CONTROL, %l0

get_th_id_o0:
        ta      T_RD_THID

        cmp     %o1, 0 
        be      main_th_0
        nop

	ba	main_all_other_threads 
	nop

main_th_0:
	clr	%i0
	clr	%i1

set_DRAM_error_inject_ch0:
	mov   0x606, %l1                ! ECC Mask (2-bit error)
	mov   0x1, %l2
	sllx  %l2, DRAM_EI_SSHOT, %l3
	Or    %l1, %l3, %l1           ! Set single shot ;
	mov   0x1, %l2
	sllx  %l2, DRAM_EI_ENB, %l3
	or    %l1, %l3, %l1           ! Enable error injection for the next write
	setx  DRAM_ERR_INJ_REG, %l3, %g6
	stx   %l1, [%g6]
	membar 0x40

L2_err_enable:
        set     0x3, %l1
        mov     0xaa, %g2
        sllx    %g2, 32, %g2
        stx     %l1, [%g2]
        stx     %l1, [%g2 + 0x40]
        stx     %l1, [%g2 + 0x80]
        stx     %l1, [%g2 + 0xc0]
        stx     %l1, [%g2 + 0x100]
        stx     %l1, [%g2 + 0x140]
        stx     %l1, [%g2 + 0x180]
        stx     %l1, [%g2 + 0x1c0]


set_L2_Directly_Mapped_Mode_errorsteer:
        setx    L2CS_PA0, %l6, %g1
        ldx     [%g1], %o6

        mov     0x2, %o5                ! L2_CSR_REG<1>=1 => DM mode
        or      %o6, %o5, %o6

        stx     %o6, [%g1]
        membar  0x40


store_to_L2_way0:
	setx  TEST_DATA1, %l0, %g5
	setx  L2_ADDR1, %l0, %g2  ! bits [21:18] select way
	stx %g5, [%g2]
	membar #Sync

	! Storing to same L2 way0 but different tag,this will write to mcu
write_mcu_channel_0:
	setx  L2_ADDR2, %l0, %g3 ! bits [21:18] select way
	stx %g5, [%g3]
	membar #Sync


cause_err_th0:
	setx	L2_ADDR1, %g7, %g2 
        ldub    [%g2], %g3			
	nop
	nop
	nop

sync_other_threads_th0:
        setx    SYNC_ADDR, %g7, %g1
        setx    0x1111111111111111, %g7, %g2
        stx     %g2, [%g1]


check_trap_taken_th0:
        cmp     %i1, 0x1
!       bne     test_failed                     ! Should take tt=0x32
        nop

        cmp     %i0, %g0 
!       be     test_failed                     ! Should not take tt=0x40
        nop

pass_th_0:
	ba	test_passed
	nop


/************************  TH B ***********************************/
main_all_other_threads:
	clr	%i0
	clr	%i1

	set	0x200, %i6
wait_for_thread0_err:
	dec	%i6
	cmp	%i6, %g0
timeout:
	be	%xcc, test_failed
	nop

	setx	SYNC_ADDR, %g7, %g1
	ldx	[%g1], %g2
        setx    0x1111111111111111, %g7, %g3
	cmp	%g2, %g3
	bne	wait_for_thread0_err	
	nop

access_err_addr:
	setx	L2_ADDR1, %g7, %g2
	ldub	[%g2], %g3
	nop
	nop
	nop

check_trap_taken:
	cmp	%i1, 0x1
!	bne	test_failed			! Should take tt=0x32
	nop

        cmp     %i0, %g0 
!       be     test_failed                     ! Should not take tt=0x40
        nop

/*******************************************************************/
test_passed:
	EXIT_GOOD

test_failed:
	EXIT_BAD


/************************************************************************
	RAS
   	Trap Handlers
 ************************************************************************/

/****************************** TT=0x40 ***********************************/
My_Recoverable_Sw_error_trap:
        inc	%i0

check_desr_NcuTrap_tt40:
        ldxa  [%g0]0x4c, %g2
        nop

check_mcu_esr_tt40:
	setx  DRAM_ERR_STAT_REG, %l3, %g5  
	ldx   [%g5], %l3

check_L2_ESR__tt40:
	setx	L2_ERR_STAT_REG, %l3, %g5  
	ldx	[%g5], %l6

trap_done_tt40:
       	retry
        nop


/****************************** TT=0x63 ***********************************/
My_Corrected_ECC_error_trap:
	ba	test_failed
        nop

/****************************** TT=0x32 ***********************************/
My_Precise_data_access_error_trap:
	inc	%i1
	cmp	%o1, 0				! %o1 value preserved from T_RD_THID 
	bne	other_threads_0x32
	nop

check_DSFSR_th0_0x32:
	set	0x18, %g3
	ldxa	[%g3] 0x58, %g2
	set	0xf, %g3
	and	%g2, %g3, %g2
	cmp	%g2, 0x1			! DCL2U
	be	clear_dsfsr_DCL2U_0x32
	nop
	cmp	%g2, 0x2			! DCL2ND
	bne	test_failed
	nop
check_clear_desr_0x32:
        ldxa  [%g0]0x4c, %g2
        nop
!add code to check the DESR value
	ba	clear_dsfsr_DCL2U_0x32
	nop

	! other threads should get tt=0x32 with DCL2ND only
other_threads_0x32:
	set	0x18, %g3
	ldxa	[%g3] 0x58, %g2
        cmp     %g2, 0x2                        ! DCL2ND
        bne     test_failed
        nop

clear_dsfsr_DCL2U_0x32:
	set	0x18, %g3
	stxa	%g0, [%g3] 0x58			! clear DSFSR
	nop

mcu_esr_0x32:
        mov     0x1, %g1
        sllx    %g1, DRAM_ES_DAU, %g2
        setx  	DRAM_ERR_STAT_REG, %g7, %g5  
        ldx   	[%g5], %g1
        setx  	0xffffffffffff0000, %g7, %g3
        andcc 	%g1, %g3, %g4                   ! Donot check SYND bits
	cmp	%g2, %g4
	bne	%xcc, test_failed
	nop

L2_err_0x32:
	cmp	%o1, 0
	bne	nd_other_threads_0x32
	nop

check_L2_ESR_th0_only_0x32:
        setx    L2_ERR_STAT_REG, %l3, %g5  
        ldx     [%g5], %l6
        setx    0x7ffffffff0000000, %l3, %l0
        andcc   %l0, %l6, %l5                   ! Donot check L2ESR SYND bits and MEU
        mov     0x1, %l1
        sllx    %l1, L2ES_DAU, %l0
        mov     0x1, %l1
        sllx    %l1, L2ES_VEU, %l2
        or      %l0, %l2, %i4
        cmp     %l5, %i4
        bne     %xcc, test_failed
        nop

	ba	done_0x32
	nop

nd_other_threads_0x32:
	setx	L2_ND_REG, %g7, %g1
	ldx	[%g1], %g2
	setx	0x7c0fffffffff0, %g7, %g4		!Mask off VCID <45:40>, amnother diag to check it; MEND;  <3:0>
	and	%g2, %g4, %g2

	setx	0x2000000000000, %g7, %g5		!Expected value: NDSP = <49>
!	sllx	%o1, 40, %g3				!%o1 => VCID = ND_REG<45:40>
!	or	%g5, %g3, %g5				! NDSP, VCID 

	setx	L2_ADDR1, %g7, %g1			!ADDRESS = ND_REG<39:4>
	or	%g1, %g5, %g5				!NDSP, ADDR

	cmp	%g2, %g5
	bne	%xcc, test_failed
	nop 
 

done_0x32:
	done
	nop

/************************************************************************
   Test case data start
************************************************************************/
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: n2_ras_vec_dau_nd_8core_6core.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
	39	#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
	40	#define H_HT0_Data_access_error_0x32 My_Precise_data_access_error_trap
	41
	42	#define ENABLE_PCIE_LINK_TRAINING
	43	/* #define MAIN_PAGE_NUCLEUS_ALSO / / Access main in priviledge mode */
	44	#define MAIN_PAGE_HV_ALSO
	45
	46	#include "err_defines.h"
	47	#include "hboot.s"
	48	#include "peu_defines.h"
	49
	50	#define TEST_DATA1 0xaaaaaaaaaaaaaaaa
	51
	52	#define L2_ADDR1 0x2000aa00
	53	#define L2_ADDR2 0x1000aa00
	54
	55	#define DRAM_ERR_INJ_REG 0x8400000290
	56	#define L2_ERR_STAT_REG 0xAB00000000
	57	#define DRAM_ERR_STAT_REG 0x8400000280
	58
	59	#define L2_ND_REG 0xAE00000000
	60
	61	#define SYNC_ADDR 0x5550000
	62
	63
	64
65	/************************************************************************
66	Test case code start
67	************************************************************************/
68	.text
69	.global main
70	.global My_Corrected_ECC_error_trap
71	.global My_Recoverable_Sw_error_trap
72	.global My_Precise_data_access_error_trap
73
74	main:
75	ta T_CHANGE_HPRIV
76	nop
77
78
79	disable_l1:
80	ldxa [%g0] ASI_LSU_CONTROL, %l0
81	! Remove the lower 2 bits (I-Cache and D-Cache enables)
82	andn %l0, 0x3, %l0
83	stxa %l0, [%g0] ASI_LSU_CONTROL
84	ldxa [%g0] ASI_LSU_CONTROL, %l0
85
86	get_th_id_o0:
87	ta T_RD_THID
88
89	cmp %o1, 0
90	be main_th_0
91	nop
92
93	ba main_all_other_threads
94	nop
95
96	main_th_0:
97	clr %i0
98	clr %i1
99
100	set_DRAM_error_inject_ch0:
101	mov 0x606, %l1 ! ECC Mask (2-bit error)
102	mov 0x1, %l2
103	sllx %l2, DRAM_EI_SSHOT, %l3
104	Or %l1, %l3, %l1 ! Set single shot ;
105	mov 0x1, %l2
106	sllx %l2, DRAM_EI_ENB, %l3
107	or %l1, %l3, %l1 ! Enable error injection for the next write
108	setx DRAM_ERR_INJ_REG, %l3, %g6
109	stx %l1, [%g6]
110	membar 0x40
111
112	L2_err_enable:
113	set 0x3, %l1
114	mov 0xaa, %g2
115	sllx %g2, 32, %g2
116	stx %l1, [%g2]
117	stx %l1, [%g2 + 0x40]
118	stx %l1, [%g2 + 0x80]
119	stx %l1, [%g2 + 0xc0]
120	stx %l1, [%g2 + 0x100]
121	stx %l1, [%g2 + 0x140]
122	stx %l1, [%g2 + 0x180]
123	stx %l1, [%g2 + 0x1c0]
124
125
126	set_L2_Directly_Mapped_Mode_errorsteer:
127	setx L2CS_PA0, %l6, %g1
128	ldx [%g1], %o6
129
130	mov 0x2, %o5 ! L2_CSR_REG<1>=1 => DM mode
131	or %o6, %o5, %o6
132
133	stx %o6, [%g1]
134	membar 0x40
135
136
137	store_to_L2_way0:
138	setx TEST_DATA1, %l0, %g5
139	setx L2_ADDR1, %l0, %g2 ! bits [21:18] select way
140	stx %g5, [%g2]
141	membar #Sync
142
143	! Storing to same L2 way0 but different tag,this will write to mcu
144	write_mcu_channel_0:
145	setx L2_ADDR2, %l0, %g3 ! bits [21:18] select way
146	stx %g5, [%g3]
147	membar #Sync
148
149
150	cause_err_th0:
151	setx L2_ADDR1, %g7, %g2
152	ldub [%g2], %g3
153	nop
154	nop
155	nop
156
157	sync_other_threads_th0:
158	setx SYNC_ADDR, %g7, %g1
159	setx 0x1111111111111111, %g7, %g2
160	stx %g2, [%g1]
161
162
163	check_trap_taken_th0:
164	cmp %i1, 0x1
165	! bne test_failed ! Should take tt=0x32
166	nop
167
168	cmp %i0, %g0
169	! be test_failed ! Should not take tt=0x40
170	nop
171
172	pass_th_0:
173	ba test_passed
174	nop
175
176
177
178	/********************** TH B *********************************/
179	main_all_other_threads:
180	clr %i0
181	clr %i1
182
183	set 0x200, %i6
184	wait_for_thread0_err:
185	dec %i6
186	cmp %i6, %g0
187	timeout:
188	be %xcc, test_failed
189	nop
190
191	setx SYNC_ADDR, %g7, %g1
192	ldx [%g1], %g2
193	setx 0x1111111111111111, %g7, %g3
194	cmp %g2, %g3
195	bne wait_for_thread0_err
196	nop
197
198	access_err_addr:
199	setx L2_ADDR1, %g7, %g2
200	ldub [%g2], %g3
201	nop
202	nop
203	nop
204
205	check_trap_taken:
206	cmp %i1, 0x1
207	! bne test_failed ! Should take tt=0x32
208	nop
209
210	cmp %i0, %g0
211	! be test_failed ! Should not take tt=0x40
212	nop
213
214	/*******************************************************************/
215	test_passed:
216	EXIT_GOOD
217
218	test_failed:
219	EXIT_BAD
220
221
222	/************************************************************************
223	RAS
224	Trap Handlers
225	************************************************************************/
226
227	/**************************** TT=0x40 *********************************/
228	My_Recoverable_Sw_error_trap:
229	inc %i0
230
231	check_desr_NcuTrap_tt40:
232	ldxa [%g0]0x4c, %g2
233	nop
234
235	check_mcu_esr_tt40:
236	setx DRAM_ERR_STAT_REG, %l3, %g5
237	ldx [%g5], %l3
238
239	check_L2_ESR__tt40:
240	setx L2_ERR_STAT_REG, %l3, %g5
241	ldx [%g5], %l6
242
243	trap_done_tt40:
244	retry
245	nop
246
247
248	/**************************** TT=0x63 *********************************/
249	My_Corrected_ECC_error_trap:
250	ba test_failed
251	nop
252
253	/**************************** TT=0x32 *********************************/
254	My_Precise_data_access_error_trap:
255	inc %i1
256	cmp %o1, 0 ! %o1 value preserved from T_RD_THID
257	bne other_threads_0x32
258	nop
259
260	check_DSFSR_th0_0x32:
261	set 0x18, %g3
262	ldxa [%g3] 0x58, %g2
263	set 0xf, %g3
264	and %g2, %g3, %g2
265	cmp %g2, 0x1 ! DCL2U
266	be clear_dsfsr_DCL2U_0x32
267	nop
268	cmp %g2, 0x2 ! DCL2ND
269	bne test_failed
270	nop
271	check_clear_desr_0x32:
272	ldxa [%g0]0x4c, %g2
273	nop
274	!add code to check the DESR value
275	ba clear_dsfsr_DCL2U_0x32
276	nop
277
278	! other threads should get tt=0x32 with DCL2ND only
279	other_threads_0x32:
280	set 0x18, %g3
281	ldxa [%g3] 0x58, %g2
282	cmp %g2, 0x2 ! DCL2ND
283	bne test_failed
284	nop
285
286	clear_dsfsr_DCL2U_0x32:
287	set 0x18, %g3
288	stxa %g0, [%g3] 0x58 ! clear DSFSR
289	nop
290
291	mcu_esr_0x32:
292	mov 0x1, %g1
293	sllx %g1, DRAM_ES_DAU, %g2
294	setx DRAM_ERR_STAT_REG, %g7, %g5
295	ldx [%g5], %g1
296	setx 0xffffffffffff0000, %g7, %g3
297	andcc %g1, %g3, %g4 ! Donot check SYND bits
298	cmp %g2, %g4
299	bne %xcc, test_failed
300	nop
301
302	L2_err_0x32:
303	cmp %o1, 0
304	bne nd_other_threads_0x32
305	nop
306
307	check_L2_ESR_th0_only_0x32:
308	setx L2_ERR_STAT_REG, %l3, %g5
309	ldx [%g5], %l6
310	setx 0x7ffffffff0000000, %l3, %l0
311	andcc %l0, %l6, %l5 ! Donot check L2ESR SYND bits and MEU
312	mov 0x1, %l1
313	sllx %l1, L2ES_DAU, %l0
314	mov 0x1, %l1
315	sllx %l1, L2ES_VEU, %l2
316	or %l0, %l2, %i4
317	cmp %l5, %i4
318	bne %xcc, test_failed
319	nop
320
321	ba done_0x32
322	nop
323
324	nd_other_threads_0x32:
325	setx L2_ND_REG, %g7, %g1
326	ldx [%g1], %g2
327	setx 0x7c0fffffffff0, %g7, %g4 !Mask off VCID <45:40>, amnother diag to check it; MEND; <3:0>
328	and %g2, %g4, %g2
329
330	setx 0x2000000000000, %g7, %g5 !Expected value: NDSP = <49>
331	! sllx %o1, 40, %g3 !%o1 => VCID = ND_REG<45:40>
332	! or %g5, %g3, %g5 ! NDSP, VCID
333
334	setx L2_ADDR1, %g7, %g1 !ADDRESS = ND_REG<39:4>
335	or %g1, %g5, %g5 !NDSP, ADDR
336
337	cmp %g2, %g5
338	bne %xcc, test_failed
339	nop
340
341
342	done_0x32:
343	done
344	nop
345
346	/************************************************************************
347	Test case data start
348	************************************************************************/
349
350