[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / vec / n2_ras_vec_dmu_dma_rd_trap.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: n2_ras_vec_dmu_dma_rd_trap.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
#define H_HT0_Sw_Recoverable_Error_0x40  My_Recoverable_Sw_error_trap

#define ENABLE_PCIE_LINK_TRAINING    
/* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */
#define MAIN_PAGE_HV_ALSO

#include "hboot.s"
#include "peu_defines.h"

#define MEM32_RD_ADDR 		mpeval(N2_PCIE_BASE_ADDR + MEM32_OFFSET_BASE_REG_DATA)

#define DMA_DATA_ADDR   	0x0000000123456700
#define DMA_DATA_BYP_SADDR      0xfffc000123456700
#define DMA_DATA_BYP_EADDR      0xfffc000123456800

#define SOC_ERR_STEERING_REG	0x9001041000

/************************************************************************
   Test case code start
 ************************************************************************/
.text
.global main
.global  My_Corrected_ECC_error_trap
.global  My_Recoverable_Sw_error_trap

main:
        ta T_CHANGE_HPRIV
        nop

	! enable bypass in IOMMU
	setx	FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
	setx	FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
	stx	%g3, [%g2]
	ldx	[%g2], %g3

errorsteer:
	ldxa	[%g0]ASI_INTR_ID, %o4			! get the thread id; for core-portable
	setx	SOC_ERR_STEERING_REG, %g7, %g1
	stx	%o4, [%g1]
	membar	0x40

clear_esr_first:
        setx    SOC_ESR_REG, %l7, %i0
        stx     %g0, [%i0]

set_ejr:
        set     0x1, %i1
        sllx    %i1, ERR_FIELD, %i2
        setx    SOC_EJR_REG, %l7, %i3
        stx     %i2, [%i3]
        membar  0x40

set_eie:
        setx    SOC_EIE_REG, %l7, %i3
        stx     %i2, [%i3]
        membar  0x40


! see if this user event works in a loop (multi-shot)
	
	setx	0x02, %g1, %g4
XmtUsrEvnt1:
	nop         ! $EV trig_pc_d(1, @VA(.MAIN.XmtUsrEvnt1)) -> EnablePCIeIgCmd ("DMARD", DMA_DATA_BYP_SADDR, DMA_DATA_BYP_EADDR, "64'h40", 1, *, * )
	dec	%g4
	brnz	%g4, XmtUsrEvnt1
	nop
	nop

	
	setx	0x40, %g1, %g4
delay_loop:
	nop; nop; nop
        nop; nop; nop  
        nop; nop; nop  
        nop; nop; nop  
        nop; nop; nop  
	
	dec	%g4
	brnz	%g4, delay_loop
	nop


  ! Check if a Corrected_ECC_Trap or Recoverable_Sw_error_trap happened
check_error_trap:
        setx  EXECUTED, %l1, %l0
        cmp   %o6, %l0
        bne   test_failed
        nop
        mov   TT, %l0
        cmp   %o7, %l0
        bne   test_failed
        nop
	
test_passed:
	EXIT_GOOD

	
test_failed:
	EXIT_BAD


/************************************************************************
        RAS
        Trap Handlers
 ************************************************************************/
My_Recoverable_Sw_error_trap:
        ! Signal trap taken
        setx  EXECUTED, %l0, %o6
        ! save trap type value
        rdpr  %tt, %o7

check_desr_tt40:
        ldxa  [%g0]0x4c, %g2
        nop
        setx    0xb300000000000000, %l0, %g3
        subcc   %g2, %g3, %g4
        brnz    %g4, test_failed
        nop

check_per_tt40:
        setx    SOC_PER_REG, %l7, %i0
        ldx     [%i0], %i1
        setx    0x8000000000000000, %l7, %o3    !valid bit
        set     0x1, %i2
        sllx    %i2, ERR_FIELD, %i3
        or      %i3, %o3, %i4
        sub     %i1, %i4, %i5
        brnz    %i5, test_failed
        nop

clear_per_tt40:
        setx    SOC_PER_REG, %l7, %i0
        stx     %g0, [%i0]
        nop
        done
        nop

My_Corrected_ECC_error_trap:
        ! Signal trap taken
        setx  EXECUTED, %l0, %o6
        ! save trap type value
        rdpr  %tt, %o7

check_desr_tt63:
        ldxa  [%g0]0x4c, %g2
        nop
        setx    0x8b00000000000000, %l0, %g3
        subcc   %g2, %g3, %g4
        brnz    %g4, test_failed

check_per_tt63:
        setx    SOC_PER_REG, %l7, %i0
        ldx     [%i0], %i1
        setx    0x8000000000000000, %l7, %o3    !valid bit
        set     0x1, %i2
        sllx    %i2, ERR_FIELD, %i3
        or      %i3, %o3, %i4
        sub     %i1, %i4, %i5
        brnz    %i5, test_failed
        nop

clear_per_tt63:
        setx    SOC_PER_REG, %l7, %i0
        stx     %g0, [%i0]
        nop
        done
        nop

/************************************************************************
   Test case data start
************************************************************************/

SECTION       .DATA DATA_VA=DMA_DATA_ADDR
attr_data {     
      Name = .DATA,
      hypervisor,
      compressimage
}

.data
	.xword 0x0001020304050607
	.xword 0x08090a0b0c0d0e0f
	.xword 0x1011121314151617
	.xword 0x18191a1b1c1d1e1f
	.xword 0x2021222324252627
	.xword 0x28292a2b2c2d2e2f
	.xword 0x3031323334353637
	.xword 0x38393a3b3c3d3e3f
	
	.xword 0x4041424344454647
	.xword 0x48494a4b4c4d4e4f
	.xword 0x5051525354555657
	.xword 0x58595a5b5c5d5e5f
	.xword 0x6061626364656667
	.xword 0x68696a6b6c6d6e6f
	.xword 0x7071727374757677
	.xword 0x78797a7b7c7d7e7f
	
	.xword 0x8081828384858687
	.xword 0x88898a8b8c8d8e8f
	.xword 0x9091929394959697
	.xword 0x98999a9b9c9d9e9f
	.xword 0xa0a1a2a3a4a5a6a7
	.xword 0xa8a9aaabacadaeaf
	.xword 0xb0b1b2b3b4b5b6b7
	.xword 0xb8b9babbbcbdbebf
	
	.xword 0xc0c1c2c3c4c5c6c7
	.xword 0xc8c9cacbcccdcecf
	.xword 0xd0d1d2d3d4d5d6d7
	.xword 0xd8d9dadbdcdddedf
	.xword 0xe0e1e2e3e4e5e6e7
	.xword 0xe8e9eaebecedeeef
	.xword 0xf0f1f2f3f4f5f6f7
	.xword 0xf8f9fafbfcfdfeff

	.xword 0x0001020304050607
	.xword 0x08090a0b0c0d0e0f
	.xword 0x1011121314151617
	.xword 0x18191a1b1c1d1e1f
	.xword 0x2021222324252627
	.xword 0x28292a2b2c2d2e2f
	.xword 0x3031323334353637
	.xword 0x38393a3b3c3d3e3f
	
	.xword 0x4041424344454647
	.xword 0x48494a4b4c4d4e4f
	.xword 0x5051525354555657
	.xword 0x58595a5b5c5d5e5f
	.xword 0x6061626364656667
	.xword 0x68696a6b6c6d6e6f
	.xword 0x7071727374757677
	.xword 0x78797a7b7c7d7e7f
	
	.xword 0x8081828384858687
	.xword 0x88898a8b8c8d8e8f
	.xword 0x9091929394959697
	.xword 0x98999a9b9c9d9e9f
	.xword 0xa0a1a2a3a4a5a6a7
	.xword 0xa8a9aaabacadaeaf
	.xword 0xb0b1b2b3b4b5b6b7
	.xword 0xb8b9babbbcbdbebf
	
	.xword 0xc0c1c2c3c4c5c6c7
	.xword 0xc8c9cacbcccdcecf
	.xword 0xd0d1d2d3d4d5d6d7
	.xword 0xd8d9dadbdcdddedf
	.xword 0xe0e1e2e3e4e5e6e7
	.xword 0xe8e9eaebecedeeef
	.xword 0xf0f1f2f3f4f5f6f7
	.xword 0xf8f9fafbfcfdfeff
	
/************************************************************************/
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: n2_ras_vec_dmu_dma_rd_trap.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
	39	#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
	40
	41	#define ENABLE_PCIE_LINK_TRAINING
	42	/* #define MAIN_PAGE_NUCLEUS_ALSO / / Access main in priviledge mode */
	43	#define MAIN_PAGE_HV_ALSO
	44
	45	#include "hboot.s"
	46	#include "peu_defines.h"
	47
	48	#define MEM32_RD_ADDR mpeval(N2_PCIE_BASE_ADDR + MEM32_OFFSET_BASE_REG_DATA)
	49
	50	#define DMA_DATA_ADDR 0x0000000123456700
	51	#define DMA_DATA_BYP_SADDR 0xfffc000123456700
	52	#define DMA_DATA_BYP_EADDR 0xfffc000123456800
	53
	54	#define SOC_ERR_STEERING_REG 0x9001041000
	55
	56	/************************************************************************
	57	Test case code start
	58	************************************************************************/
	59	.text
	60	.global main
	61	.global My_Corrected_ECC_error_trap
	62	.global My_Recoverable_Sw_error_trap
	63
	64	main:
65	ta T_CHANGE_HPRIV
66	nop
67
68	! enable bypass in IOMMU
69	setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
70	setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
71	stx %g3, [%g2]
72	ldx [%g2], %g3
73
74	errorsteer:
75	ldxa [%g0]ASI_INTR_ID, %o4 ! get the thread id; for core-portable
76	setx SOC_ERR_STEERING_REG, %g7, %g1
77	stx %o4, [%g1]
78	membar 0x40
79
80	clear_esr_first:
81	setx SOC_ESR_REG, %l7, %i0
82	stx %g0, [%i0]
83
84	set_ejr:
85	set 0x1, %i1
86	sllx %i1, ERR_FIELD, %i2
87	setx SOC_EJR_REG, %l7, %i3
88	stx %i2, [%i3]
89	membar 0x40
90
91	set_eie:
92	setx SOC_EIE_REG, %l7, %i3
93	stx %i2, [%i3]
94	membar 0x40
95
96
97	! see if this user event works in a loop (multi-shot)
98
99	setx 0x02, %g1, %g4
100	XmtUsrEvnt1:
101	nop ! $EV trig_pc_d(1, @VA(.MAIN.XmtUsrEvnt1)) -> EnablePCIeIgCmd ("DMARD", DMA_DATA_BYP_SADDR, DMA_DATA_BYP_EADDR, "64'h40", 1, , )
102	dec %g4
103	brnz %g4, XmtUsrEvnt1
104	nop
105	nop
106
107
108	setx 0x40, %g1, %g4
109	delay_loop:
110	nop; nop; nop
111	nop; nop; nop
112	nop; nop; nop
113	nop; nop; nop
114	nop; nop; nop
115
116	dec %g4
117	brnz %g4, delay_loop
118	nop
119
120
121	! Check if a Corrected_ECC_Trap or Recoverable_Sw_error_trap happened
122	check_error_trap:
123	setx EXECUTED, %l1, %l0
124	cmp %o6, %l0
125	bne test_failed
126	nop
127	mov TT, %l0
128	cmp %o7, %l0
129	bne test_failed
130	nop
131
132	test_passed:
133	EXIT_GOOD
134
135
136	test_failed:
137	EXIT_BAD
138
139
140	/************************************************************************
141	RAS
142	Trap Handlers
143	************************************************************************/
144	My_Recoverable_Sw_error_trap:
145	! Signal trap taken
146	setx EXECUTED, %l0, %o6
147	! save trap type value
148	rdpr %tt, %o7
149
150	check_desr_tt40:
151	ldxa [%g0]0x4c, %g2
152	nop
153	setx 0xb300000000000000, %l0, %g3
154	subcc %g2, %g3, %g4
155	brnz %g4, test_failed
156	nop
157
158	check_per_tt40:
159	setx SOC_PER_REG, %l7, %i0
160	ldx [%i0], %i1
161	setx 0x8000000000000000, %l7, %o3 !valid bit
162	set 0x1, %i2
163	sllx %i2, ERR_FIELD, %i3
164	or %i3, %o3, %i4
165	sub %i1, %i4, %i5
166	brnz %i5, test_failed
167	nop
168
169	clear_per_tt40:
170	setx SOC_PER_REG, %l7, %i0
171	stx %g0, [%i0]
172	nop
173	done
174	nop
175
176	My_Corrected_ECC_error_trap:
177	! Signal trap taken
178	setx EXECUTED, %l0, %o6
179	! save trap type value
180	rdpr %tt, %o7
181
182	check_desr_tt63:
183	ldxa [%g0]0x4c, %g2
184	nop
185	setx 0x8b00000000000000, %l0, %g3
186	subcc %g2, %g3, %g4
187	brnz %g4, test_failed
188
189	check_per_tt63:
190	setx SOC_PER_REG, %l7, %i0
191	ldx [%i0], %i1
192	setx 0x8000000000000000, %l7, %o3 !valid bit
193	set 0x1, %i2
194	sllx %i2, ERR_FIELD, %i3
195	or %i3, %o3, %i4
196	sub %i1, %i4, %i5
197	brnz %i5, test_failed
198	nop
199
200	clear_per_tt63:
201	setx SOC_PER_REG, %l7, %i0
202	stx %g0, [%i0]
203	nop
204	done
205	nop
206
207	/************************************************************************
208	Test case data start
209	************************************************************************/
210
211	SECTION .DATA DATA_VA=DMA_DATA_ADDR
212	attr_data {
213	Name = .DATA,
214	hypervisor,
215	compressimage
216	}
217
218	.data
219	.xword 0x0001020304050607
220	.xword 0x08090a0b0c0d0e0f
221	.xword 0x1011121314151617
222	.xword 0x18191a1b1c1d1e1f
223	.xword 0x2021222324252627
224	.xword 0x28292a2b2c2d2e2f
225	.xword 0x3031323334353637
226	.xword 0x38393a3b3c3d3e3f
227
228	.xword 0x4041424344454647
229	.xword 0x48494a4b4c4d4e4f
230	.xword 0x5051525354555657
231	.xword 0x58595a5b5c5d5e5f
232	.xword 0x6061626364656667
233	.xword 0x68696a6b6c6d6e6f
234	.xword 0x7071727374757677
235	.xword 0x78797a7b7c7d7e7f
236
237	.xword 0x8081828384858687
238	.xword 0x88898a8b8c8d8e8f
239	.xword 0x9091929394959697
240	.xword 0x98999a9b9c9d9e9f
241	.xword 0xa0a1a2a3a4a5a6a7
242	.xword 0xa8a9aaabacadaeaf
243	.xword 0xb0b1b2b3b4b5b6b7
244	.xword 0xb8b9babbbcbdbebf
245
246	.xword 0xc0c1c2c3c4c5c6c7
247	.xword 0xc8c9cacbcccdcecf
248	.xword 0xd0d1d2d3d4d5d6d7
249	.xword 0xd8d9dadbdcdddedf
250	.xword 0xe0e1e2e3e4e5e6e7
251	.xword 0xe8e9eaebecedeeef
252	.xword 0xf0f1f2f3f4f5f6f7
253	.xword 0xf8f9fafbfcfdfeff
254
255	.xword 0x0001020304050607
256	.xword 0x08090a0b0c0d0e0f
257	.xword 0x1011121314151617
258	.xword 0x18191a1b1c1d1e1f
259	.xword 0x2021222324252627
260	.xword 0x28292a2b2c2d2e2f
261	.xword 0x3031323334353637
262	.xword 0x38393a3b3c3d3e3f
263
264	.xword 0x4041424344454647
265	.xword 0x48494a4b4c4d4e4f
266	.xword 0x5051525354555657
267	.xword 0x58595a5b5c5d5e5f
268	.xword 0x6061626364656667
269	.xword 0x68696a6b6c6d6e6f
270	.xword 0x7071727374757677
271	.xword 0x78797a7b7c7d7e7f
272
273	.xword 0x8081828384858687
274	.xword 0x88898a8b8c8d8e8f
275	.xword 0x9091929394959697
276	.xword 0x98999a9b9c9d9e9f
277	.xword 0xa0a1a2a3a4a5a6a7
278	.xword 0xa8a9aaabacadaeaf
279	.xword 0xb0b1b2b3b4b5b6b7
280	.xword 0xb8b9babbbcbdbebf
281
282	.xword 0xc0c1c2c3c4c5c6c7
283	.xword 0xc8c9cacbcccdcecf
284	.xword 0xd0d1d2d3d4d5d6d7
285	.xword 0xd8d9dadbdcdddedf
286	.xword 0xe0e1e2e3e4e5e6e7
287	.xword 0xe8e9eaebecedeeef
288	.xword 0xf0f1f2f3f4f5f6f7
289	.xword 0xf8f9fafbfcfdfeff
290
291	/************************************************************************/