[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / vec / n2_ras_vec_dru_8core.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: n2_ras_vec_dru_8core.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
#define H_HT0_Sw_Recoverable_Error_0x40  My_Recoverable_Sw_error_trap

#define ENABLE_PCIE_LINK_TRAINING
/* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */
#define MAIN_PAGE_HV_ALSO

#include "err_defines.h"
#include "hboot.s"
#include "peu_defines.h"

#define DMA_DATA_ADDR           0x0000000123456700
#define DMA_DATA_BYP_ADDR1      0xfffc000123456700
#define DMA_DATA_BYP_ADDR2      0xfffc000123456780
#define DMA_DATA_BYP_ADDR3      0xfffc000123456800

#define DMA_DATA_ADDR           0x0000000123456700
#define DMA_DATA_BYP_SADDR      0xfffc000123456700
#define DMA_DATA_BYP_EADDR      0xfffc000123456800

#define ADDR1      		0xfffc00002000aa00
#define TEST_DATA1		0xaaaaaaaaaaaaaaaa
#define  DRAM_ERR_INJ_REG   	0x8400000290

#define ERR_BITS                0x2
#define ERR_BITS_EXPECT         0x8000000000000002


#ifdef L2_0
#define L2CS_REG		0xA900000000
#define L2_ERR_STAT_REG         0xAB00000000

#define DRAM_ERR_INJ_REG	0x8400000290
#define DRAM_ERR_STAT_REG	0x8400000280
   
#define L2_ADDR1                0x2000aa00
#define L2_ADDR2                0x1000aa00

#define ADDR1                   0xfffc00002000aa00
#endif


#ifdef L2_1
#define L2CS_REG		0xA900000040
#define L2_ERR_STAT_REG         0xAB00000040

#define DRAM_ERR_INJ_REG	0x8400000290
#define DRAM_ERR_STAT_REG	0x8400000280
   
#define L2_ADDR1                0x2000aa40
#define L2_ADDR2                0x1000aa40

#define ADDR1                   0xfffc00002000aa40
#endif

#ifdef L2_2
#define L2CS_REG		0xA900000080
#define L2_ERR_STAT_REG         0xAB00000080

#define DRAM_ERR_INJ_REG	0x8400001290
#define DRAM_ERR_STAT_REG	0x8400001280
   
#define L2_ADDR1                0x2000aa80
#define L2_ADDR2                0x1000aa80

#define ADDR1                   0xfffc00002000aa80
#endif


#ifdef L2_3
#define L2CS_REG		0xA9000000c0
#define L2_ERR_STAT_REG         0xAB000000c0

#define DRAM_ERR_INJ_REG	0x8400001290
#define DRAM_ERR_STAT_REG	0x8400001280
   
#define L2_ADDR1                0x2000aac0
#define L2_ADDR2                0x1000aac0

#define ADDR1                   0xfffc00002000aac0
#endif

#ifdef L2_4
#define L2CS_REG		0xA900000100
#define L2_ERR_STAT_REG         0xAB00000100

#define DRAM_ERR_INJ_REG	0x8400002290
#define DRAM_ERR_STAT_REG	0x8400002280
   
#define L2_ADDR1                0x2000ab00
#define L2_ADDR2                0x1000ab00

#define ADDR1                   0xfffc00002000ab00
#endif

#ifdef L2_5
#define L2CS_REG		0xA900000140
#define L2_ERR_STAT_REG         0xAB00000140

#define DRAM_ERR_INJ_REG	0x8400002290
#define DRAM_ERR_STAT_REG	0x8400002280
   
#define L2_ADDR1                0x2000ab40
#define L2_ADDR2                0x1000ab40

#define ADDR1                   0xfffc00002000ab40
#endif

#ifdef L2_6
#define L2CS_REG		0xA900000180
#define L2_ERR_STAT_REG         0xAB00000180

#define DRAM_ERR_INJ_REG	0x8400003290
#define DRAM_ERR_STAT_REG	0x8400003280
   
#define L2_ADDR1                0x2000ab80
#define L2_ADDR2                0x1000ab80

#define ADDR1                   0xfffc00002000ab80
#endif

#ifdef L2_7
#define L2CS_REG		0xA9000001c0
#define L2_ERR_STAT_REG         0xAB000001c0

#define DRAM_ERR_INJ_REG	0x8400003290
#define DRAM_ERR_STAT_REG	0x8400003280
   
#define L2_ADDR1                0x2000abc0
#define L2_ADDR2                0x1000abc0

#define ADDR1                   0xfffc00002000abc0
#endif


#define	L2_ES_W1C_VALUE		0xc03ffffc00000000
#define	DRAM_ES_W1C_VALUE  	0xffc0000000000000
 
/************************************************************************
   Test case code start
 ************************************************************************/
.text
.global main
.global  My_Corrected_ECC_error_trap
.global  My_Recoverable_Sw_error_trap

main:
        ta T_CHANGE_HPRIV
        nop

get_th_id_o0:
        ta      T_RD_THID

        cmp     %o1, TH_A
        be      main_th_a
        nop

        cmp     %o1, TH_B
        be      main_th_b
        nop

main_th_a:
	clr	%i7
	clr	%o6
	clr	%o7
	clr	%i0
	
	setx    0x3330000, %g7, %g3
	stx	%g0, [%g3]
wait_for_other_th:
	ldx	[%g3], %g4
	cmp	%g4, %g0
	be	%xcc, wait_for_other_th
	nop

disable_l1:
  	ldxa  [%g0] ASI_LSU_CONTROL, %l0
  	! Remove the lower 2 bits (I-Cache and D-Cache enables)
  	andn  %l0, 0x3, %l0
  	stxa  %l0, [%g0] ASI_LSU_CONTROL

set_DRAM_error_inject_ch0:
	mov   0x606, %l1                ! ECC Mask (2-bit error)
	mov   0x1, %l2
	sllx  %l2, DRAM_EI_SSHOT, %l3
	Or    %l1, %l3, %l1           ! Set single shot ;
	mov   0x1, %l2
	sllx  %l2, DRAM_EI_ENB, %l3
	or    %l1, %l3, %l1           ! Enable error injection for the next write
	setx  DRAM_ERR_INJ_REG, %l3, %g6
	stx   %l1, [%g6]
	membar 0x40

L2_err_enable:
        set     0x3, %l1
        mov     0xaa, %g2
        sllx    %g2, 32, %g2
        stx     %l1, [%g2]
        stx     %l1, [%g2 + 0x40]
        stx     %l1, [%g2 + 0x80]
        stx     %l1, [%g2 + 0xc0]
        stx     %l1, [%g2 + 0x100]
        stx     %l1, [%g2 + 0x140]
        stx     %l1, [%g2 + 0x180]
        stx     %l1, [%g2 + 0x1c0]

/*
set_L2_Directly_Mapped_Mode:
	setx  L2CS_REG, %l6, %g1
	mov   0x2, %l0
	stx   %l0, [%g1]
*/

set_L2_Directly_Mapped_Mode_errorsteer:
        setx    L2CS_PA0, %l6, %g1
        ldx     [%g1], %o6

        mov     0x2, %o5                ! L2_CSR_REG<1>=1 => DM mode

	set	TH_B, %o3
	sllx	%o3, 15, %o4		! thid of 2nd thread to be core-steering thread
        or      %o5, %o4, %o5

        or      %o6, %o5, %o6

        stx     %o6, [%g1]
        membar  0x40


store_to_L2_way0:
	setx  TEST_DATA1, %l0, %g5
!	setx  0x2000aa00, %l0, %g2  ! bits [21:18] select way
	setx  L2_ADDR1, %l0, %g2  ! bits [21:18] select way
	stx %g5, [%g2]
	membar #Sync

	! Storing to same L2 way0 but different tag,this will write to mcu
write_mcu_channel_0:
!	setx  0x1000aa00, %l0, %g3 ! bits [21:18] select way
	setx  L2_ADDR2, %l0, %g3 ! bits [21:18] select way
	stx %g5, [%g3]
	membar #Sync

piu_iommu:
        ! enable bypass in IOMMU
        setx    FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
        setx    FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
        stx     %g3, [%g2]
        ldx     [%g2], %g3

	/*******************************************************
		RDD from DMU
	********************************************************/

dma_rdd:
	nop
UsrEvnt_rdd:
        nop         ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_rdd)) -> EnablePCIeIgCmd ("DMARD_UE", ADDR1, ADDR1, "64'h40", 1, *, * )

        ldx     [%g2], %g3
        ldx     [%g2], %g3
        ldx     [%g2], %g3
        ldx     [%g2], %g3

l2_esr:
        mov     0x1, %g1
        sllx    %g1, L2ES_DRU, %g2

        mov     0x1, %g1
        sllx    %g1, L2ES_VEU, %g3

        or      %g2, %g3, %g4

        setx	0x7ffffffff0000000, %g7, %g5
	setx	0x30, %g7, %g6
check_l2_esr:
        cmp     %g6, %g0
        be      %xcc, test_failed
        nop
	dec	%g6

	setx	L2_ERR_STAT_REG, %g7, %g1  
	ldx	[%g1], %g2
	andcc	%g2, %g5, %g3			! Donot check L2ESR SYND bits and MEC

	cmp	%g3, %g4
	bne	%xcc, check_l2_esr 
	nop

cause_trap:
	setx	0x2222222222222222, %g3, %g2
	setx	0x20008000, %g3, %g1
	stx	%g2, [%g1]
	setx	0x80080000, %g3, %g1
	ldx	[%g1], %g2

	setx	0x20000040, %g3, %g1
	stx	 %g2, [%g1]
	setx	0x80080040, %g3, %g1
	ldx	[%g1], %g2

	setx	0x20000080, %g3, %g1
	stx	 %g2, [%g1]
	setx	0x80080000, %g3, %g1
	ldx	[%g1], %g2

	setx	0x200080c0, %g3, %g1
	stx	 %g2, [%g1]
	setx	0x800800c0, %g3, %g1
	ldx	[%g1], %g2

	setx	0x20000100, %g3, %g1
	stx	 %g2, [%g1]
	setx	0x80000100, %g3, %g1
	ldx	[%g1], %g2

	setx	0x20000140, %g3, %g1
	stx	 %g2, [%g1]
	setx	0x80000140, %g3, %g1
	ldx	[%g1], %g2

	setx	0x20000180, %g3, %g1
	stx	 %g2, [%g1]
	setx	0x80000180, %g3, %g1
	ldx	[%g1], %g2

	setx	0x200001c0, %g3, %g1
	stx	 %g2, [%g1]
	setx	0x800001c0, %g3, %g1
	ldx	[%g1], %g2

check_trap_th_a:
	! no trap to be taken
	cmp	%i7, %g0
	bne	test_failed
	nop

pass_th_a:
	ba	test_passed
	nop


/************************  TH B ***********************************/
main_th_b:
	clr	%i0


sync_th_b:
        setx    0x3330000, %g7, %g3
	setx	0xaaaaaaaaaaaaaaaa, %g7, %g4
        stx     %g4, [%g3]
	nop


	set	0x200, %o5		! timeout counter
wait_th_b:
	cmp	%o5, %g0
	be	test_failed
	nop

	cmp	%i0, %g0
	be	%xcc, wait_th_b
	nop

	nop; nop; nop; nop; nop
        nop; nop; nop; nop; nop
        nop; nop; nop; nop; nop
        nop; nop; nop; nop; nop
/*******************************************************************/


test_passed:
	EXIT_GOOD

test_failed:
	EXIT_BAD


/************************************************************************
	RAS
   	Trap Handlers
 ************************************************************************/
My_Recoverable_Sw_error_trap:
        ! Signal trap taken
        setx  EXECUTED, %l0, %o6
        ! save trap type value
        rdpr  %tt, %o7

        inc	%i7

check_desr_NcuTrap_tt40:
        ldxa  [%g0]0x4c, %g2
        nop

        setx    0xb300000000000000, %l0, %g3
        subcc   %g2, %g3, %g4
        brnz    %g4, l2_trap 
	nop

check_per_tt40:
	ba	test_failed
	nop


l2_trap:
	nop
	inc	%i0

check_desr_L2Trap_tt40:
        setx    0xb000000000000000, %l0, %g3
        subcc   %g2, %g3, %g4
        brnz    %g4, test_failed 
        nop

check_mcu2_esr_L2Trap_tt40:
        mov     0x1, %l1
        sllx    %l1, DRAM_ES_DAU, %l0

        setx  DRAM_ERR_STAT_REG, %l3, %g5  
        ldx   [%g5], %l3

        setx  0xffffffffffff0000, %l2, %l1
        andcc %l1, %l3, %l4                   ! Donot check SYND bits

        sub     %l0, %l4, %i4
        brnz    %i4, test_failed
        nop

clear_mcu_esr_L2Trap_tt40:
	setx	DRAM_ES_W1C_VALUE, %g7, %g6
        stx     %g6, [%g5]


check_L2_4_ESR_L2Trap_tt40:
        setx  	L2_ERR_STAT_REG, %l3, %g5  
        ldx   	[%g5], %l6

        setx  	0x7ffffffff0000000, %l3, %l0
        andcc 	%l0, %l6, %l5                   ! Donot check L2ESR SYND bits and MEU

        mov   	0x1, %l1
        sllx  	%l1, L2ES_DRU, %l0

        mov   	0x1, %l1
        sllx  	%l1, L2ES_VEU, %l2

        or    	%l0, %l2, %i4

        cmp   	%l5, %i4
        bne   	%xcc, test_failed
        nop

clear_l2_esr_L2Trap_tt40:
	setx	L2_ES_W1C_VALUE, %g7, %g6
	stx	%g6, [%g5]

trap_done_tt40:
       	retry 
        nop


My_Corrected_ECC_error_trap:
	ba	test_failed
        nop


/************************************************************************
   Test case data start
************************************************************************/

SECTION       .DATA DATA_VA=DMA_DATA_ADDR
attr_data {
      Name = .DATA,
      hypervisor,
      compressimage
}

.data
.global PCIAddr9
        .xword 0x0001020304050607
        .xword 0x08090a0b0c0d0e0f
        .xword 0x1011121314151617
        .xword 0x18191a1b1c1d1e1f
        .xword 0x2021222324252627
        .xword 0x28292a2b2c2d2e2f
        .xword 0x3031323334353637
        .xword 0x38393a3b3c3d3e3f

        .xword 0x4041424344454647
        .xword 0x48494a4b4c4d4e4f
        .xword 0x5051525354555657
        .xword 0x58595a5b5c5d5e5f
        .xword 0x6061626364656667
        .xword 0x68696a6b6c6d6e6f
        .xword 0x7071727374757677
        .xword 0x78797a7b7c7d7e7f

        .xword 0x8081828384858687
        .xword 0x88898a8b8c8d8e8f
        .xword 0x9091929394959697
        .xword 0x98999a9b9c9d9e9f
        .xword 0xa0a1a2a3a4a5a6a7
        .xword 0xa8a9aaabacadaeaf
        .xword 0xb0b1b2b3b4b5b6b7
        .xword 0xb8b9babbbcbdbebf

        .xword 0xc0c1c2c3c4c5c6c7
        .xword 0xc8c9cacbcccdcecf
        .xword 0xd0d1d2d3d4d5d6d7
        .xword 0xd8d9dadbdcdddedf
        .xword 0xe0e1e2e3e4e5e6e7
        .xword 0xe8e9eaebecedeeef
        .xword 0xf0f1f2f3f4f5f6f7
        .xword 0xf8f9fafbfcfdfeff

        .xword 0x0001020304050607
        .xword 0x08090a0b0c0d0e0f
        .xword 0x1011121314151617
        .xword 0x18191a1b1c1d1e1f
        .xword 0x2021222324252627
        .xword 0x28292a2b2c2d2e2f
        .xword 0x3031323334353637
        .xword 0x38393a3b3c3d3e3f

        .xword 0x4041424344454647
        .xword 0x48494a4b4c4d4e4f
        .xword 0x5051525354555657
        .xword 0x58595a5b5c5d5e5f
        .xword 0x6061626364656667
        .xword 0x68696a6b6c6d6e6f
        .xword 0x7071727374757677
        .xword 0x78797a7b7c7d7e7f

        .xword 0x8081828384858687
        .xword 0x88898a8b8c8d8e8f
        .xword 0x9091929394959697
        .xword 0x98999a9b9c9d9e9f
        .xword 0xa0a1a2a3a4a5a6a7
        .xword 0xa8a9aaabacadaeaf
        .xword 0xb0b1b2b3b4b5b6b7
        .xword 0xb8b9babbbcbdbebf

        .xword 0xc0c1c2c3c4c5c6c7
        .xword 0xc8c9cacbcccdcecf
        .xword 0xd0d1d2d3d4d5d6d7
        .xword 0xd8d9dadbdcdddedf
        .xword 0xe0e1e2e3e4e5e6e7
        .xword 0xe8e9eaebecedeeef
        .xword 0xf0f1f2f3f4f5f6f7
        .xword 0xf8f9fafbfcfdfeff

/************************************************************************/
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: n2_ras_vec_dru_8core.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
	39	#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
	40
	41	#define ENABLE_PCIE_LINK_TRAINING
	42	/* #define MAIN_PAGE_NUCLEUS_ALSO / / Access main in priviledge mode */
	43	#define MAIN_PAGE_HV_ALSO
	44
	45	#include "err_defines.h"
	46	#include "hboot.s"
	47	#include "peu_defines.h"
	48
	49	#define DMA_DATA_ADDR 0x0000000123456700
	50	#define DMA_DATA_BYP_ADDR1 0xfffc000123456700
	51	#define DMA_DATA_BYP_ADDR2 0xfffc000123456780
	52	#define DMA_DATA_BYP_ADDR3 0xfffc000123456800
	53
	54	#define DMA_DATA_ADDR 0x0000000123456700
	55	#define DMA_DATA_BYP_SADDR 0xfffc000123456700
	56	#define DMA_DATA_BYP_EADDR 0xfffc000123456800
	57
	58	#define ADDR1 0xfffc00002000aa00
	59	#define TEST_DATA1 0xaaaaaaaaaaaaaaaa
	60	#define DRAM_ERR_INJ_REG 0x8400000290
	61
	62	#define ERR_BITS 0x2
	63	#define ERR_BITS_EXPECT 0x8000000000000002
	64
65
66	#ifdef L2_0
67	#define L2CS_REG 0xA900000000
68	#define L2_ERR_STAT_REG 0xAB00000000
69
70	#define DRAM_ERR_INJ_REG 0x8400000290
71	#define DRAM_ERR_STAT_REG 0x8400000280
72
73	#define L2_ADDR1 0x2000aa00
74	#define L2_ADDR2 0x1000aa00
75
76	#define ADDR1 0xfffc00002000aa00
77	#endif
78
79
80	#ifdef L2_1
81	#define L2CS_REG 0xA900000040
82	#define L2_ERR_STAT_REG 0xAB00000040
83
84	#define DRAM_ERR_INJ_REG 0x8400000290
85	#define DRAM_ERR_STAT_REG 0x8400000280
86
87	#define L2_ADDR1 0x2000aa40
88	#define L2_ADDR2 0x1000aa40
89
90	#define ADDR1 0xfffc00002000aa40
91	#endif
92
93	#ifdef L2_2
94	#define L2CS_REG 0xA900000080
95	#define L2_ERR_STAT_REG 0xAB00000080
96
97	#define DRAM_ERR_INJ_REG 0x8400001290
98	#define DRAM_ERR_STAT_REG 0x8400001280
99
100	#define L2_ADDR1 0x2000aa80
101	#define L2_ADDR2 0x1000aa80
102
103	#define ADDR1 0xfffc00002000aa80
104	#endif
105
106
107	#ifdef L2_3
108	#define L2CS_REG 0xA9000000c0
109	#define L2_ERR_STAT_REG 0xAB000000c0
110
111	#define DRAM_ERR_INJ_REG 0x8400001290
112	#define DRAM_ERR_STAT_REG 0x8400001280
113
114	#define L2_ADDR1 0x2000aac0
115	#define L2_ADDR2 0x1000aac0
116
117	#define ADDR1 0xfffc00002000aac0
118	#endif
119
120	#ifdef L2_4
121	#define L2CS_REG 0xA900000100
122	#define L2_ERR_STAT_REG 0xAB00000100
123
124	#define DRAM_ERR_INJ_REG 0x8400002290
125	#define DRAM_ERR_STAT_REG 0x8400002280
126
127	#define L2_ADDR1 0x2000ab00
128	#define L2_ADDR2 0x1000ab00
129
130	#define ADDR1 0xfffc00002000ab00
131	#endif
132
133	#ifdef L2_5
134	#define L2CS_REG 0xA900000140
135	#define L2_ERR_STAT_REG 0xAB00000140
136
137	#define DRAM_ERR_INJ_REG 0x8400002290
138	#define DRAM_ERR_STAT_REG 0x8400002280
139
140	#define L2_ADDR1 0x2000ab40
141	#define L2_ADDR2 0x1000ab40
142
143	#define ADDR1 0xfffc00002000ab40
144	#endif
145
146	#ifdef L2_6
147	#define L2CS_REG 0xA900000180
148	#define L2_ERR_STAT_REG 0xAB00000180
149
150	#define DRAM_ERR_INJ_REG 0x8400003290
151	#define DRAM_ERR_STAT_REG 0x8400003280
152
153	#define L2_ADDR1 0x2000ab80
154	#define L2_ADDR2 0x1000ab80
155
156	#define ADDR1 0xfffc00002000ab80
157	#endif
158
159	#ifdef L2_7
160	#define L2CS_REG 0xA9000001c0
161	#define L2_ERR_STAT_REG 0xAB000001c0
162
163	#define DRAM_ERR_INJ_REG 0x8400003290
164	#define DRAM_ERR_STAT_REG 0x8400003280
165
166	#define L2_ADDR1 0x2000abc0
167	#define L2_ADDR2 0x1000abc0
168
169	#define ADDR1 0xfffc00002000abc0
170	#endif
171
172
173	#define L2_ES_W1C_VALUE 0xc03ffffc00000000
174	#define DRAM_ES_W1C_VALUE 0xffc0000000000000
175
176	/************************************************************************
177	Test case code start
178	************************************************************************/
179	.text
180	.global main
181	.global My_Corrected_ECC_error_trap
182	.global My_Recoverable_Sw_error_trap
183
184	main:
185	ta T_CHANGE_HPRIV
186	nop
187
188	get_th_id_o0:
189	ta T_RD_THID
190
191	cmp %o1, TH_A
192	be main_th_a
193	nop
194
195	cmp %o1, TH_B
196	be main_th_b
197	nop
198
199	main_th_a:
200	clr %i7
201	clr %o6
202	clr %o7
203	clr %i0
204
205	setx 0x3330000, %g7, %g3
206	stx %g0, [%g3]
207	wait_for_other_th:
208	ldx [%g3], %g4
209	cmp %g4, %g0
210	be %xcc, wait_for_other_th
211	nop
212
213	disable_l1:
214	ldxa [%g0] ASI_LSU_CONTROL, %l0
215	! Remove the lower 2 bits (I-Cache and D-Cache enables)
216	andn %l0, 0x3, %l0
217	stxa %l0, [%g0] ASI_LSU_CONTROL
218
219	set_DRAM_error_inject_ch0:
220	mov 0x606, %l1 ! ECC Mask (2-bit error)
221	mov 0x1, %l2
222	sllx %l2, DRAM_EI_SSHOT, %l3
223	Or %l1, %l3, %l1 ! Set single shot ;
224	mov 0x1, %l2
225	sllx %l2, DRAM_EI_ENB, %l3
226	or %l1, %l3, %l1 ! Enable error injection for the next write
227	setx DRAM_ERR_INJ_REG, %l3, %g6
228	stx %l1, [%g6]
229	membar 0x40
230
231	L2_err_enable:
232	set 0x3, %l1
233	mov 0xaa, %g2
234	sllx %g2, 32, %g2
235	stx %l1, [%g2]
236	stx %l1, [%g2 + 0x40]
237	stx %l1, [%g2 + 0x80]
238	stx %l1, [%g2 + 0xc0]
239	stx %l1, [%g2 + 0x100]
240	stx %l1, [%g2 + 0x140]
241	stx %l1, [%g2 + 0x180]
242	stx %l1, [%g2 + 0x1c0]
243
244	/*
245	set_L2_Directly_Mapped_Mode:
246	setx L2CS_REG, %l6, %g1
247	mov 0x2, %l0
248	stx %l0, [%g1]
249	*/
250
251	set_L2_Directly_Mapped_Mode_errorsteer:
252	setx L2CS_PA0, %l6, %g1
253	ldx [%g1], %o6
254
255	mov 0x2, %o5 ! L2_CSR_REG<1>=1 => DM mode
256
257	set TH_B, %o3
258	sllx %o3, 15, %o4 ! thid of 2nd thread to be core-steering thread
259	or %o5, %o4, %o5
260
261	or %o6, %o5, %o6
262
263	stx %o6, [%g1]
264	membar 0x40
265
266
267	store_to_L2_way0:
268	setx TEST_DATA1, %l0, %g5
269	! setx 0x2000aa00, %l0, %g2 ! bits [21:18] select way
270	setx L2_ADDR1, %l0, %g2 ! bits [21:18] select way
271	stx %g5, [%g2]
272	membar #Sync
273
274	! Storing to same L2 way0 but different tag,this will write to mcu
275	write_mcu_channel_0:
276	! setx 0x1000aa00, %l0, %g3 ! bits [21:18] select way
277	setx L2_ADDR2, %l0, %g3 ! bits [21:18] select way
278	stx %g5, [%g3]
279	membar #Sync
280
281	piu_iommu:
282	! enable bypass in IOMMU
283	setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
284	setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
285	stx %g3, [%g2]
286	ldx [%g2], %g3
287
288	/*******************************************************
289	RDD from DMU
290	********************************************************/
291
292	dma_rdd:
293	nop
294	UsrEvnt_rdd:
295	nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_rdd)) -> EnablePCIeIgCmd ("DMARD_UE", ADDR1, ADDR1, "64'h40", 1, , )
296
297	ldx [%g2], %g3
298	ldx [%g2], %g3
299	ldx [%g2], %g3
300	ldx [%g2], %g3
301
302	l2_esr:
303	mov 0x1, %g1
304	sllx %g1, L2ES_DRU, %g2
305
306	mov 0x1, %g1
307	sllx %g1, L2ES_VEU, %g3
308
309	or %g2, %g3, %g4
310
311	setx 0x7ffffffff0000000, %g7, %g5
312	setx 0x30, %g7, %g6
313	check_l2_esr:
314	cmp %g6, %g0
315	be %xcc, test_failed
316	nop
317	dec %g6
318
319	setx L2_ERR_STAT_REG, %g7, %g1
320	ldx [%g1], %g2
321	andcc %g2, %g5, %g3 ! Donot check L2ESR SYND bits and MEC
322
323	cmp %g3, %g4
324	bne %xcc, check_l2_esr
325	nop
326
327	cause_trap:
328	setx 0x2222222222222222, %g3, %g2
329	setx 0x20008000, %g3, %g1
330	stx %g2, [%g1]
331	setx 0x80080000, %g3, %g1
332	ldx [%g1], %g2
333
334	setx 0x20000040, %g3, %g1
335	stx %g2, [%g1]
336	setx 0x80080040, %g3, %g1
337	ldx [%g1], %g2
338
339	setx 0x20000080, %g3, %g1
340	stx %g2, [%g1]
341	setx 0x80080000, %g3, %g1
342	ldx [%g1], %g2
343
344	setx 0x200080c0, %g3, %g1
345	stx %g2, [%g1]
346	setx 0x800800c0, %g3, %g1
347	ldx [%g1], %g2
348
349	setx 0x20000100, %g3, %g1
350	stx %g2, [%g1]
351	setx 0x80000100, %g3, %g1
352	ldx [%g1], %g2
353
354	setx 0x20000140, %g3, %g1
355	stx %g2, [%g1]
356	setx 0x80000140, %g3, %g1
357	ldx [%g1], %g2
358
359	setx 0x20000180, %g3, %g1
360	stx %g2, [%g1]
361	setx 0x80000180, %g3, %g1
362	ldx [%g1], %g2
363
364	setx 0x200001c0, %g3, %g1
365	stx %g2, [%g1]
366	setx 0x800001c0, %g3, %g1
367	ldx [%g1], %g2
368
369	check_trap_th_a:
370	! no trap to be taken
371	cmp %i7, %g0
372	bne test_failed
373	nop
374
375	pass_th_a:
376	ba test_passed
377	nop
378
379
380
381	/********************** TH B *********************************/
382	main_th_b:
383	clr %i0
384
385
386	sync_th_b:
387	setx 0x3330000, %g7, %g3
388	setx 0xaaaaaaaaaaaaaaaa, %g7, %g4
389	stx %g4, [%g3]
390	nop
391
392
393	set 0x200, %o5 ! timeout counter
394	wait_th_b:
395	cmp %o5, %g0
396	be test_failed
397	nop
398
399	cmp %i0, %g0
400	be %xcc, wait_th_b
401	nop
402
403	nop; nop; nop; nop; nop
404	nop; nop; nop; nop; nop
405	nop; nop; nop; nop; nop
406	nop; nop; nop; nop; nop
407	/*******************************************************************/
408
409
410
411	test_passed:
412	EXIT_GOOD
413
414	test_failed:
415	EXIT_BAD
416
417
418	/************************************************************************
419	RAS
420	Trap Handlers
421	************************************************************************/
422	My_Recoverable_Sw_error_trap:
423	! Signal trap taken
424	setx EXECUTED, %l0, %o6
425	! save trap type value
426	rdpr %tt, %o7
427
428	inc %i7
429
430	check_desr_NcuTrap_tt40:
431	ldxa [%g0]0x4c, %g2
432	nop
433
434	setx 0xb300000000000000, %l0, %g3
435	subcc %g2, %g3, %g4
436	brnz %g4, l2_trap
437	nop
438
439	check_per_tt40:
440	ba test_failed
441	nop
442
443
444	l2_trap:
445	nop
446	inc %i0
447
448	check_desr_L2Trap_tt40:
449	setx 0xb000000000000000, %l0, %g3
450	subcc %g2, %g3, %g4
451	brnz %g4, test_failed
452	nop
453
454	check_mcu2_esr_L2Trap_tt40:
455	mov 0x1, %l1
456	sllx %l1, DRAM_ES_DAU, %l0
457
458	setx DRAM_ERR_STAT_REG, %l3, %g5
459	ldx [%g5], %l3
460
461	setx 0xffffffffffff0000, %l2, %l1
462	andcc %l1, %l3, %l4 ! Donot check SYND bits
463
464	sub %l0, %l4, %i4
465	brnz %i4, test_failed
466	nop
467
468	clear_mcu_esr_L2Trap_tt40:
469	setx DRAM_ES_W1C_VALUE, %g7, %g6
470	stx %g6, [%g5]
471
472
473	check_L2_4_ESR_L2Trap_tt40:
474	setx L2_ERR_STAT_REG, %l3, %g5
475	ldx [%g5], %l6
476
477	setx 0x7ffffffff0000000, %l3, %l0
478	andcc %l0, %l6, %l5 ! Donot check L2ESR SYND bits and MEU
479
480	mov 0x1, %l1
481	sllx %l1, L2ES_DRU, %l0
482
483	mov 0x1, %l1
484	sllx %l1, L2ES_VEU, %l2
485
486	or %l0, %l2, %i4
487
488	cmp %l5, %i4
489	bne %xcc, test_failed
490	nop
491
492	clear_l2_esr_L2Trap_tt40:
493	setx L2_ES_W1C_VALUE, %g7, %g6
494	stx %g6, [%g5]
495
496	trap_done_tt40:
497	retry
498	nop
499
500
501
502	My_Corrected_ECC_error_trap:
503	ba test_failed
504	nop
505
506
507	/************************************************************************
508	Test case data start
509	************************************************************************/
510
511	SECTION .DATA DATA_VA=DMA_DATA_ADDR
512	attr_data {
513	Name = .DATA,
514	hypervisor,
515	compressimage
516	}
517
518	.data
519	.global PCIAddr9
520	.xword 0x0001020304050607
521	.xword 0x08090a0b0c0d0e0f
522	.xword 0x1011121314151617
523	.xword 0x18191a1b1c1d1e1f
524	.xword 0x2021222324252627
525	.xword 0x28292a2b2c2d2e2f
526	.xword 0x3031323334353637
527	.xword 0x38393a3b3c3d3e3f
528
529	.xword 0x4041424344454647
530	.xword 0x48494a4b4c4d4e4f
531	.xword 0x5051525354555657
532	.xword 0x58595a5b5c5d5e5f
533	.xword 0x6061626364656667
534	.xword 0x68696a6b6c6d6e6f
535	.xword 0x7071727374757677
536	.xword 0x78797a7b7c7d7e7f
537
538	.xword 0x8081828384858687
539	.xword 0x88898a8b8c8d8e8f
540	.xword 0x9091929394959697
541	.xword 0x98999a9b9c9d9e9f
542	.xword 0xa0a1a2a3a4a5a6a7
543	.xword 0xa8a9aaabacadaeaf
544	.xword 0xb0b1b2b3b4b5b6b7
545	.xword 0xb8b9babbbcbdbebf
546
547	.xword 0xc0c1c2c3c4c5c6c7
548	.xword 0xc8c9cacbcccdcecf
549	.xword 0xd0d1d2d3d4d5d6d7
550	.xword 0xd8d9dadbdcdddedf
551	.xword 0xe0e1e2e3e4e5e6e7
552	.xword 0xe8e9eaebecedeeef
553	.xword 0xf0f1f2f3f4f5f6f7
554	.xword 0xf8f9fafbfcfdfeff
555
556	.xword 0x0001020304050607
557	.xword 0x08090a0b0c0d0e0f
558	.xword 0x1011121314151617
559	.xword 0x18191a1b1c1d1e1f
560	.xword 0x2021222324252627
561	.xword 0x28292a2b2c2d2e2f
562	.xword 0x3031323334353637
563	.xword 0x38393a3b3c3d3e3f
564
565	.xword 0x4041424344454647
566	.xword 0x48494a4b4c4d4e4f
567	.xword 0x5051525354555657
568	.xword 0x58595a5b5c5d5e5f
569	.xword 0x6061626364656667
570	.xword 0x68696a6b6c6d6e6f
571	.xword 0x7071727374757677
572	.xword 0x78797a7b7c7d7e7f
573
574	.xword 0x8081828384858687
575	.xword 0x88898a8b8c8d8e8f
576	.xword 0x9091929394959697
577	.xword 0x98999a9b9c9d9e9f
578	.xword 0xa0a1a2a3a4a5a6a7
579	.xword 0xa8a9aaabacadaeaf
580	.xword 0xb0b1b2b3b4b5b6b7
581	.xword 0xb8b9babbbcbdbebf
582
583	.xword 0xc0c1c2c3c4c5c6c7
584	.xword 0xc8c9cacbcccdcecf
585	.xword 0xd0d1d2d3d4d5d6d7
586	.xword 0xd8d9dadbdcdddedf
587	.xword 0xe0e1e2e3e4e5e6e7
588	.xword 0xe8e9eaebecedeeef
589	.xword 0xf0f1f2f3f4f5f6f7
590	.xword 0xf8f9fafbfcfdfeff
591
592	/************************************************************************/
593