[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / vec / n2_ras_vec_l2_da_ce.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: n2_ras_vec_l2_da_ce.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define MAIN_PAGE_HV_ALSO


#define  	L2_ENTRY_PA        	0xa000000000
#define  	TEST_DATA1         	0x5555555555555555
#define	 	L2_ENTRY_PA0       	0x30000008
#define  	L2_ES_W1C_VALUE    	0xc03ffffc00000000

#define	 	SPARC_ES_W1C_VALUE 	0xefffffff
#define  	TT_SW_Error        	0x40

#define  	L2_ESR_MASK	0xf03ffffff0000000 
#define 	L2_VEC		36
#define		L2_LDWC		51
#define         L2_LDAC         53
 
#include "hboot.s"
#include "asi_s.h"
#include "err_defines.h"

.text
.global	 main

main:


  ! Boot code does not provide TLB translation for IO address space
	ta    T_CHANGE_HPRIV


disable_l1_DCache:
	ldxa  	[%g0] ASI_LSU_CONTROL, %l0
	! Remove bit 2
	andn  	%l0, 0x2, %l0
	stxa  	%l0, [%g0] ASI_LSU_CONTROL

set_L2_Directly_Mapped_Mode:
	setx  	L2CS_PA0, %l6, %g1      ! Bit 1 in L2 Control Status Register
	mov   	0x2, %l0
	stx   	%l0, [%g1]

store_to_L2:
	setx  	TEST_DATA1, %l0, %g5

store_to_L2_way0:
	setx	0x3000aa00, %l0, %g2  ! bits [21:18] select way
	stx 	%g5, [%g2] 
	stx 	%g5, [%g2+8]
	nop
	nop; nop; nop; nop; nop
        nop; nop; nop; nop; nop
        nop; nop; nop; nop; nop

	membar 	#Sync

L2_diag_load:
	setx  	0x3ffff8, %l0, %l2      ! Mask for extracting [21:3]
	setx	L2_ENTRY_PA, %l0, %g4
	and   	%g2, %l2, %g5           !g2 has L2 PA, 
	or	%g5, %g4, %g5           !g5 now has Diagnostic Data Array address 
	ldx	[%g5], %g6
	membar 	#Sync

! Flip one bits to inject error
	xor 	%g6, 0x200, %g6
	stx	%g6, [%g5]
	membar 	#Sync

reading_back_0:                 !Load to L2 again to get the error
	setx  	0x3000aa00, %l0, %g2
	ldx   	[%g2], %l6
	membar 	#Sync  


check_l2_ESR:
  	setx  	L2ES_PA0, %l6, %g1
  	ldx   	[%g1], %g2

	setx	L2_ESR_MASK, %g7, %g3
	and	%g2, %g3, %g4

	mov	0x1, %i1
	sllx	%i1, L2_VEC, %i2	
	sllx	%i1, L2_LDAC, %i3
	or 	%i2, %i3, %i4

	cmp	%g4, %i4
	bne	%xcc, test_fail
	nop

clear_l2_ESR:
	setx	L2_ES_W1C_VALUE, %g7, %g2
	stx	%g2, [%g1]
	membar	#Sync
     
check_l2_EAR:
	setx  	L2EA_PA0, %g7, %g1
	ldx   	[%g1], %g2
	setx  	0x3000aa00, %g7, %g3
	cmp	%g3, %g2
	bne	test_fail
	nop

clear_l2_EAR:
        stx     %g0, [%g1]
        membar  #Sync
    
	membar #Sync


/**********************************************
	LDWC
***********************************************/
write_back:         
	setx  0x1000aa00, %l0, %g2
	ldx   [%g2], %l6
	add	%g2, 0x200, %g2
        ldx   [%g2], %l6
	membar #Sync

        setx  0x2000aa00, %l0, %g2
        ldx   [%g2], %l6


check_l2_ESR_LDWC:
        setx  L2ES_PA0, %l6, %g1
        ldx   [%g1], %g2

        setx    L2_ESR_MASK, %g7, %g3
        and     %g2, %g3, %g4

        mov     0x1, %i1
        sllx    %i1, L2_VEC, %i2
        sllx    %i1, L2_LDWC, %i3
        or      %i2, %i3, %i4

        cmp     %g4, %i4
        bne     %xcc, test_fail
        nop

check_l2_EAR_LDWC:
        setx    L2EA_PA0, %g7, %g1
        ldx     [%g1], %g2
        setx    0x3000aa00, %g7, %g3
        cmp     %g3, %g2
        bne     test_fail
        nop


  ba    test_pass
  nop


/*******************************************************
 * Exit code
 *******************************************************/

test_pass:
	ta  T_GOOD_TRAP

test_fail:
	ta  T_BAD_TRAP
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: n2_ras_vec_l2_da_ce.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define MAIN_PAGE_HV_ALSO
	39
	40
	41	#define L2_ENTRY_PA 0xa000000000
	42	#define TEST_DATA1 0x5555555555555555
	43	#define L2_ENTRY_PA0 0x30000008
	44	#define L2_ES_W1C_VALUE 0xc03ffffc00000000
	45
	46	#define SPARC_ES_W1C_VALUE 0xefffffff
	47	#define TT_SW_Error 0x40
	48
	49	#define L2_ESR_MASK 0xf03ffffff0000000
	50	#define L2_VEC 36
	51	#define L2_LDWC 51
	52	#define L2_LDAC 53
	53
	54	#include "hboot.s"
	55	#include "asi_s.h"
	56	#include "err_defines.h"
	57
	58	.text
	59	.global main
	60
	61	main:
	62
	63
	64	! Boot code does not provide TLB translation for IO address space
65	ta T_CHANGE_HPRIV
66
67
68	disable_l1_DCache:
69	ldxa [%g0] ASI_LSU_CONTROL, %l0
70	! Remove bit 2
71	andn %l0, 0x2, %l0
72	stxa %l0, [%g0] ASI_LSU_CONTROL
73
74	set_L2_Directly_Mapped_Mode:
75	setx L2CS_PA0, %l6, %g1 ! Bit 1 in L2 Control Status Register
76	mov 0x2, %l0
77	stx %l0, [%g1]
78
79	store_to_L2:
80	setx TEST_DATA1, %l0, %g5
81
82	store_to_L2_way0:
83	setx 0x3000aa00, %l0, %g2 ! bits [21:18] select way
84	stx %g5, [%g2]
85	stx %g5, [%g2+8]
86	nop
87	nop; nop; nop; nop; nop
88	nop; nop; nop; nop; nop
89	nop; nop; nop; nop; nop
90
91	membar #Sync
92
93	L2_diag_load:
94	setx 0x3ffff8, %l0, %l2 ! Mask for extracting [21:3]
95	setx L2_ENTRY_PA, %l0, %g4
96	and %g2, %l2, %g5 !g2 has L2 PA,
97	or %g5, %g4, %g5 !g5 now has Diagnostic Data Array address
98	ldx [%g5], %g6
99	membar #Sync
100
101	! Flip one bits to inject error
102	xor %g6, 0x200, %g6
103	stx %g6, [%g5]
104	membar #Sync
105
106	reading_back_0: !Load to L2 again to get the error
107	setx 0x3000aa00, %l0, %g2
108	ldx [%g2], %l6
109	membar #Sync
110
111
112	check_l2_ESR:
113	setx L2ES_PA0, %l6, %g1
114	ldx [%g1], %g2
115
116	setx L2_ESR_MASK, %g7, %g3
117	and %g2, %g3, %g4
118
119	mov 0x1, %i1
120	sllx %i1, L2_VEC, %i2
121	sllx %i1, L2_LDAC, %i3
122	or %i2, %i3, %i4
123
124	cmp %g4, %i4
125	bne %xcc, test_fail
126	nop
127
128	clear_l2_ESR:
129	setx L2_ES_W1C_VALUE, %g7, %g2
130	stx %g2, [%g1]
131	membar #Sync
132
133	check_l2_EAR:
134	setx L2EA_PA0, %g7, %g1
135	ldx [%g1], %g2
136	setx 0x3000aa00, %g7, %g3
137	cmp %g3, %g2
138	bne test_fail
139	nop
140
141	clear_l2_EAR:
142	stx %g0, [%g1]
143	membar #Sync
144
145	membar #Sync
146
147
148	/**********************************************
149	LDWC
150	***********************************************/
151	write_back:
152	setx 0x1000aa00, %l0, %g2
153	ldx [%g2], %l6
154	add %g2, 0x200, %g2
155	ldx [%g2], %l6
156	membar #Sync
157
158	setx 0x2000aa00, %l0, %g2
159	ldx [%g2], %l6
160
161
162	check_l2_ESR_LDWC:
163	setx L2ES_PA0, %l6, %g1
164	ldx [%g1], %g2
165
166	setx L2_ESR_MASK, %g7, %g3
167	and %g2, %g3, %g4
168
169	mov 0x1, %i1
170	sllx %i1, L2_VEC, %i2
171	sllx %i1, L2_LDWC, %i3
172	or %i2, %i3, %i4
173
174	cmp %g4, %i4
175	bne %xcc, test_fail
176	nop
177
178	check_l2_EAR_LDWC:
179	setx L2EA_PA0, %g7, %g1
180	ldx [%g1], %g2
181	setx 0x3000aa00, %g7, %g3
182	cmp %g3, %g2
183	bne test_fail
184	nop
185
186
187	ba test_pass
188	nop
189
190
191
192	/*******************************************************
193	* Exit code
194	*******************************************************/
195
196	test_pass:
197	ta T_GOOD_TRAP
198
199	test_fail:
200	ta T_BAD_TRAP