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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: n2_ras_vec_l2_off_dau_trap.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define MAIN_PAGE_NUCLEUS_ALSO | |
39 | #define MAIN_PAGE_HV_ALSO | |
40 | ||
41 | #define L2_ERR_STAT_REG 0xAB00000000 | |
42 | #define L2_ERR_ADDR_REG 0xAC00000000 | |
43 | ||
44 | #define TEST_DATA0 0x1000100081c3e008 | |
45 | #define TEST_DATA1 0x2000200081c3e008 | |
46 | #define TEST_DATA2 0x3000300081c3e008 | |
47 | #define L2_ES_W1C_VALUE 0xc03ffffc00000000 | |
48 | #define DRAM_ES_W1C_VALUE 0xfe00000000000000 | |
49 | ||
50 | #ifdef MCU0 | |
51 | #define L2_BANK_ADDR 0x0 | |
52 | #define MCU_BANK_ADDR 0x0 | |
53 | #define DRAM_ERR_INJ_REG 0x8400000290 | |
54 | #define DRAM_ERR_STAT_REG 0x8400000280 | |
55 | #define ERROR_ADDR 0x20200000 | |
56 | #endif | |
57 | ||
58 | #ifdef MCU1 | |
59 | #define L2_BANK_ADDR 0x80 | |
60 | #define MCU_BANK_ADDR 0x80 | |
61 | #define DRAM_ERR_INJ_REG 0x8400001290 | |
62 | #define DRAM_ERR_STAT_REG 0x8400001280 | |
63 | ||
64 | ||
65 | #endif | |
66 | ||
67 | #ifdef MCU2 | |
68 | #define L2_BANK_ADDR 0x100 | |
69 | #define MCU_BANK_ADDR 0x100 | |
70 | #define DRAM_ERR_INJ_REG 0x8400002290 | |
71 | #define DRAM_ERR_STAT_REG 0x8400002280 | |
72 | #define ERROR_ADDR 0x20200100 | |
73 | ||
74 | #endif | |
75 | ||
76 | #ifdef MCU3 | |
77 | #define L2_BANK_ADDR 0x180 | |
78 | #define MCU_BANK_ADDR 0x180 | |
79 | #define DRAM_ERR_INJ_REG 0x8400003290 | |
80 | #define DRAM_ERR_STAT_REG 0x8400003280 | |
81 | ||
82 | ||
83 | #endif | |
84 | ||
85 | #define L2_ESR_MASK 0xf03ffffff0000000 | |
86 | ||
87 | ||
88 | #include "hboot.s" | |
89 | #include "asi_s.h" | |
90 | #include "err_defines.h" | |
91 | ||
92 | ||
93 | .text | |
94 | .global main | |
95 | .global My_Corrected_ECC_error_trap | |
96 | ||
97 | ||
98 | ||
99 | main: | |
100 | ta T_CHANGE_HPRIV | |
101 | disable_l1: | |
102 | ldxa [%g0] ASI_LSU_CONTROL, %l0 | |
103 | ! Remove the lower 2 bits (I-Cache and D-Cache enables) | |
104 | andn %l0, 0x3, %l0 | |
105 | stxa %l0, [%g0] ASI_LSU_CONTROL | |
106 | ||
107 | ||
108 | clear_dram_esr_0: | |
109 | ! Clear DRAM Error status register (Bit[63:57] write-1-clear) | |
110 | setx DRAM_ES_W1C_VALUE, %l0, %l5 | |
111 | setx DRAM_ERR_STAT_REG, %l3, %g5 | |
112 | ! add %g5, MCU_BANK_ADDR, %g5 | |
113 | stx %l5, [%g5] | |
114 | ||
115 | set_DRAM_error_inject_ch0: | |
116 | mov 0x606, %l1 ! ECC Mask (Multi-bit error) | |
117 | mov 0x1, %l2 | |
118 | sllx %l2, DRAM_EI_SSHOT, %l3 | |
119 | Or %l1, %l3, %l1 ! Set single shot ; | |
120 | mov 0x1, %l2 | |
121 | sllx %l2, DRAM_EI_ENB, %l3 | |
122 | or %l1, %l3, %l1 ! Enable error injection for the next write | |
123 | setx DRAM_ERR_INJ_REG, %l3, %g6 | |
124 | ! add %g6, MCU_BANK_ADDR, %g6 | |
125 | stx %l1, [%g6] | |
126 | membar 0x40 | |
127 | ||
128 | enable_err_reporting: | |
129 | setx L2EE_PA0, %l0, %l1 | |
130 | add %l1, L2_BANK_ADDR, %l1 | |
131 | ldx [%l1], %l2 | |
132 | mov 0x3, %l0 | |
133 | or %l2, %l0, %l2 | |
134 | stx %l2, [%l1] | |
135 | ||
136 | ||
137 | ! Write 1 to clear L2 Error status registers | |
138 | clear_l2_ESR: | |
139 | setx L2ES_PA0, %l3, %l4 | |
140 | add %l4, L2_BANK_ADDR, %l4 | |
141 | stx %l5, [%l4] | |
142 | nop | |
143 | ||
144 | ||
145 | ||
146 | set_L2_Off_Mode_errorsteer: | |
147 | setx L2CS_PA0, %l6, %g1 | |
148 | ldx [%g1], %o6 | |
149 | ||
150 | mov 0x1, %o5 ! L2_CSR_REG<0>=1 => L2 Off mode | |
151 | ||
152 | ldxa [%g0]ASI_INTR_ID, %o4 ! get the thread id; for core-portable | |
153 | sllx %o4, 15, %o4 ! L2_CSR_REG<21:15> = ERROR_STEER | |
154 | ||
155 | or %o5, %o4, %o5 | |
156 | ||
157 | or %o6, %o5, %o6 | |
158 | ||
159 | stx %o6, [%g1] | |
160 | membar 0x40 | |
161 | ||
162 | ||
163 | store_to_L2_way0: | |
164 | setx 0x2200aa00, %l0, %g2 ! bits [21:18] select way | |
165 | add %g2, L2_BANK_ADDR, %g2 | |
166 | stx %g5, [%g2] | |
167 | membar #Sync | |
168 | read_error_address_ch0: | |
169 | ldx [%g2], %l1 | |
170 | membar #Sync | |
171 | ||
172 | ||
173 | ! Storing to same L2 way0 but different tag,this will write to mcu | |
174 | write_mcu_channel_0: | |
175 | setx 0x2100aa00, %l0, %g3 ! bits [21:18] select way | |
176 | add %g3, L2_BANK_ADDR, %g3 | |
177 | stx %g5, [%g3] | |
178 | membar #Sync | |
179 | ||
180 | /** | |
181 | *read_error_address_ch0: | |
182 | * ldx [%g2], %l1 | |
183 | * membar #Sync | |
184 | *! ldx [%g3], %l2 | |
185 | *! membar #Sync | |
186 | **/ | |
187 | ||
188 | ||
189 | check_DRAM_ESR_0: | |
190 | setx DRAM_ERR_STAT_REG, %l3, %g5 | |
191 | ! add %g5, MCU_BANK_ADDR, %g5 | |
192 | ldx [%g5], %l6 | |
193 | setx 0xffc0000000000000, %l0,%o2 | |
194 | and %l6,%o2,%l6 | |
195 | ||
196 | ||
197 | compute_dram_ESR: | |
198 | mov 0x1, %l1 | |
199 | sllx %l1, DRAM_ES_DAU, %l0 | |
200 | ||
201 | ||
202 | verify_dram_ESR: | |
203 | cmp %l0, %l6 | |
204 | bne %xcc, test_fail | |
205 | nop | |
206 | ||
207 | check_L2_ESR_0: | |
208 | setx L2_ERR_STAT_REG, %l3, %g5 | |
209 | add %g5, L2_BANK_ADDR, %g5 | |
210 | ldx [%g5], %l6 | |
211 | ||
212 | compute_L2_ESR: | |
213 | setx L2_ESR_MASK, %l3, %l0 ! Avoid VCID check; SYND check | |
214 | andcc %l0, %l6, %l6 ! Donot check L2ESR SYND bits | |
215 | ||
216 | mov 0x1, %l1 | |
217 | sllx %l1, L2ES_DAU, %l0 | |
218 | mov 0x1, %l1 | |
219 | sllx %l1, L2ES_VEU, %l2 | |
220 | or %l0, %l2, %l3 | |
221 | ||
222 | verify_L2_ESR: | |
223 | cmp %l6, %l3 | |
224 | bne %xcc, test_fail | |
225 | nop | |
226 | ||
227 | ||
228 | setx L2EA_PA0, %l2, %l3 | |
229 | add %l3, L2_BANK_ADDR, %l3 | |
230 | check_l2_EAR: | |
231 | ldx [%l3], %l4 | |
232 | ! Error address is the physical address of the cache line (PA[5:0] 0) | |
233 | setx 0x2200aa00, %l0, %g2 ! bits [21:18] select way | |
234 | add %g2, L2_BANK_ADDR, %g2 | |
235 | ||
236 | setx 0xffffffffc0, %l0,%o2 | |
237 | and %l4, %o2, %l4 | |
238 | cmp %l4, %g2 | |
239 | bne %xcc, test_fail | |
240 | nop | |
241 | ||
242 | check_Corr_err_trap: | |
243 | ! Check if a Corrected ECC Error Trap happened | |
244 | set EXECUTED, %l0 | |
245 | cmp %o0, %l0 | |
246 | bne test_fail | |
247 | nop | |
248 | mov TT_Data_Access_Error, %l0 | |
249 | cmp %o1, %l0 | |
250 | bne test_fail | |
251 | nop | |
252 | ||
253 | ||
254 | ba test_pass | |
255 | nop | |
256 | ||
257 | ||
258 | /******************************************************* | |
259 | * Exit code | |
260 | *******************************************************/ | |
261 | ||
262 | test_pass: | |
263 | ta T_GOOD_TRAP | |
264 | ||
265 | ||
266 | test_fail: | |
267 | ta T_BAD_TRAP | |
268 | ||
269 | ||
270 |