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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: n2_ras_vec_mcu_dac.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define MAIN_PAGE_NUCLEUS_ALSO | |
39 | #define MAIN_PAGE_HV_ALSO | |
40 | ||
41 | #define L2_ERR_STAT_REG 0xAB00000000 | |
42 | #define L2_ERR_ADDR_REG 0xAC00000000 | |
43 | ||
44 | #define TEST_DATA0 0x1000100081c3e008 | |
45 | #define TEST_DATA1 0x2000200081c3e008 | |
46 | #define TEST_DATA2 0x3000300081c3e008 | |
47 | #define L2_ES_W1C_VALUE 0xc03ffffc00000000 | |
48 | #define DRAM_ES_W1C_VALUE 0xfe00000000000000 | |
49 | ||
50 | #ifdef MCU0 | |
51 | #define L2_BANK_ADDR 0x0 | |
52 | #define MCU_BANK_ADDR 0x0 | |
53 | #define DRAM_ERR_INJ_REG 0x8400000290 | |
54 | #define DRAM_ERR_STAT_REG 0x8400000280 | |
55 | #define ERROR_ADDR 0x20200000 | |
56 | #endif | |
57 | ||
58 | #ifdef MCU1 | |
59 | #define L2_BANK_ADDR 0x80 | |
60 | #define MCU_BANK_ADDR 0x80 | |
61 | #define DRAM_ERR_INJ_REG 0x8400001290 | |
62 | #define DRAM_ERR_STAT_REG 0x8400001280 | |
63 | ||
64 | ||
65 | #endif | |
66 | ||
67 | #ifdef MCU2 | |
68 | #define L2_BANK_ADDR 0x100 | |
69 | #define MCU_BANK_ADDR 0x100 | |
70 | #define DRAM_ERR_INJ_REG 0x8400002290 | |
71 | #define DRAM_ERR_STAT_REG 0x8400002280 | |
72 | #define ERROR_ADDR 0x20200100 | |
73 | ||
74 | #endif | |
75 | ||
76 | #ifdef MCU3 | |
77 | #define L2_BANK_ADDR 0x180 | |
78 | #define MCU_BANK_ADDR 0x180 | |
79 | #define DRAM_ERR_INJ_REG 0x8400003290 | |
80 | #define DRAM_ERR_STAT_REG 0x8400003280 | |
81 | ||
82 | ||
83 | #endif | |
84 | ||
85 | ||
86 | #include "hboot.s" | |
87 | #include "asi_s.h" | |
88 | #include "err_defines.h" | |
89 | ||
90 | ||
91 | .text | |
92 | .global main | |
93 | ||
94 | ||
95 | main: | |
96 | ta T_CHANGE_HPRIV | |
97 | disable_l1: | |
98 | ldxa [%g0] ASI_LSU_CONTROL, %l0 | |
99 | ! Remove the lower 2 bits (I-Cache and D-Cache enables) | |
100 | andn %l0, 0x3, %l0 | |
101 | stxa %l0, [%g0] ASI_LSU_CONTROL | |
102 | ||
103 | ||
104 | clear_dram_esr_0: | |
105 | ! Clear DRAM Error status register (Bit[63:57] write-1-clear) | |
106 | setx DRAM_ES_W1C_VALUE, %l0, %l5 | |
107 | setx DRAM_ERR_STAT_REG, %l3, %g5 | |
108 | ! add %g5, MCU_BANK_ADDR, %g5 | |
109 | stx %l5, [%g5] | |
110 | ||
111 | set_DRAM_error_inject_ch0: | |
112 | mov 0x2, %l1 ! ECC Mask (1-bit error) | |
113 | mov 0x1, %l2 | |
114 | sllx %l2, DRAM_EI_SSHOT, %l3 | |
115 | Or %l1, %l3, %l1 ! Set single shot ; | |
116 | mov 0x1, %l2 | |
117 | sllx %l2, DRAM_EI_ENB, %l3 | |
118 | or %l1, %l3, %l1 ! Enable error injection for the next write | |
119 | setx DRAM_ERR_INJ_REG, %l3, %g6 | |
120 | ! add %g6, MCU_BANK_ADDR, %g6 | |
121 | stx %l1, [%g6] | |
122 | membar 0x40 | |
123 | ||
124 | ! Write 1 to clear L2 Error status registers | |
125 | clear_l2_ESR: | |
126 | setx L2ES_PA0, %l3, %l4 | |
127 | add %l4, L2_BANK_ADDR, %l4 | |
128 | stx %l5, [%l4] | |
129 | nop | |
130 | ||
131 | store_to_L2: | |
132 | setx TEST_DATA1, %l0, %g5 | |
133 | ||
134 | ||
135 | set_L2_Directly_Mapped_Mode: | |
136 | setx L2CS_PA0, %l6, %g1 | |
137 | add %g1, L2_BANK_ADDR, %g1 | |
138 | mov 0x2, %l0 | |
139 | stx %l0, [%g1] | |
140 | ||
141 | ||
142 | store_to_L2_way0: | |
143 | setx 0x2200aa00, %l0, %g2 ! bits [21:18] select way | |
144 | add %g2, L2_BANK_ADDR, %g2 | |
145 | stx %g5, [%g2] | |
146 | stx %g5, [%g2+8] | |
147 | membar #Sync | |
148 | ||
149 | ! Storing to same L2 way0 but different tag,this will write to mcu | |
150 | write_mcu_channel_0: | |
151 | setx 0x2100aa00, %l0, %g3 ! bits [21:18] select way | |
152 | add %g3, L2_BANK_ADDR, %g3 | |
153 | stx %g5, [%g3] | |
154 | stx %g5, [%g3+8] | |
155 | membar #Sync | |
156 | ||
157 | ||
158 | read_error_address_ch0: | |
159 | ldx [%g2], %l1 | |
160 | membar #Sync | |
161 | ! ldx [%g3], %l2 | |
162 | ! membar #Sync | |
163 | ||
164 | ||
165 | check_DRAM_ESR_0: | |
166 | setx DRAM_ERR_STAT_REG, %l3, %g5 | |
167 | ! add %g5, MCU_BANK_ADDR, %g5 | |
168 | ldx [%g5], %l6 | |
169 | ||
170 | compute_dram_ESR: | |
171 | mov 0x1, %l1 | |
172 | sllx %l1, DRAM_ES_DAC, %l0 | |
173 | set 0x0002, %l3 ! 16-bit Syndrome - for SECC, it's the mask nibble-reversed | |
174 | or %l0, %l3, %l0 ! %l0 has expected value | |
175 | ||
176 | verify_dram_ESR: | |
177 | cmp %l0, %l6 | |
178 | bne %xcc, test_fail | |
179 | nop | |
180 | ||
181 | check_L2_ESR_0: | |
182 | setx L2_ERR_STAT_REG, %l3, %g5 | |
183 | add %g5, L2_BANK_ADDR, %g5 | |
184 | ldx [%g5], %l6 | |
185 | ||
186 | compute_L2_ESR: | |
187 | setx 0xf0cffffff0000000, %l3, %l0 ! take out VCID check | |
188 | andcc %l0, %l6, %l0 ! Donot check L2ESR SYND bits | |
189 | mov 0x1, %l1 | |
190 | sllx %l1, L2ES_DAC, %l0 | |
191 | mov 0x1, %l1 | |
192 | sllx %l1, L2ES_VEC, %l2 | |
193 | or %l0, %l2, %l3 | |
194 | ||
195 | verify_L2_ESR: | |
196 | cmp %l6, %l3 | |
197 | bne %xcc, test_fail | |
198 | nop | |
199 | ||
200 | ||
201 | setx L2EA_PA0, %l2, %l3 | |
202 | add %l3, L2_BANK_ADDR, %l3 | |
203 | check_l2_EAR: | |
204 | ldx [%l3], %l4 | |
205 | ! Error address is the physical address of the cache line (PA[5:0] 0) | |
206 | setx 0x2200aa00, %l0, %g2 ! bits [21:18] select way | |
207 | add %g2, L2_BANK_ADDR, %g2 | |
208 | ||
209 | setx 0xffffffffc0, %l0,%o2 | |
210 | and %l4, %o2, %l4 | |
211 | cmp %l4, %g2 | |
212 | bne %xcc, test_fail | |
213 | nop | |
214 | ||
215 | ||
216 | ||
217 | ba test_pass | |
218 | nop | |
219 | ||
220 | /******************************************************* | |
221 | * Exit code | |
222 | *******************************************************/ | |
223 | ||
224 | test_pass: | |
225 | ta T_GOOD_TRAP | |
226 | ||
227 | ||
228 | test_fail: | |
229 | ta T_BAD_TRAP | |
230 | ||
231 | ||
232 |