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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: n2_ras_vec_mcu_dac_strm.s | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | #define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap | |
39 | ||
40 | #define MAIN_PAGE_NUCLEUS_ALSO | |
41 | #define MAIN_PAGE_HV_ALSO | |
42 | ||
43 | #define TEST_DATA1 0x2000200081c3e008 | |
44 | ||
45 | #define L2_ES_W1C_VALUE 0xc03ffffc00000000 | |
46 | #define DRAM_ES_W1C_VALUE 0xfe00000000000000 | |
47 | ||
48 | #ifdef MCU0 | |
49 | #define L2_BANK_ADDR 0x0 | |
50 | #define MCU_BANK_ADDR 0x0 | |
51 | #define DRAM_ERR_INJ_REG 0x8400000290 | |
52 | #define DRAM_ERR_STAT_REG 0x8400000280 | |
53 | #define DRAM_ERR_ADDR_REG 0x8400000288 | |
54 | #define DRAM_SCRB_FREQ_REG 0x8400000018 | |
55 | #define DRAM_SCRB_ENB_REG 0x8400000040 | |
56 | #define L2_ERR_STAT_REG 0xAB00000000 | |
57 | #define ERROR_ADDR 0x22000000 | |
58 | #define WB_ADDR 0x24000000 | |
59 | #define FILL_ADDR 0x26000000 | |
60 | #endif | |
61 | ||
62 | #ifdef MCU1 | |
63 | #define L2_BANK_ADDR 0x80 | |
64 | #define MCU_BANK_ADDR 0x80 | |
65 | #define DRAM_ERR_INJ_REG 0x8400001290 | |
66 | #define DRAM_ERR_STAT_REG 0x8400001280 | |
67 | #define DRAM_ERR_ADDR_REG 0x8400001288 | |
68 | #define DRAM_SCRB_FREQ_REG 0x8400001018 | |
69 | #define DRAM_SCRB_ENB_REG 0x8400001040 | |
70 | #define L2_ERR_STAT_REG 0xAB00000080 | |
71 | #define ERROR_ADDR 0x22000080 | |
72 | #define WB_ADDR 0x24000080 | |
73 | #define FILL_ADDR 0x26000080 | |
74 | #endif | |
75 | ||
76 | #ifdef MCU2 | |
77 | #define L2_BANK_ADDR 0x100 | |
78 | #define MCU_BANK_ADDR 0x100 | |
79 | #define DRAM_ERR_INJ_REG 0x8400002290 | |
80 | #define DRAM_ERR_STAT_REG 0x8400002280 | |
81 | #define DRAM_ERR_ADDR_REG 0x8400002288 | |
82 | #define DRAM_SCRB_FREQ_REG 0x8400002018 | |
83 | #define DRAM_SCRB_ENB_REG 0x8400002040 | |
84 | #define L2_ERR_STAT_REG 0xAB00000100 | |
85 | #define ERROR_ADDR 0x22000100 | |
86 | #define WB_ADDR 0x24000100 | |
87 | #define FILL_ADDR 0x26000100 | |
88 | #endif | |
89 | ||
90 | #ifdef MCU3 | |
91 | #define L2_BANK_ADDR 0x180 | |
92 | #define MCU_BANK_ADDR 0x180 | |
93 | #define DRAM_ERR_INJ_REG 0x8400003290 | |
94 | #define DRAM_ERR_STAT_REG 0x8400003280 | |
95 | #define DRAM_ERR_ADDR_REG 0x8400003288 | |
96 | #define DRAM_SCRB_FREQ_REG 0x8400003018 | |
97 | #define DRAM_SCRB_ENB_REG 0x8400003040 | |
98 | #define L2_ERR_STAT_REG 0xAB00000180 | |
99 | #define ERROR_ADDR 0x22000180 | |
100 | #define WB_ADDR 0x24000180 | |
101 | #define FILL_ADDR 0x26000180 | |
102 | #endif | |
103 | ||
104 | ||
105 | #include "hboot.s" | |
106 | #include "asi_s.h" | |
107 | #include "err_defines.h" | |
108 | ||
109 | ||
110 | .text | |
111 | .global main | |
112 | .global My_Corrected_ECC_error_trap | |
113 | ||
114 | ||
115 | main: | |
116 | ta T_CHANGE_HPRIV | |
117 | clr %o0 | |
118 | clr %o1 | |
119 | ||
120 | disable_l1: | |
121 | ldxa [%g0] ASI_LSU_CONTROL, %l0 | |
122 | ! Remove the lower 2 bits (I-Cache and D-Cache enables) | |
123 | andn %l0, 0x3, %l0 | |
124 | stxa %l0, [%g0] ASI_LSU_CONTROL | |
125 | ||
126 | set_DRAM_scrub_frequency: | |
127 | setx DRAM_SCRB_FREQ_REG, %l0, %l1 | |
128 | mov 0x1, %l0 | |
129 | stx %l0, [%l1] | |
130 | membar #Sync | |
131 | ||
132 | ||
133 | enable_err_reporting: | |
134 | setx L2EE_PA0, %l0, %l1 | |
135 | add %l1, L2_BANK_ADDR, %l1 | |
136 | ldx [%l1], %l2 | |
137 | mov 0x3, %l0 | |
138 | or %l2, %l0, %l2 | |
139 | stx %l2, [%l1] | |
140 | ||
141 | membar #Sync | |
142 | ||
143 | ||
144 | ||
145 | ! MSA 01/04/07: Set Continuous error Injection | |
146 | set_DRAM_error_inject_ch0: | |
147 | mov 0x2, %l1 ! ECC Mask (1-bit error) | |
148 | ! mov 0x1, %l2 | |
149 | ! sllx %l2, DRAM_EI_SSHOT, %l3 | |
150 | ! Or %l1, %l3, %l1 | |
151 | mov 0x1, %l2 | |
152 | sllx %l2, DRAM_EI_ENB, %l3 | |
153 | or %l1, %l3, %l1 ! Enable error injection for the next write | |
154 | setx DRAM_ERR_INJ_REG, %l3, %g6 | |
155 | stx %l1, [%g6] | |
156 | membar 0x40 | |
157 | ||
158 | ||
159 | store_to_L2: | |
160 | setx TEST_DATA1, %l0, %g5 | |
161 | ||
162 | ||
163 | set_L2_Directly_Mapped_Mode_errorsteer: | |
164 | setx L2CS_PA0, %l6, %g1 | |
165 | add %g1, L2_BANK_ADDR, %g1 | |
166 | ||
167 | ldx [%g1], %o6 | |
168 | ||
169 | mov 0x2, %o5 ! L2_CSR_REG<1>=1 => DM mode | |
170 | ||
171 | ldxa [%g0]ASI_INTR_ID, %o4 ! get the thread id; for core-portable | |
172 | sllx %o4, 15, %o4 ! L2_CSR_REG<21:15> = ERROR_STEER | |
173 | ||
174 | or %o5, %o4, %o5 | |
175 | ||
176 | or %o6, %o5, %o6 | |
177 | ||
178 | stx %o6, [%g1] | |
179 | membar 0x40 | |
180 | ||
181 | /*************** Make line dirty**************/ | |
182 | set LOOP, %g6 | |
183 | setx ERROR_ADDR, %l0, %g2 | |
184 | store_1: | |
185 | stx %g5, [%g2] | |
186 | add %g2, 0x200, %g2 ! next index; same tag | |
187 | dec %g6 | |
188 | cmp %g6, %g0 | |
189 | bne store_1 | |
190 | nop | |
191 | ||
192 | /************ WB *********************/ | |
193 | set LOOP, %g6 | |
194 | setx WB_ADDR, %l0, %g2 | |
195 | store_alias: | |
196 | stx %g5, [%g2] | |
197 | add %g2, 0x200, %g2 ! next index; same tag | |
198 | dec %g6 | |
199 | cmp %g6, %g0 | |
200 | bne store_alias | |
201 | nop | |
202 | ||
203 | /******* Read Errror Addr *************/ | |
204 | set LOOP, %g6 | |
205 | setx ERROR_ADDR, %l0, %g2 | |
206 | read_err_addr: | |
207 | clr %o0 ! clear %o0 each time before error addr access | |
208 | ldx [%g2], %g7 | |
209 | ||
210 | /******* wait for trap ****************/ | |
211 | setx FILL_ADDR, %l0, %g3 | |
212 | clr %i5 | |
213 | trap_wait: | |
214 | cmp %o0, %g0 | |
215 | bne %xcc, next_error_addr | |
216 | nop | |
217 | ldx [%g3], %g1 ! cause a fill | |
218 | nop; nop; nop | |
219 | nop; nop; nop | |
220 | nop; nop; nop | |
221 | ||
222 | add %g3, 0x200, %g3 | |
223 | inc %i5 | |
224 | cmp %i5, 0x100 ! trap timeout | |
225 | bne trap_wait | |
226 | nop | |
227 | ||
228 | next_error_addr: | |
229 | add %g2, 0x200, %g2 ! next index; same tag | |
230 | dec %g6 | |
231 | cmp %g6, %g0 | |
232 | bne read_err_addr | |
233 | nop | |
234 | /******* Read Errror Addr Done *************/ | |
235 | ||
236 | ||
237 | ba test_pass | |
238 | nop | |
239 | ||
240 | ||
241 | /**************** Trap Handler *******************/ | |
242 | My_Corrected_ECC_error_trap: | |
243 | ! Signal trap taken | |
244 | setx EXECUTED, %l0, %o0 | |
245 | ! save trap type value | |
246 | rdpr %tt, %o1 | |
247 | ||
248 | check_l2esr: | |
249 | setx L2_ERR_STAT_REG, %g7, %g1 | |
250 | ldx [%g1], %g2 | |
251 | ||
252 | setx 0xb03ffffc00000000, %g7, %g4 ! take out MEC, VCID, SYND check | |
253 | and %g2, %g4, %g2 | |
254 | ||
255 | setx 0x41000000000, %g7, %g3 ! VEC, DAC | |
256 | cmp %g2, %g3 | |
257 | bne %xcc, test_fail | |
258 | nop | |
259 | ||
260 | clear_l2esr: | |
261 | setx L2_ES_W1C_VALUE, %g7, %g2 | |
262 | stx %g2, [%g1] | |
263 | ||
264 | check_mcuesr: | |
265 | setx DRAM_ERR_STAT_REG, %g7, %g1 | |
266 | ldx [%g1], %g2 | |
267 | setx 0xbfc0000000000000, %g7, %g4 | |
268 | and %g2, %g4, %g2 | |
269 | ||
270 | setx 0x2000000000000000, %g7, %g3 !DAC | |
271 | cmp %g2, %g3 | |
272 | bne %xcc, test_fail | |
273 | nop | |
274 | ||
275 | ||
276 | clear_mcuesr: | |
277 | setx DRAM_ES_W1C_VALUE, %g7, %g2 | |
278 | stx %g2, [%g1] | |
279 | ||
280 | check_DESR: | |
281 | ldxa [%g0] 0x4c, %g2 | |
282 | setx 0x8900000000000000, %g7, %g3 | |
283 | cmp %g2, %g3 | |
284 | ! bne %xcc, test_fail | |
285 | nop | |
286 | ||
287 | retry | |
288 | nop | |
289 | ||
290 | ba test_pass | |
291 | nop | |
292 | ||
293 | /******************************************************* | |
294 | * Exit code | |
295 | *******************************************************/ | |
296 | ||
297 | test_pass: | |
298 | ta T_GOOD_TRAP | |
299 | ||
300 | ||
301 | test_fail: | |
302 | ta T_BAD_TRAP | |
303 | ||
304 | ||
305 |