[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / vec / n2_ras_vec_mcu_dac_trap.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: n2_ras_vec_mcu_dac_trap.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap

#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO

#define  L2_ERR_STAT_REG    0xAB00000000
#define  L2_ERR_ADDR_REG    0xAC00000000

#define  TEST_DATA0         0x1000100081c3e008
#define  TEST_DATA1         0x2000200081c3e008
#define  TEST_DATA2         0x3000300081c3e008
#define  L2_ES_W1C_VALUE    0xc03ffffc00000000
#define  DRAM_ES_W1C_VALUE  0xfe00000000000000

#ifdef MCU0
#define L2_BANK_ADDR        0x0       
#define MCU_BANK_ADDR       0x0
#define  DRAM_ERR_INJ_REG   0x8400000290
#define  DRAM_ERR_STAT_REG  0x8400000280
#define	 ERROR_ADDR	    0x20200000
#endif

#ifdef MCU1
#define L2_BANK_ADDR        0x80
#define MCU_BANK_ADDR       0x80
#define  DRAM_ERR_INJ_REG   0x8400001290
#define  DRAM_ERR_STAT_REG  0x8400001280


#endif

#ifdef MCU2
#define L2_BANK_ADDR        0x100
#define MCU_BANK_ADDR       0x100
#define  DRAM_ERR_INJ_REG   0x8400002290
#define  DRAM_ERR_STAT_REG  0x8400002280
#define  ERROR_ADDR         0x20200100

#endif

#ifdef MCU3
#define L2_BANK_ADDR        0x180
#define MCU_BANK_ADDR       0x180
#define  DRAM_ERR_INJ_REG   0x8400003290
#define  DRAM_ERR_STAT_REG  0x8400003280


#endif


#define		L2_ESR_MASK	0xf03ffffff0000000
#define		L2_VEC		36
#define		L2_LDWC		51
#define		L2_LDAC		53
#define         L2_DAC 		42

#define		MCU_DAC		61


#include "hboot.s"
#include "asi_s.h"
#include "err_defines.h"


.text
.global  main
.global  My_Corrected_ECC_error_trap


main:
  ta T_CHANGE_HPRIV


disable_l1:
  ldxa  [%g0] ASI_LSU_CONTROL, %l0
  ! Remove the lower 2 bits (I-Cache and D-Cache enables)
  andn  %l0, 0x3, %l0
  stxa  %l0, [%g0] ASI_LSU_CONTROL


set_DRAM_error_inject_ch0:
  mov   0x2, %l1                ! ECC Mask (1-bit error)
  mov   0x1, %l2 		
  sllx  %l2, DRAM_EI_SSHOT, %l3
  Or    %l1, %l3, %l1           ! Set single shot ; 
  mov   0x1, %l2
  sllx  %l2, DRAM_EI_ENB, %l3
  or    %l1, %l3, %l1           ! Enable error injection for the next write
  setx  DRAM_ERR_INJ_REG, %l3, %g6 
  stx   %l1, [%g6]
  membar 0x40

enable_err_reporting:
  setx L2EE_PA0, %l0, %l1
  add   %l1, L2_BANK_ADDR, %l1
  ldx  [%l1], %l2
  mov  0x3, %l0
  or   %l2, %l0, %l2
  stx  %l2, [%l1]

store_to_L2:
  setx  TEST_DATA1, %l0, %g5


set_L2_Directly_Mapped_Mode_errorsteer:
        setx    L2CS_PA0, %l6, %g1
        ldx     [%g1], %o6

        mov     0x2, %o5                ! L2_CSR_REG<1>=1 => DM mode

        ldxa    [%g0]ASI_INTR_ID, %o4   ! get the thread id; for core-portable
        sllx    %o4, 15, %o4            ! L2_CSR_REG<21:15> = ERROR_STEER

        or      %o5, %o4, %o5

        or      %o6, %o5, %o6

        stx     %o6, [%g1]
        membar  0x40


store_to_L2_way0:
  setx	0x2200aa00, %l0, %g2  ! bits [21:18] select way
  add	%g2, L2_BANK_ADDR, %g2
  stx %g5, [%g2]
  stx %g5, [%g2+8]
  membar #Sync

! Storing to same L2 way0 but different tag,this will write to mcu
write_mcu_channel_0:
  setx	0x2100aa00, %l0, %g3 ! bits [21:18] select way
  add	%g3, L2_BANK_ADDR, %g3
  stx %g5, [%g3]
  stx %g5, [%g3+8]
  membar #Sync


read_error_address_ch0:
  ldx	[%g2], %l1
  membar #Sync

	! Loop until gets first	 trap
	set	0x100, %o2
loop_1:
        dec	%o2
	cmp	%o2, %g0
	be	test_fail
	nop

	nop
	cmp	%i0, 0x1
	bne	loop_1
	nop

pass:   
  	ba    test_pass
  	nop


/************************************
       	Trap Handler 
************************************/
My_Corrected_ECC_error_trap:
	inc	%i0

check_l2_ESR_0x63:
	setx  L2ES_PA0, %l6, %g1
	ldx   [%g1], %g2

	setx	L2_ESR_MASK, %g7, %g3
	and	%g2, %g3, %g4

check_DAC_0x63:
	mov	0x1, %i1
	sllx	%i1, L2_VEC, %i2
	sllx	%i1, L2_DAC, %i3
	or	%i2, %i3, %i4

	cmp	%g4, %i4
	bne	%xcc, test_fail
	nop

clear_l2_ESR_0x63:
	setx	L2_ES_W1C_VALUE, %g7, %g2
	stx	%g2, [%g1]
	membar	#Sync

check_l2_EAR_0x63:
	setx	L2EA_PA0, %g7, %g1
	ldx	[%g1], %g2
	setx	0xffffffffffffffc0, %g7, %g5 
	and	%g2, %g5, %g2
	setx	0x2200aa00, %g7, %g3
	cmp	%g3, %g2
	bne	test_fail
	nop

check_mcu_esr:
	setx	DRAM_ERR_STAT_REG, %g7, %g1
	ldx	[%g1], %g2

	mov	0x1, %g6
	sllx	%g6, MCU_DAC, %g3
	set	0x0002, %g5
	or	%g3, %g5, %g4

	cmp	%g4, %g2
	bne	%xcc, test_fail
	nop

	
check_DESR_L2C_0x63:
	ldxa	[%g0] 0x4c, %g1
	setx	0xff00000000000000, %g7, %g2
	and	%g1, %g2, %g3
	setx	0x8900000000000000, %g7, %g4
	cmp	%g3, %g4
	bne	 %xcc, test_fail
        nop

	retry
        nop


/*******************************************************
 * Exit code
 *******************************************************/

test_pass:
ta  T_GOOD_TRAP


test_fail:
ta  T_BAD_TRAP
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: n2_ras_vec_mcu_dac_trap.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
	39
	40	#define MAIN_PAGE_NUCLEUS_ALSO
	41	#define MAIN_PAGE_HV_ALSO
	42
	43	#define L2_ERR_STAT_REG 0xAB00000000
	44	#define L2_ERR_ADDR_REG 0xAC00000000
	45
	46	#define TEST_DATA0 0x1000100081c3e008
	47	#define TEST_DATA1 0x2000200081c3e008
	48	#define TEST_DATA2 0x3000300081c3e008
	49	#define L2_ES_W1C_VALUE 0xc03ffffc00000000
	50	#define DRAM_ES_W1C_VALUE 0xfe00000000000000
	51
	52	#ifdef MCU0
	53	#define L2_BANK_ADDR 0x0
	54	#define MCU_BANK_ADDR 0x0
	55	#define DRAM_ERR_INJ_REG 0x8400000290
	56	#define DRAM_ERR_STAT_REG 0x8400000280
	57	#define ERROR_ADDR 0x20200000
	58	#endif
	59
	60	#ifdef MCU1
	61	#define L2_BANK_ADDR 0x80
	62	#define MCU_BANK_ADDR 0x80
	63	#define DRAM_ERR_INJ_REG 0x8400001290
	64	#define DRAM_ERR_STAT_REG 0x8400001280
65
66
67	#endif
68
69	#ifdef MCU2
70	#define L2_BANK_ADDR 0x100
71	#define MCU_BANK_ADDR 0x100
72	#define DRAM_ERR_INJ_REG 0x8400002290
73	#define DRAM_ERR_STAT_REG 0x8400002280
74	#define ERROR_ADDR 0x20200100
75
76	#endif
77
78	#ifdef MCU3
79	#define L2_BANK_ADDR 0x180
80	#define MCU_BANK_ADDR 0x180
81	#define DRAM_ERR_INJ_REG 0x8400003290
82	#define DRAM_ERR_STAT_REG 0x8400003280
83
84
85	#endif
86
87
88	#define L2_ESR_MASK 0xf03ffffff0000000
89	#define L2_VEC 36
90	#define L2_LDWC 51
91	#define L2_LDAC 53
92	#define L2_DAC 42
93
94	#define MCU_DAC 61
95
96
97
98	#include "hboot.s"
99	#include "asi_s.h"
100	#include "err_defines.h"
101
102
103	.text
104	.global main
105	.global My_Corrected_ECC_error_trap
106
107
108
109	main:
110	ta T_CHANGE_HPRIV
111
112
113	disable_l1:
114	ldxa [%g0] ASI_LSU_CONTROL, %l0
115	! Remove the lower 2 bits (I-Cache and D-Cache enables)
116	andn %l0, 0x3, %l0
117	stxa %l0, [%g0] ASI_LSU_CONTROL
118
119
120	set_DRAM_error_inject_ch0:
121	mov 0x2, %l1 ! ECC Mask (1-bit error)
122	mov 0x1, %l2
123	sllx %l2, DRAM_EI_SSHOT, %l3
124	Or %l1, %l3, %l1 ! Set single shot ;
125	mov 0x1, %l2
126	sllx %l2, DRAM_EI_ENB, %l3
127	or %l1, %l3, %l1 ! Enable error injection for the next write
128	setx DRAM_ERR_INJ_REG, %l3, %g6
129	stx %l1, [%g6]
130	membar 0x40
131
132	enable_err_reporting:
133	setx L2EE_PA0, %l0, %l1
134	add %l1, L2_BANK_ADDR, %l1
135	ldx [%l1], %l2
136	mov 0x3, %l0
137	or %l2, %l0, %l2
138	stx %l2, [%l1]
139
140	store_to_L2:
141	setx TEST_DATA1, %l0, %g5
142
143
144
145	set_L2_Directly_Mapped_Mode_errorsteer:
146	setx L2CS_PA0, %l6, %g1
147	ldx [%g1], %o6
148
149	mov 0x2, %o5 ! L2_CSR_REG<1>=1 => DM mode
150
151	ldxa [%g0]ASI_INTR_ID, %o4 ! get the thread id; for core-portable
152	sllx %o4, 15, %o4 ! L2_CSR_REG<21:15> = ERROR_STEER
153
154	or %o5, %o4, %o5
155
156	or %o6, %o5, %o6
157
158	stx %o6, [%g1]
159	membar 0x40
160
161
162	store_to_L2_way0:
163	setx 0x2200aa00, %l0, %g2 ! bits [21:18] select way
164	add %g2, L2_BANK_ADDR, %g2
165	stx %g5, [%g2]
166	stx %g5, [%g2+8]
167	membar #Sync
168
169	! Storing to same L2 way0 but different tag,this will write to mcu
170	write_mcu_channel_0:
171	setx 0x2100aa00, %l0, %g3 ! bits [21:18] select way
172	add %g3, L2_BANK_ADDR, %g3
173	stx %g5, [%g3]
174	stx %g5, [%g3+8]
175	membar #Sync
176
177
178	read_error_address_ch0:
179	ldx [%g2], %l1
180	membar #Sync
181
182	! Loop until gets first trap
183	set 0x100, %o2
184	loop_1:
185	dec %o2
186	cmp %o2, %g0
187	be test_fail
188	nop
189
190	nop
191	cmp %i0, 0x1
192	bne loop_1
193	nop
194
195	pass:
196	ba test_pass
197	nop
198
199
200
201	/************************************
202	Trap Handler
203	************************************/
204	My_Corrected_ECC_error_trap:
205	inc %i0
206
207	check_l2_ESR_0x63:
208	setx L2ES_PA0, %l6, %g1
209	ldx [%g1], %g2
210
211	setx L2_ESR_MASK, %g7, %g3
212	and %g2, %g3, %g4
213
214	check_DAC_0x63:
215	mov 0x1, %i1
216	sllx %i1, L2_VEC, %i2
217	sllx %i1, L2_DAC, %i3
218	or %i2, %i3, %i4
219
220	cmp %g4, %i4
221	bne %xcc, test_fail
222	nop
223
224	clear_l2_ESR_0x63:
225	setx L2_ES_W1C_VALUE, %g7, %g2
226	stx %g2, [%g1]
227	membar #Sync
228
229	check_l2_EAR_0x63:
230	setx L2EA_PA0, %g7, %g1
231	ldx [%g1], %g2
232	setx 0xffffffffffffffc0, %g7, %g5
233	and %g2, %g5, %g2
234	setx 0x2200aa00, %g7, %g3
235	cmp %g3, %g2
236	bne test_fail
237	nop
238
239	check_mcu_esr:
240	setx DRAM_ERR_STAT_REG, %g7, %g1
241	ldx [%g1], %g2
242
243	mov 0x1, %g6
244	sllx %g6, MCU_DAC, %g3
245	set 0x0002, %g5
246	or %g3, %g5, %g4
247
248	cmp %g4, %g2
249	bne %xcc, test_fail
250	nop
251
252
253	check_DESR_L2C_0x63:
254	ldxa [%g0] 0x4c, %g1
255	setx 0xff00000000000000, %g7, %g2
256	and %g1, %g2, %g3
257	setx 0x8900000000000000, %g7, %g4
258	cmp %g3, %g4
259	bne %xcc, test_fail
260	nop
261
262	retry
263	nop
264
265
266
267	/*******************************************************
268	* Exit code
269	*******************************************************/
270
271	test_pass:
272	ta T_GOOD_TRAP
273
274
275	test_fail:
276	ta T_BAD_TRAP
277
278
279