[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / vec / n2_ras_vec_mcu_dsu_trap.s

/*
* ========== Copyright Header Begin ==========================================
* 
* OpenSPARC T2 Processor File: n2_ras_vec_mcu_dsu_trap.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license 
* choice is available it will apply instead, Sun elects to use only 
* the General Public License version 2 (GPLv2) at this time for any 
* software where a choice of GPL license versions is made 
* available with the language indicating that GPLv2 or any later version 
* may be used, or where a choice of which version of the GPL is applied is 
* otherwise unspecified. 
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, 
* CA 95054 USA or visit www.sun.com if you need additional information or 
* have any questions. 
*
* 
* ========== Copyright Header End ============================================
*/
#define H_HT0_Sw_Recoverable_Error_0x40	 My_Recoverable_Sw_error_trap

#define MAIN_PAGE_NUCLEUS_ALSO
#define MAIN_PAGE_HV_ALSO


#define	 TEST_DATA1	    0x2000200081c3e008

#ifdef MCU0
#define L2_BANK_ADDR	    0x0
#define MCU_BANK_ADDR	    0x0
#define	 DRAM_ERR_INJ_REG   0x8400000290
#define	 DRAM_ERR_STAT_REG  0x8400000280
#define	 DRAM_ERR_ADDR_REG  0x8400000288
#define	 DRAM_SCRB_FREQ_REG 0x8400000018
#define	 DRAM_SCRB_ENB_REG  0x8400000040
#define	 L2_ERR_STAT_REG    0xAB00000000
#endif

#ifdef MCU1
#define L2_BANK_ADDR	    0x80
#define MCU_BANK_ADDR	    0x80
#define	 DRAM_ERR_INJ_REG   0x8400001290
#define	 DRAM_ERR_STAT_REG  0x8400001280
#define	 DRAM_ERR_ADDR_REG  0x8400001288
#define	 DRAM_SCRB_FREQ_REG 0x8400001018
#define	 DRAM_SCRB_ENB_REG  0x8400001040
#define	 L2_ERR_STAT_REG    0xAB00000080
#endif

#ifdef MCU2
#define L2_BANK_ADDR	    0x100
#define MCU_BANK_ADDR	    0x100
#define	 DRAM_ERR_INJ_REG   0x8400002290
#define	 DRAM_ERR_STAT_REG  0x8400002280
#define	 DRAM_ERR_ADDR_REG  0x8400002288
#define	 DRAM_SCRB_FREQ_REG 0x8400002018
#define	 DRAM_SCRB_ENB_REG  0x8400002040
#define	 L2_ERR_STAT_REG    0xAB00000100
#endif

#ifdef MCU3
#define L2_BANK_ADDR	    0x180
#define MCU_BANK_ADDR	    0x180
#define	 DRAM_ERR_INJ_REG   0x8400003290
#define	 DRAM_ERR_STAT_REG  0x8400003280
#define	 DRAM_ERR_ADDR_REG  0x8400003288
#define	 DRAM_SCRB_FREQ_REG 0x8400003018
#define	 DRAM_SCRB_ENB_REG  0x8400003040
#define	 L2_ERR_STAT_REG    0xAB00000180
#endif


#include "hboot.s"
#include "asi_s.h"
#include "err_defines.h"


.text
.global  main
.global	 My_Recoverable_Sw_error_trap


main:
  ta T_CHANGE_HPRIV
  clr	%o0
  clr	%o1

disable_l1:
  ldxa  [%g0] ASI_LSU_CONTROL, %l0
  ! Remove the lower 2 bits (I-Cache and D-Cache enables)
  andn  %l0, 0x3, %l0
  stxa  %l0, [%g0] ASI_LSU_CONTROL

set_DRAM_scrub_frequency:
  setx	DRAM_SCRB_FREQ_REG, %l0, %l1
  mov	0x1, %l0
  stx	%l0, [%l1]
  membar #Sync


enable_err_reporting:
  setx L2EE_PA0, %l0, %l1
  add   %l1, L2_BANK_ADDR, %l1
  ldx	[%l1], %l2
  mov	0x3, %l0
  or	%l2, %l0, %l2
  stx	%l2, [%l1]
  membar #Sync

set_DRAM_error_inject_ch0:
  set   0x606, %l1                ! ECC Mask (1-bit error)
  mov   0x1, %l2 		
  sllx  %l2, DRAM_EI_SSHOT, %l3
  Or    %l1, %l3, %l1           ! Set single shot ; 
  mov   0x1, %l2
  sllx  %l2, DRAM_EI_ENB, %l3
  or    %l1, %l3, %l1           ! Enable error injection for the next write
  setx  DRAM_ERR_INJ_REG, %l3, %g6 
!  add   %g6, MCU_BANK_ADDR, %g6
  stx   %l1, [%g6]
  membar 0x40

store_to_L2:
  setx  TEST_DATA1, %l0, %g5


set_L2_Directly_Mapped_Mode_errorsteer:
        setx    L2CS_PA0, %l6, %g1
	add	%g1, L2_BANK_ADDR, %g1
        ldx     [%g1], %o6

        mov     0x2, %o5                ! L2_CSR_REG<1>=1 => DM mode

        ldxa    [%g0]ASI_INTR_ID, %o4   ! get the thread id; for core-portable
        sllx    %o4, 15, %o4            ! L2_CSR_REG<21:15> = ERROR_STEER

        or      %o5, %o4, %o5

        or      %o6, %o5, %o6

        stx     %o6, [%g1]
        membar  0x40


store_to_L2_way0:
  setx  0x002000, %l0, %g2  ! bits [21:18] select way
  add   %g2, L2_BANK_ADDR, %g2
  stx %g5, [%g2]
  stx %g5, [%g2+8]
  membar #Sync

! Storing to same L2 way0 but different tag,this will write to mcu
write_mcu_channel_0:
  setx  0x21002000, %l0, %g3 ! bits [21:18] select way
  add   %g3, L2_BANK_ADDR, %g3
  stx %g5, [%g3]
!  stx %g5, [%g3+8]
  membar #Sync

enable_DRAM_scrub:
  setx	DRAM_SCRB_ENB_REG, %l0, %l1
  mov	0x1, %l0
  stx	%l0, [%l1]
  membar #Sync

        setx    0x22002000, %l0, %g3 ! bits [21:18] select way
        add     %g3, L2_BANK_ADDR, %g3  ! 01/07/07: cause fill from the appropreate mcu
	clr	%i5
Nops:
	cmp	%o0, %g0
	bne	%xcc, check_error_trap
	nop
 
	ldx	[%g3], %g1 ! cause  a fill 
        nop; nop; nop
        nop; nop; nop
        nop; nop; nop
        nop; nop; nop
        nop; nop; nop
        nop; nop; nop
        nop; nop; nop
        nop; nop; nop
        nop; nop; nop
        nop; nop; nop
        nop; nop; nop
        nop; nop; nop

	add	%g3, 0x200, %g3 
	inc	%i5
	cmp	%i5, 0x200
	bne	Nops
	nop

   
check_error_trap:
 setx	EXECUTED, %l1, %l0
  cmp	%o0, %l0
  bne	test_fail
  nop

  ba	test_pass
  nop


	/**************** Trap Handler *******************/
My_Recoverable_Sw_error_trap:
  ! Signal trap taken
  setx	EXECUTED, %l0, %o0
  ! save trap type value
  rdpr	%tt, %o1

check_l2esr:
	setx	L2_ERR_STAT_REG, %g7, %g1
	ldx   [%g1], %g2

	setx	0x2000000000, %g7, %g3		!DSU
	cmp	%g2, %g3
	bne	%xcc, test_fail
	nop

check_mcuesr:
        setx 	DRAM_ERR_STAT_REG, %g7, %g1
        ldx   	[%g1], %g2

        setx    0x0400000000000606, %g7, %g3	!SYND =0x606; DSU
        cmp     %g2, %g3
        bne     %xcc, test_fail
        nop

check_DSFSR:
	set  	0x18, %g3
	ldxa  	[%g3] 0x58, %g2
	cmp  	%g0, %g2
	bne  	test_fail
	nop

check_DESR:
	ldxa	[%g0] 0x4c, %g2
	setx    0xb000000000000000, %g7, %g3   		  ! <63>=f=1; <61>=S=1; 60:56=10000
	cmp	%g2, %g3
	bne	%xcc, test_fail
	nop

check_mcu_EAR:
!	setx	0x8400000288, %l1, %g1
	setx	DRAM_ERR_ADDR_REG, %g7, %g1
	ldx	[%g1], %g2
	setx	0x2000, %l1, %g3
	cmp	%g2, %g3
!	bne	%xcc, test_fail
	nop

	done	
  	nop

  ba    test_pass
  nop

/*******************************************************
 * Exit code
 *******************************************************/

test_pass:
ta  T_GOOD_TRAP


test_fail:
ta  T_BAD_TRAP
Commit	Line	Data
86530b38 AT	1	/*
	2	* ========== Copyright Header Begin ==========================================
	3	*
	4	* OpenSPARC T2 Processor File: n2_ras_vec_mcu_dsu_trap.s
	5	* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
	6	* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
	7	*
	8	* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License as published by
	12	* the Free Software Foundation; version 2 of the License.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	* For the avoidance of doubt, and except that if any non-GPL license
	24	* choice is available it will apply instead, Sun elects to use only
	25	* the General Public License version 2 (GPLv2) at this time for any
	26	* software where a choice of GPL license versions is made
	27	* available with the language indicating that GPLv2 or any later version
	28	* may be used, or where a choice of which version of the GPL is applied is
	29	* otherwise unspecified.
	30	*
	31	* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
	32	* CA 95054 USA or visit www.sun.com if you need additional information or
	33	* have any questions.
	34	*
	35	*
	36	* ========== Copyright Header End ============================================
	37	*/
	38	#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
	39
	40	#define MAIN_PAGE_NUCLEUS_ALSO
	41	#define MAIN_PAGE_HV_ALSO
	42
	43
	44	#define TEST_DATA1 0x2000200081c3e008
	45
	46	#ifdef MCU0
	47	#define L2_BANK_ADDR 0x0
	48	#define MCU_BANK_ADDR 0x0
	49	#define DRAM_ERR_INJ_REG 0x8400000290
	50	#define DRAM_ERR_STAT_REG 0x8400000280
	51	#define DRAM_ERR_ADDR_REG 0x8400000288
	52	#define DRAM_SCRB_FREQ_REG 0x8400000018
	53	#define DRAM_SCRB_ENB_REG 0x8400000040
	54	#define L2_ERR_STAT_REG 0xAB00000000
	55	#endif
	56
	57	#ifdef MCU1
	58	#define L2_BANK_ADDR 0x80
	59	#define MCU_BANK_ADDR 0x80
	60	#define DRAM_ERR_INJ_REG 0x8400001290
	61	#define DRAM_ERR_STAT_REG 0x8400001280
	62	#define DRAM_ERR_ADDR_REG 0x8400001288
	63	#define DRAM_SCRB_FREQ_REG 0x8400001018
	64	#define DRAM_SCRB_ENB_REG 0x8400001040
65	#define L2_ERR_STAT_REG 0xAB00000080
66	#endif
67
68	#ifdef MCU2
69	#define L2_BANK_ADDR 0x100
70	#define MCU_BANK_ADDR 0x100
71	#define DRAM_ERR_INJ_REG 0x8400002290
72	#define DRAM_ERR_STAT_REG 0x8400002280
73	#define DRAM_ERR_ADDR_REG 0x8400002288
74	#define DRAM_SCRB_FREQ_REG 0x8400002018
75	#define DRAM_SCRB_ENB_REG 0x8400002040
76	#define L2_ERR_STAT_REG 0xAB00000100
77	#endif
78
79	#ifdef MCU3
80	#define L2_BANK_ADDR 0x180
81	#define MCU_BANK_ADDR 0x180
82	#define DRAM_ERR_INJ_REG 0x8400003290
83	#define DRAM_ERR_STAT_REG 0x8400003280
84	#define DRAM_ERR_ADDR_REG 0x8400003288
85	#define DRAM_SCRB_FREQ_REG 0x8400003018
86	#define DRAM_SCRB_ENB_REG 0x8400003040
87	#define L2_ERR_STAT_REG 0xAB00000180
88	#endif
89
90
91	#include "hboot.s"
92	#include "asi_s.h"
93	#include "err_defines.h"
94
95
96	.text
97	.global main
98	.global My_Recoverable_Sw_error_trap
99
100
101	main:
102	ta T_CHANGE_HPRIV
103	clr %o0
104	clr %o1
105
106	disable_l1:
107	ldxa [%g0] ASI_LSU_CONTROL, %l0
108	! Remove the lower 2 bits (I-Cache and D-Cache enables)
109	andn %l0, 0x3, %l0
110	stxa %l0, [%g0] ASI_LSU_CONTROL
111
112	set_DRAM_scrub_frequency:
113	setx DRAM_SCRB_FREQ_REG, %l0, %l1
114	mov 0x1, %l0
115	stx %l0, [%l1]
116	membar #Sync
117
118
119	enable_err_reporting:
120	setx L2EE_PA0, %l0, %l1
121	add %l1, L2_BANK_ADDR, %l1
122	ldx [%l1], %l2
123	mov 0x3, %l0
124	or %l2, %l0, %l2
125	stx %l2, [%l1]
126	membar #Sync
127
128	set_DRAM_error_inject_ch0:
129	set 0x606, %l1 ! ECC Mask (1-bit error)
130	mov 0x1, %l2
131	sllx %l2, DRAM_EI_SSHOT, %l3
132	Or %l1, %l3, %l1 ! Set single shot ;
133	mov 0x1, %l2
134	sllx %l2, DRAM_EI_ENB, %l3
135	or %l1, %l3, %l1 ! Enable error injection for the next write
136	setx DRAM_ERR_INJ_REG, %l3, %g6
137	! add %g6, MCU_BANK_ADDR, %g6
138	stx %l1, [%g6]
139	membar 0x40
140
141	store_to_L2:
142	setx TEST_DATA1, %l0, %g5
143
144
145
146	set_L2_Directly_Mapped_Mode_errorsteer:
147	setx L2CS_PA0, %l6, %g1
148	add %g1, L2_BANK_ADDR, %g1
149	ldx [%g1], %o6
150
151	mov 0x2, %o5 ! L2_CSR_REG<1>=1 => DM mode
152
153	ldxa [%g0]ASI_INTR_ID, %o4 ! get the thread id; for core-portable
154	sllx %o4, 15, %o4 ! L2_CSR_REG<21:15> = ERROR_STEER
155
156	or %o5, %o4, %o5
157
158	or %o6, %o5, %o6
159
160	stx %o6, [%g1]
161	membar 0x40
162
163
164	store_to_L2_way0:
165	setx 0x002000, %l0, %g2 ! bits [21:18] select way
166	add %g2, L2_BANK_ADDR, %g2
167	stx %g5, [%g2]
168	stx %g5, [%g2+8]
169	membar #Sync
170
171	! Storing to same L2 way0 but different tag,this will write to mcu
172	write_mcu_channel_0:
173	setx 0x21002000, %l0, %g3 ! bits [21:18] select way
174	add %g3, L2_BANK_ADDR, %g3
175	stx %g5, [%g3]
176	! stx %g5, [%g3+8]
177	membar #Sync
178
179	enable_DRAM_scrub:
180	setx DRAM_SCRB_ENB_REG, %l0, %l1
181	mov 0x1, %l0
182	stx %l0, [%l1]
183	membar #Sync
184
185	setx 0x22002000, %l0, %g3 ! bits [21:18] select way
186	add %g3, L2_BANK_ADDR, %g3 ! 01/07/07: cause fill from the appropreate mcu
187	clr %i5
188	Nops:
189	cmp %o0, %g0
190	bne %xcc, check_error_trap
191	nop
192
193	ldx [%g3], %g1 ! cause a fill
194	nop; nop; nop
195	nop; nop; nop
196	nop; nop; nop
197	nop; nop; nop
198	nop; nop; nop
199	nop; nop; nop
200	nop; nop; nop
201	nop; nop; nop
202	nop; nop; nop
203	nop; nop; nop
204	nop; nop; nop
205	nop; nop; nop
206
207	add %g3, 0x200, %g3
208	inc %i5
209	cmp %i5, 0x200
210	bne Nops
211	nop
212
213
214	check_error_trap:
215	setx EXECUTED, %l1, %l0
216	cmp %o0, %l0
217	bne test_fail
218	nop
219
220	ba test_pass
221	nop
222
223
224	/************** Trap Handler *****************/
225	My_Recoverable_Sw_error_trap:
226	! Signal trap taken
227	setx EXECUTED, %l0, %o0
228	! save trap type value
229	rdpr %tt, %o1
230
231	check_l2esr:
232	setx L2_ERR_STAT_REG, %g7, %g1
233	ldx [%g1], %g2
234
235	setx 0x2000000000, %g7, %g3 !DSU
236	cmp %g2, %g3
237	bne %xcc, test_fail
238	nop
239
240	check_mcuesr:
241	setx DRAM_ERR_STAT_REG, %g7, %g1
242	ldx [%g1], %g2
243
244	setx 0x0400000000000606, %g7, %g3 !SYND =0x606; DSU
245	cmp %g2, %g3
246	bne %xcc, test_fail
247	nop
248
249	check_DSFSR:
250	set 0x18, %g3
251	ldxa [%g3] 0x58, %g2
252	cmp %g0, %g2
253	bne test_fail
254	nop
255
256	check_DESR:
257	ldxa [%g0] 0x4c, %g2
258	setx 0xb000000000000000, %g7, %g3 ! <63>=f=1; <61>=S=1; 60:56=10000
259	cmp %g2, %g3
260	bne %xcc, test_fail
261	nop
262
263	check_mcu_EAR:
264	! setx 0x8400000288, %l1, %g1
265	setx DRAM_ERR_ADDR_REG, %g7, %g1
266	ldx [%g1], %g2
267	setx 0x2000, %l1, %g3
268	cmp %g2, %g3
269	! bne %xcc, test_fail
270	nop
271
272	done
273	nop
274
275	ba test_pass
276	nop
277
278	/*******************************************************
279	* Exit code
280	*******************************************************/
281
282	test_pass:
283	ta T_GOOD_TRAP
284
285
286	test_fail:
287	ta T_BAD_TRAP
288
289
290