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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / vec / n2_ras_vec_mcu_strm_SB_err.s
CommitLineData
86530b38
AT		 1/*
2* ========== Copyright Header Begin ==========================================
3*
4* OpenSPARC T2 Processor File: n2_ras_vec_mcu_strm_SB_err.s
5* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
6* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
7*
8* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
9*
10* This program is free software; you can redistribute it and/or modify
11* it under the terms of the GNU General Public License as published by
12* the Free Software Foundation; version 2 of the License.
13*
14* This program is distributed in the hope that it will be useful,
15* but WITHOUT ANY WARRANTY; without even the implied warranty of
16* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17* GNU General Public License for more details.
18*
19* You should have received a copy of the GNU General Public License
20* along with this program; if not, write to the Free Software
21* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22*
23* For the avoidance of doubt, and except that if any non-GPL license
24* choice is available it will apply instead, Sun elects to use only
25* the General Public License version 2 (GPLv2) at this time for any
26* software where a choice of GPL license versions is made
27* available with the language indicating that GPLv2 or any later version
28* may be used, or where a choice of which version of the GPL is applied is
29* otherwise unspecified.
30*
31* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
32* CA 95054 USA or visit www.sun.com if you need additional information or
33* have any questions.
34*
35*
36* ========== Copyright Header End ============================================
37*/
38#define MAIN_PAGE_NUCLEUS_ALSO
39#define MAIN_PAGE_HV_ALSO
40
41#define TEST_DATA1 0x2000200081c3e008
42
43#ifdef MCU0
44#define L2_BANK_ADDR 0x0
45#define MCU_BANK_ADDR 0x0
46#define DRAM_ERR_INJ_REG 0x8400000290
47#define DRAM_ERR_STAT_REG 0x8400000280
48#define DRAM_ERR_ADDR_REG 0x8400000288
49#define DRAM_SCRB_FREQ_REG 0x8400000018
50#define DRAM_SCRB_ENB_REG 0x8400000040
51#define L2_ERR_STAT_REG 0xAB00000000
52
53#define DRAM_FBR_CNT_REG_PA DRAM_FBR_CNT_REG_PA_0
54#define DRAM_ERR_CNT_REG_PA DRAM_ERR_CNT_REG_PA_0
55
56#define DRAM_FBD_ERR_SYND_REG_PA DRAM_FBD_ERR_SYND_REG_PA_0
57#define DRAM_FBD_INJ_ERR_SRC_REG_PA DRAM_FBD_INJ_ERR_SRC_REG_PA_0
58
59#define ERROR_ADDR 0x22000000
60#define WB_ADDR 0x24000000
61#define FILL_ADDR 0x26000000
62#endif
63
64#ifdef MCU1
65#define L2_BANK_ADDR 0x80
66#define MCU_BANK_ADDR 0x80
67#define DRAM_ERR_INJ_REG 0x8400001290
68#define DRAM_ERR_STAT_REG 0x8400001280
69#define DRAM_ERR_ADDR_REG 0x8400001288
70#define DRAM_SCRB_FREQ_REG 0x8400001018
71#define DRAM_SCRB_ENB_REG 0x8400001040
72#define L2_ERR_STAT_REG 0xAB00000080
73#define DRAM_FBR_CNT_REG_PA DRAM_FBR_CNT_REG_PA_1
74#define DRAM_ERR_CNT_REG_PA DRAM_ERR_CNT_REG_PA_1
75
76#define DRAM_FBD_ERR_SYND_REG_PA DRAM_FBD_ERR_SYND_REG_PA_1
77#define DRAM_FBD_INJ_ERR_SRC_REG_PA DRAM_FBD_INJ_ERR_SRC_REG_PA_1
78
79
80#define ERROR_ADDR 0x22000080
81#define WB_ADDR 0x24000080
82#define FILL_ADDR 0x26000080
83#endif
84
85#ifdef MCU2
86#define L2_BANK_ADDR 0x100
87#define MCU_BANK_ADDR 0x100
88#define DRAM_ERR_INJ_REG 0x8400002290
89#define DRAM_ERR_STAT_REG 0x8400002280
90#define DRAM_ERR_ADDR_REG 0x8400002288
91#define DRAM_SCRB_FREQ_REG 0x8400002018
92#define DRAM_SCRB_ENB_REG 0x8400002040
93#define L2_ERR_STAT_REG 0xAB00000100
94
95#define DRAM_FBR_CNT_REG_PA DRAM_FBR_CNT_REG_PA_2
96#define DRAM_ERR_CNT_REG_PA DRAM_ERR_CNT_REG_PA_2
97
98#define DRAM_FBD_ERR_SYND_REG_PA DRAM_FBD_ERR_SYND_REG_PA_2
99#define DRAM_FBD_INJ_ERR_SRC_REG_PA DRAM_FBD_INJ_ERR_SRC_REG_PA_2
100
101
102#define ERROR_ADDR 0x22000100
103#define WB_ADDR 0x24000100
104#define FILL_ADDR 0x26000100
105#endif
106
107#ifdef MCU3
108#define L2_BANK_ADDR 0x180
109#define MCU_BANK_ADDR 0x180
110#define DRAM_ERR_INJ_REG 0x8400003290
111#define DRAM_ERR_STAT_REG 0x8400003280
112#define DRAM_ERR_ADDR_REG 0x8400003288
113#define DRAM_SCRB_FREQ_REG 0x8400003018
114#define DRAM_SCRB_ENB_REG 0x8400003040
115#define L2_ERR_STAT_REG 0xAB00000180
116#define DRAM_FBR_CNT_REG_PA DRAM_FBR_CNT_REG_PA_3
117#define DRAM_ERR_CNT_REG_PA DRAM_ERR_CNT_REG_PA_3
118
119#define DRAM_FBD_ERR_SYND_REG_PA DRAM_FBD_ERR_SYND_REG_PA_3
120#define DRAM_FBD_INJ_ERR_SRC_REG_PA DRAM_FBD_INJ_ERR_SRC_REG_PA_3
121
122
123#define ERROR_ADDR 0x22000180
124#define WB_ADDR 0x24000180
125#define FILL_ADDR 0x26000180
126#endif
127
128
129#include "hboot.s"
130#include "asi_s.h"
131#include "err_defines.h"
132
133
134.text
135.global main
136
137
138main:
139 ta T_CHANGE_HPRIV
140 clr %o0
141 clr %o1
142
143get_th_id_o0:
144 ta T_RD_THID
145
146 cmp %o1, 0
147 be main_th_0
148 nop
149
150 cmp %o1, 1
151 be main_th_1
152 nop
153
154main_th_0:
155nop
156
157disable_l1:
158 ldxa [%g0] ASI_LSU_CONTROL, %l0
159 ! Remove the lower 2 bits (I-Cache and D-Cache enables)
160 andn %l0, 0x3, %l0
161 stxa %l0, [%g0] ASI_LSU_CONTROL
162
163
164
165! MSA 01/04/07: Set Continuous error Injection
166set_DRAM_error_inject_ch0:
167 mov 0x2, %l1 ! ECC Mask (1-bit error)
168! mov 0x1, %l2
169! sllx %l2, DRAM_EI_SSHOT, %l3
170! Or %l1, %l3, %l1
171 mov 0x1, %l2
172 sllx %l2, DRAM_EI_ENB, %l3
173 or %l1, %l3, %l1 ! Enable error injection for the next write
174 setx DRAM_ERR_INJ_REG, %l3, %g6
175 stx %l1, [%g6]
176 membar 0x40
177
178
179store_to_L2:
180 setx TEST_DATA1, %l0, %g5
181
182
183set_L2_Directly_Mapped_Mode_errorsteer:
184 setx L2CS_PA0, %l6, %g1
185 add %g1, L2_BANK_ADDR, %g1
186
187 ldx [%g1], %o6
188
189 mov 0x2, %o5 ! L2_CSR_REG<1>=1 => DM mode
190
191 ldxa [%g0]ASI_INTR_ID, %o4 ! get the thread id; for core-portable
192 sllx %o4, 15, %o4 ! L2_CSR_REG<21:15> = ERROR_STEER
193
194 or %o5, %o4, %o5
195
196 or %o6, %o5, %o6
197
198 stx %o6, [%g1]
199 membar 0x40
200
201 /*************** Make line dirty**************/
202 set 0x80, %g6
203 setx ERROR_ADDR, %l0, %g2
204store_1:
205 stx %g5, [%g2]
206 add %g2, 0x200, %g2 ! next index; same tag
207 dec %g6
208 cmp %g6, %g0
209 bne store_1
210 nop
211
212 /************ WB *********************/
213 set 0x80, %g6
214 setx WB_ADDR, %l0, %g2
215store_alias:
216 stx %g5, [%g2]
217 add %g2, 0x200, %g2 ! next index; same tag
218 dec %g6
219 cmp %g6, %g0
220 bne store_alias
221 nop
222
223
224 ba test_pass
225 nop
226
227
228 /**************** TH1 *******************/
229main_th_1:
230 nop
231
232set_inj_err_src_reg:
233 set INJ_ERR_SRC, %g1
234 setx DRAM_FBD_INJ_ERR_SRC_REG_PA, %l7, %g3
235 stx %g1, [%g3]
236 membar 0x40
237
238 set 0x1, %g1
239 sllx %g1, ERR_FIELD, %g2
240 setx SOC_EJR_REG, %l7, %g3
241 set 0x20, %g6
242set_ejr:
243 stx %g2, [%g3]
244 nop; nop; nop
245 nop; nop; nop
246 nop; nop; nop
247 nop; nop; nop
248 nop; nop; nop
249 nop; nop; nop
250 nop; nop; nop
251 nop; nop; nop
252 nop; nop; nop
253 nop; nop; nop
254 nop; nop; nop
255 nop; nop; nop
256 stx %g0, [%g3]
257 nop; nop; nop
258 nop; nop; nop
259 nop; nop; nop
260 nop; nop; nop
261 nop; nop; nop
262 nop; nop; nop
263 nop; nop; nop
264 nop; nop; nop
265 nop; nop; nop
266 nop; nop; nop
267 nop; nop; nop
268 nop; nop; nop
269
270 dec %g6
271 cmp %g6, %g0
272 bne %xcc, set_ejr
273 nop
274 membar 0x40
275
276/*******************************************************
277 * Exit code
278 *******************************************************/
279
280test_pass:
281ta T_GOOD_TRAP
282
283
284test_fail:
285ta T_BAD_TRAP
286
287
288
Full OpenSPARC design & verification tarball including full HDL.